CN114730322A

CN114730322A - Data searching system and data searching method

Info

Publication number: CN114730322A
Application number: CN201980102169.9A
Authority: CN
Inventors: 王锦
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-12-26
Filing date: 2019-12-26
Publication date: 2022-07-08
Also published as: WO2021128217A1

Abstract

The application discloses a data searching system and a data searching method, wherein the data searching system can comprise a controller, a first memory and a second memory, and the first memory is a Content Addressing Memory (CAM); the controller may receive a target key entry and position indication information for finding target data, where the position indication information may indicate a target key region and a target AD region associated with the target data; the controller can use the target key table item to carry out matching search in the target key area to obtain the position of the matched table item; the controller may then obtain target data from the target AD region based on the matched entry location. In the embodiment of the application, the maximum storage length of the first storage and the maximum storage length of the second storage do not need to maintain a mapping relation, so that the storage density of the first storage and/or the second storage is favorably improved.

Description

Data searching system and data searching method

Technical Field

The application relates to the technical field of electronic science, in particular to a data searching system and a data searching method.

Background

The branch accelerator is used to provide branch acceleration assist functions for processors that support multiple threads. Generally, a branch accelerator includes a first memory and a second memory. The first memory is used for storing a plurality of key table entries (entries) which may exist in a plurality of keys (keys) of the conditional instruction. The second memory is used for storing a plurality of Associated Data (AD) which are in one-to-one correspondence with the plurality of key table entries.

Generally, the key entries of each conditional instruction are indexed by a plurality of positions to be in one-to-one correspondence with the AD data of the conditional instruction in the second memory. The plurality of position indexes may indicate storage addresses of the plurality of AD data in the second memory, respectively.

The processor may send the target key entry to the branch accelerator when it runs to the target conditional instruction. The branch accelerator can search the storage position of the target key entry from the first storage, and further obtain a target position index corresponding to the target key entry according to the mapping relation of the maximum storage length between the first storage and the second storage. Thereafter, the branch accelerator may acquire target data from the plurality of AD data stored in the second memory according to the target position index. The branch accelerator may then send the target data to the processor. The processor can process other threads in parallel during the execution of the actions by the branch accelerator, and after target data returned by the branch accelerator is received, the processor continues to execute the thread where the target conditional instruction is located according to the target data, so that branch acceleration is realized.

However, there may be differences in the length of key entries between different conditional instructions. When the data length difference of the key entry is large, since the mapping relationship needs to be maintained between the maximum storage length of the first storage and the maximum storage length of the second storage, the storage resources in the first storage and/or the second storage are wasted, and the storage density of the first storage and/or the second storage is not high.

For example, the maximum storage length of the first memory is 40 bits, and the second memoryHas a maximum storage length of 16 bits. Suppose that the first memory is configured with 40 x 20 bits²Wherein, the storage width of the storage space is 20 bits. Then, according to the mapping relationship, the second memory will be configured with 16 × 20 bits²The storage space of (2). If the first memory stores both key entries with a length of 40 bits and key entries with a length of 80 bits, each key entry with a length of 80 bits occupies a storage width of 2 bits. Each 80-bit key table entry only corresponds to one AD data actually, and only the storage space with the storage width of 1bit in the second storage is occupied. In this case, each key entry of 80 bits will waste the storage space of 1bit storage width in the second storage.

For another example, the maximum storage length of the first memory is configured to be 80 bits, and the maximum storage length of the second memory is 16 bits. In this case, when the first memory stores both the 40-bit key entry and the 80-bit key entry, although the storage resources of the second memory can be fully utilized, each 40-bit key entry in the first memory will occupy 80 × 1bit²The memory space in the first memory is thus wasted again.

In summary, the storage density of the memory (the first memory and/or the second memory) in the current branch accelerator is not high, and further research is needed.

Disclosure of Invention

The application provides a data searching system and a data searching method, which are used for improving the storage density of a memory in the data searching system.

In a first aspect, an embodiment of the present application provides a data lookup system, where the data lookup system may be a branch accelerator or a chip integrated with a branch accelerator. For example, the data search system provided in the embodiment of the present application may include: the Memory device comprises a controller, a first Memory and a second Memory, wherein the first Memory is a Content Addressable Memory (CAM); the first memory comprises a plurality of key areas, wherein each key area comprises a plurality of key table entries; the second memory includes a plurality of associated data AD areas, wherein each AD area includes a plurality of AD data; the controller may receive a target key entry and position indication information for finding target data, where the position indication information may indicate a target key region and a target AD region associated with the target data; the controller can use the target key table item to carry out matching search in the target key area to obtain the position of the matched table item; the controller may then obtain target data from the target AD region based on the matched entry location.

In the embodiment of the application, since the position indication information may indicate the target key area, the controller may determine the target key area from the first storage according to the position indication information, and further may obtain a relative position of the target key entry in the target key area, that is, a matched entry position. In the embodiment of the present application, the position indication information may indicate the target AD area, and thus the controller may determine the target AD area from the second memory according to the position indication information. Since the first memory is a CAM memory in the embodiment of the present application, the matching entry position of the target key entry in the target key area may be equivalent to the relative position of the target data in the target AD area. Further, the controller may obtain target data from the target AD region based on the matched entry position. In the embodiment of the application, the controller does not need to calculate the position index of the target data according to the mapping relationship between the maximum storage length of the first storage and the maximum storage length of the second storage, so that the storage spaces of the first storage and the second storage can be flexibly configured according to an actual application scene, and the storage density of the first storage and/or the second storage is improved under the condition that the lengths of key entries in the first storage are inconsistent.

In one possible implementation, the target key entry may be used to execute the target conditional instruction. The data search system provided by the embodiment of the application further includes a processor, where the processor may obtain the position indication information according to configuration information of the first memory and the second memory and a target conditional instruction, where the configuration information includes a plurality of conditional instructions, a plurality of key regions, and a plurality of AD regions, a key region corresponding to the target conditional instruction is the target key region, and an AD region corresponding to the target conditional instruction is the target AD region; the processor further sends the target key entry and the position indication information to the controller. In this case, the controller, the first memory and the second memory may act as a branch accelerator providing a processor with an auxiliary function of branch acceleration.

In one possible implementation, the controller may also send the target data to the processor. After receiving the target data, the processor may continue to execute the target conditional instruction according to the target data. For example, in the embodiment of the present application, the target data may be an instruction counter, the target conditional instruction includes a plurality of branch instructions, and the processor may obtain a branch instruction corresponding to the target data from among the target conditional instructions, and continue to execute the branch instruction.

In one possible implementation, the processor may also receive the above-mentioned configuration information. Specifically, the memory spaces of the first memory and the second memory may be configured by a device in which a compiler is installed according to a plurality of conditional instructions that are likely to be executed by the processor. The device in which the compiler is installed may be the processor itself, or may be another device besides the processor, which is not limited in this embodiment of the present application. When the storage spaces of the first memory and the second memory are configured by other devices except the processor, the device may transmit configuration information of the first memory and the second memory to the processor, and the processor may instruct the controller to search for data according to the received configuration information.

In a possible implementation manner, the configuration information may further include depth information of a plurality of key areas; the processor can also acquire the depth information of the target key area according to the configuration information and send the depth information to the controller; the controller may further determine the target key area from the first memory and the target AD area from the second memory, respectively, based on the position indication information and the depth information. Wherein, the depth information can be understood as the number of key entries in the target key area. The number of key entries in the target key region is the same as the number of AD data in the target AD region, and therefore the depth information can also be understood as the number of AD data in the target AD region. Therefore, when searching for the target key area, the controller may determine the target key area from the first memory and the target AD area from the second memory, respectively, based on the position indication information and the depth information.

In a possible implementation manner, the configuration information further includes storage lengths of the plurality of key areas; the processor can also determine the storage length corresponding to the target key area according to the configuration information, and send first length indication information to the controller, wherein the first length indication information can indicate the storage length of the target key area; the controller may determine the target key area from the first memory according to the position indication information, the depth information, and the first length indication information.

In one possible implementation, in each AD region, one or more AD data are located in the same row of memory cells of the second memory. The storage mode provided by the embodiment of the application is favorable for further improving the storage density of the second storage.

In a possible implementation manner, the configuration information further includes length information of each AD data in each AD area; the processor may further obtain an AD length message corresponding to the target AD area according to the configuration information, where the AD length message includes data length information of one or more pieces of AD data in the target AD area, and each piece of data length information is used to indicate a data length of the AD data corresponding to each piece of data length information; an AD length message is sent to the controller.

When one or more AD data are located in the same row of storage units of the second memory, the AD data located in the same row of storage units are difficult to distinguish, and the controller cannot acquire the target data from the target AD area. In view of this, in the embodiment of the present application, the processor sends an AD length message to the controller, so that the controller can distinguish the target data from other data according to the AD length message, and thus can acquire the target data.

In a possible implementation manner, the configuration information may further include a starting storage address of each key area, and a starting storage address of each AD area; the position indication information may include a start storage address of the target key area and a start storage address of the target AD area.

In a possible implementation manner, the controller may obtain, according to the matched entry position, a data length of the AD data before the target data in the AD length message; determining the initial storage address of the target data according to the initial storage address of the target AD area and the data length of AD data before the target data; and acquiring the target data from the target AD area according to the initial storage address of the target data.

In a possible implementation manner, the processor may further determine a data length of the target data according to the configuration information, and send second length indication information to the controller, where the second length indication information may indicate the data length of the target data; in this case, the controller may acquire the target data from the target AD area according to the data length of the target data based on the start storage address of the target data.

In a second aspect, an embodiment of the present application provides a data search method, which may be applied to the data search system provided in any one of the first aspects. Illustratively, the data search method provided by the embodiment of the present application mainly includes: the method comprises the steps that a controller receives a target key table entry and position indication information, wherein the target key table entry is used for searching target data, the position indication information is used for indicating a target key area which is associated with the target data in a first memory and a target AD area which is associated with the target data in a second memory, the first memory is a content addressing memory CAM, the first memory comprises a plurality of key areas, each key area comprises a plurality of key table entries, the second memory comprises a plurality of associated data AD areas, and each AD area comprises a plurality of AD data; the controller uses the target key table item to carry out matching search in the target key area to obtain the position of the matched table item; and the controller obtains target data from the target AD area according to the matched table entry position.

In a possible implementation manner, before the target key entry is used to execute the target conditional instruction, and the controller receives the target key entry and the location indication information used to search for the target data, the method further includes: the processor obtains position indication information according to configuration information of the first memory and the second memory and a target conditional instruction, wherein the configuration information comprises a plurality of conditional instructions, a plurality of key areas and a plurality of AD areas, the key area corresponding to the target conditional instruction is a target key area, and the AD area corresponding to the target conditional instruction is a target AD area; the processor sends the target key entry and the position indication information to the controller.

In a possible implementation manner, after the controller obtains the target data from the target AD area according to the matched entry position, the method further includes: the controller sends the target data to the processor.

In a possible implementation manner, before the processor obtains the position indication information according to the configuration information of the first memory and the second memory, and the target condition instruction, the method further includes: the processor receives configuration information.

In one possible implementation, the configuration information further includes depth information of the plurality of key regions; the controller uses the target key table item to perform matching search in the target key area, and before obtaining the position of the matched table item, the method further comprises the following steps: the processor acquires the depth information of the target key area according to the configuration information and sends the depth information to the controller; the controller determines a target key area from the first memory and a target AD area from the second memory based on the position indication information and the depth information.

In a possible implementation manner, the configuration information further includes storage lengths of the plurality of key areas; the controller uses the target key table item to perform matching search in the target key area, and before obtaining the position of the matched table item, the method further comprises the following steps: the processor determines the storage length corresponding to the target key area according to the configuration information, and sends first length indication information to the controller, wherein the first length indication information is used for indicating the storage length of the target key area; the controller determines a target key area from the first memory according to the position indication information and the depth information, and includes: the controller determines the target key area from the first memory according to the position indication information, the depth information, and the first length indication information.

In one possible implementation, in each AD region, one or more AD data are located in the same row of memory cells of the second memory.

In a possible implementation manner, the configuration information further includes length information of each AD data in each AD area; before the controller obtains the target data from the target AD region according to the matched entry position, the controller further includes: the processor acquires an AD length message corresponding to the target AD area according to the configuration information, wherein the AD length message comprises data length information of one or more AD data in the target AD area, and each data length information is used for indicating the data length of the AD data corresponding to each data length information; the processor sends an AD length message to the controller.

In a possible implementation manner, the configuration information further includes a starting storage address of each key area, and a starting storage address of each AD area; the position indication information includes a start storage address of the target key area and a start storage address of the target AD area.

In one possible implementation manner, the obtaining, by the controller, target data from the target AD area according to the matched entry position includes: acquiring the data length of AD data before the target data in the AD length message according to the matched table entry position; determining the initial storage address of the target data according to the initial storage address of the target AD area and the data length of AD data before the target data; and acquiring the target data from the target AD area according to the initial storage address of the target data.

In a possible implementation manner, before the controller obtains the target data from the target AD area according to the matched entry position, the method further includes: the processor determines the data length of the target data according to the configuration information and sends second length indication information to the controller, wherein the second length indication information is used for indicating the data length of the target data; according to the initial storage address of the target data, acquiring the target data from the target AD area, comprising: and the controller acquires the target data from the target AD area according to the initial storage address of the target data and the data length of the target data.

These and other aspects of the present application will be more readily apparent from the following description of the embodiments.

Drawings

Fig. 1 is a schematic structural diagram of a data searching system according to an embodiment of the present application;

fig. 2 is a schematic diagram of a storage structure of a first memory according to an embodiment of the present disclosure;

fig. 3 is a schematic view of a storage structure of a key area according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram illustrating a storage structure of a second memory according to an embodiment of the present disclosure;

fig. 5 is a schematic flow chart of a data searching method according to an embodiment of the present application;

fig. 6 is a schematic diagram illustrating a correspondence relationship between a data length and a length identifier according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of an AD length message according to an embodiment of the present application;

fig. 8 is a schematic diagram of a Kswitch instruction according to an embodiment of the present disclosure.

Detailed Description

The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail with reference to the accompanying drawings. The particular methods of operation in the method embodiments may also be applied to apparatus embodiments or system embodiments. It is to be noted that "at least one" in the description of the present application means one or more, where a plurality means two or more. In view of this, the "plurality" may also be understood as "at least two" in the embodiments of the present invention. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" generally indicates that the preceding and following related objects are in an "or" relationship, unless otherwise specified. In addition, it is to be understood that the terms first, second, etc. in the description of the present application are used for distinguishing between the descriptions and not necessarily for describing a sequential or chronological order.

It should be noted that the memory in the embodiments of the present application can be understood as a two-dimensional memory array, and the storage length of any data can be understood as the number of bits occupied by the data in the length direction of the memory array (the row direction of the memory array). The memory width corresponding to the memory length can be understood as the number of bits of data occupied in the width direction of the memory array (the column direction of the memory array). The storage length and storage width of any data define the storage space of the data. For convenience of description, the embodiments of the present application will be described with a × b bits²The size of the storage space is represented, wherein a represents the number of bits in the length direction of the storage space, i.e. the storage length, and b represents the number of bits in the width direction of the storage space, i.e. the storage width.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

Fig. 1 schematically illustrates a structural diagram of a data searching system provided by an embodiment of the present application. The data search system may be a branch accelerator, or may be a chip integrated with a branch accelerator, or a system on a chip, etc. For example, in the embodiment of the present application, the data lookup system may be a processing chip with a large computation amount, such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and the like, and the processor 100 and the branch accelerator 200 are integrated in the chip to increase the computation speed of the chip.

As shown in fig. 1, the data lookup system includes a controller 201, a first memory 202, and a second memory 203. The controller 201 is connected to the first memory 202 and the second memory 203, respectively, the controller 201 includes a control circuit of the first memory 202 and a control circuit of the second memory 203, and the controller 201 can search the first memory 202 and the second memory 203.

In the case where the data lookup system is a chip, or system-on-a-chip, integrated with a branch accelerator, as shown in fig. 1, the data lookup system may also include a processor 100. The processor 100 may be a logic circuit with arithmetic capabilities. Illustratively, the processor 100 may include an Arithmetic and Logic Unit (ALU), through which arithmetic and logic operations and other operation functions may be implemented.

In the embodiment of the present application, the processor 100 and the controller 201 may be interconnected through a control bus, so that information may be transferred between the processor 100 and the branch accelerator 200.

The processor 100 often needs to execute conditional instructions when performing arithmetic functions. Where the conditional instruction may include a plurality of branch instructions. Common conditional instructions are a switch instruction, a plurality of multi-level nested instructions composed of if and else (else), and so on. Taking a multi-layer nested instruction composed of a plurality of ifs and else as an example, the pseudo code of the instruction can be expressed as:

as can be seen from the pseudo code, the conditional instruction includes 4 key (key) entries (entries), which are key entries 1 to 4, respectively. Here, the key entry 4 may be understood as the only entry excluding the key entries 1 to 3, and thus is not directly shown in the embodiment of the present application. As shown in the above conditional branch instruction, the key entry 1 corresponds to the branch instruction 1, the key entry 2 corresponds to the branch instruction 2, the key entry 3 corresponds to the branch instruction 3, and the key entry 4(else) corresponds to the branch instruction 4.

Before the processor 100 executes the conditional instruction, the target key entry is often obtained first, for example, the processor 100 may generate the target key entry, or may receive the target key entry input by another device, which is not limited in this embodiment of the present application.

Thereafter, the processor 100 may execute a cmp (compare) instruction to match the target key entry with the key entries 1 to 4 one by one in sequence until the matching is successful. For example, if the target key entry is successfully matched with key entry 2, for example, the target key entry is key entry 2, the processor 100 may continue to execute branch instruction 2.

However, the computational resources of the processor 100 are wasted significantly during the execution of the CMP instruction. By adopting the data lookup system integrated with the branch accelerator, the operation pressure of the conditional instruction on the processor 100 can be saved, and the operation speed and the multithreading processing capability of the processor 100 can be improved.

For example, the controller 201 may receive a target key entry sent by the processor 100, and search the first memory 202 and the second memory 203 according to the received target key entry, so as to obtain target data corresponding to the target key entry.

The target data corresponding to the target key entry may be a target branch instruction corresponding to the target key entry in possible embodiments, or may also be a Program Counter (PC) corresponding to the target key entry and the target branch instruction, which is not limited in this embodiment. In the case that the target data is a PC, the processor 100 stores a plurality of branch instructions, and after receiving the target data returned by the controller 201, the processor 100 may read and execute a branch instruction corresponding to the target data, that is, a target branch instruction, from the stored branch instructions according to the target data.

Specifically, the first Memory 202 may be a Content Addressable Memory (CAM), which is currently more commonly a Ternary Content Addressable Memory (TCAM). The first memory 202 stores a plurality of groups (groups). Each group corresponds to a conditional instruction. And for each group, a plurality of key entries of the conditional instruction corresponding to the group are included. For example, assuming that the conditional instruction is a switch instruction, the storage structure of the first memory may be as shown in the following table one:

watch 1

As shown in table one, M groups, such as group 1, group2, … …, and group M, are stored in the first memory 202, where M is an integer greater than 1. M groups correspond to M switch instructions, for example, group 1 corresponds to switch instruction 1, group2 corresponds to switch instruction 2, and group M corresponds to switch instruction M.

For each switch instruction, the key of the switch instruction may have a plurality of key entries, and the key entries respectively correspond to a plurality of branch instructions of the switch instruction one to one. Taking switch instruction 1 in table one as an example, the key of switch instruction 1 includes 16 key entries (key entry 11, key entry 12, … …, key entry 116), and the 16 key entries correspond to the 16 branch instructions of switch instruction 1 one to one. switch instruction 2 through switch instruction M are the same and will not be described again.

Currently, each key entry in each group can be implemented by one-to-one correspondence between the position index and the AD data in the second storage 203. Taking the key entry 11 in the group 1 as an example, the key entry 11 may correspond to the AD data 11 in the second memory 203 through the position index 11, that is, the key entry 11 is stored in the first memory 202, the key entry 11 corresponds to the position index 11, the AD data 11 is stored in the second memory 203, and the AD data 11 also corresponds to the position index 11.

The correspondence between the key entry 11 and the position index 11 may be calculated by the controller 201 according to the storage address of the key entry 11 and the mapping relationship between the maximum storage length of the first storage 202 and the maximum storage length of the second storage 203. The correspondence between the position index 11 and the AD data 11 can be understood as that the position index 11 can indicate the storage address of the AD data 11 in the second memory 203, that is, the controller 201 can determine the storage address of the AD data 11 in the second memory 203 according to the position index 11, so that the AD data 11 can be read.

The processor 100, upon executing the conditional instruction, may send a target key entry to the branch accelerator 200, from which the controller 201 may look up the first memory 202. After the target key entry is hit, assuming that the key entry 11 hits the target key entry, the position index 11 is calculated according to the storage address of the key entry 11 in the first memory 202 and the mapping relationship between the maximum storage length of the first memory 202 and the maximum storage length of the second memory 203. The controller 201 reads the AD data 11 from the second memory 203 according to the position index 11.

The controller 201 returns the AD data 11 to the processor 100, and the processor 100 may obtain a branch instruction corresponding to the AD data 11 according to the AD data 11 and continue to execute the branch instruction. As can be seen from the above process, the branch accelerator 200 may replace the processor 100 to determine the AD data corresponding to the target key entry, so that the process of executing the CMP instruction by the processor 100 may be omitted, which is beneficial to reducing the operation pressure of the processor 100 when executing the conditional instruction.

It should be appreciated that for the same switch instruction, the data length of the key entries therein is the same. The data length of the key entry may be different for different switch instructions. Since a mapping relationship needs to be maintained between the maximum storage length of the first storage 202 and the maximum storage length of the second storage 203 at present, the length of the key entry stored in the first storage 202 is not short, which will result in a waste of storage resources of the first storage 202 and/or the second storage 203, and the storage density of the first storage 202 and/or the second storage 203 is yet to be further improved.

Specifically, the first memory 202 is configured with a maximum storage length that limits the storage length of a key entry in the first memory 202. For example, in the case that the maximum storage length is 40 bits, for a key entry whose data length is not greater than 40 bits, 40 × 1 bits are occupied²The storage space of (a). For key table entry of 80 bits, 40 × 2 bits are occupied²The storage space of (2).

The second memory 203 is also configured with a maximum storage length, which limits the maximum storage length of the AD data in the second memory 203, and a 1-bit storage width can only store 1 piece of AD data.

When key entries with inconsistent data lengths are stored in the first memory 202, the mapping relationship between the maximum storage length of the first memory 202 and the maximum storage length of the second memory 203 will limit further increase of the storage density of the first memory 202 and/or the second register.

Illustratively, for example, the data length of the key entries 11 to 116 in group 1 shown in table one is 40 bits, and the length of the key entries 21 to 216 in group2 is 80 bits.

It is assumed that the maximum storage length of the first memory 202 is 40 bits and the maximum storage length of the second memory 203 is 16 bits, that is, the storage length of every 40 bits in the first memory 202 can be mapped to the storage length of 16 bits in the second memory 203. The first memory 202 is configured with 2000 bits²The maximum storage width is 50 bits, so that 2000-bit key table data can be stored, and correspondingly, 800 bits are configured in the second storage 203²(16×50bit ²) The storage space of (2).

In this case, the group 1 is mapped with 16 × 16 bits in the second memory 203 according to the above mapping relationship²The group2 is mapped with 16 x 32bit in the second memory 203²The storage space of (2). As can be seen from Table I, group 1 and group2 both include 16 key entries, i.e., group2 only needs to use 16 × 16 bits of the second memory 203²The storage space of (2). Therefore, a part of the storage resources in the second memory 203 is wasted, resulting in a low storage density of the second memory 203.

Further, it is assumed that the maximum storage length of the first memory 202 is 80 bits, and the maximum storage length of the second memory 203 is 16 bits. For example, the second memory 203 is configured with 800 bits²(16 x 50bit2), the first memory 202 is configured with 4000 bits²(80×50bit ²) The storage space of (2).

In this case, according to the above-mentioned mapIn the second memory 203, group 1 is mapped with 16 × 16 bits²The group2 is mapped with 16 x 16 bits in the second memory 203²The storage space of (2). Although the storage resources of the second memory 203 are not wasted, the total amount of group 1 data in the first memory 202 is 40 × 16 bits, but it occupies 80 × 16 bits²The storage space of the first memory 202 is wasted, and the storage resource of the first memory 202 is low.

In summary, the storage density of the memories (the first memory 202 and/or the second memory 203) in the current data lookup system is yet to be further improved. In view of this, the embodiment of the present application provides a data searching system, and even if the maximum storage length of the first storage 202 and the maximum storage length of the second storage 203 no longer need to maintain a mapping relationship, the controller 201 can search for the target data corresponding to the target key entry, so that the storage structures of the first storage 202 and the second storage 203 can be configured more flexibly, and therefore, the embodiment of the present application is beneficial to improving the storage density of the first storage 202 and/or the second storage 203.

In one possible example, as shown in fig. 2, in the embodiment of the present application, the first storage 202 stores a plurality of key areas (key areas A, B, C, D, XX and YY), and each key area includes a plurality of key entries. In a possible implementation manner, the plurality of key areas correspond to the plurality of conditional instructions, and it should be noted that any one of one-to-one, one-to-many, and many-to-one correspondence relationships may be used between the plurality of key areas and the plurality of conditional instructions.

Illustratively, one-to-many is understood to mean that one key region corresponds to a plurality of conditional instructions. For example, multiple conditional instructions have the same key entry, in which case, multiple conditional instructions may correspond to the same key region. It should be noted that a plurality of conditional instructions corresponding to the same key area may have different branch instructions, that is, a plurality of conditional instructions corresponding to the same key area, or may correspond to different AD areas, respectively.

Many-to-one can be understood as multiple key regions corresponding to the same conditional instruction. For example, a plurality of key entries of a conditional instruction may be stored in a plurality of key areas.

One-to-one can be understood as one key area corresponding to one conditional instruction. For example, in fig. 2, the key area a corresponds to the instruction a, the key area B corresponds to the instruction B, the key area C corresponds to the instruction C, the key area D corresponds to the instruction D, the key area XX corresponds to the instruction XX, and the key area YY corresponds to the instruction YY, where the instruction a, the instruction B, the instruction C, the instruction D, the instruction XX, and the instruction YY are all conditional instructions.

The second memory 203 stores a plurality of Associated Data (AD) areas, each of which includes a plurality of AD data. In a possible implementation manner, the plurality of AD regions correspond to the plurality of key regions in the first memory 202, and it should be noted that there may be any one of a one-to-one correspondence, a one-to-many correspondence, and a many-to-one correspondence between the plurality of AD regions and the plurality of key regions.

Illustratively, one-to-many may be understood as one AD region corresponding to a plurality of key regions. For example, a plurality of conditional instructions have different key entries but the same branch instruction, in which case, the key regions corresponding to the conditional instructions may correspond to the same AD region.

Many-to-one can be understood as multiple AD regions corresponding to the same key region. For example, multiple conditional instructions have the same key entry but different branch instructions, in which case the multiple conditional instructions may correspond to the same key region, but the key region may correspond to multiple AD regions.

One-to-one can be understood as one AD region corresponding to one key region. For example, in fig. 2, key region a corresponds to AD region a, key region B corresponds to AD region B, key region C corresponds to AD region C, key region D corresponds to AD region D, key region XX corresponds to AD region XX, and key region YY corresponds to AD region.

For convenience of understanding, unless otherwise specified, the embodiments of the present application are described below with reference to a one-to-one correspondence relationship among a plurality of conditional instructions, a plurality of key areas, and a plurality of AD areas. Other scenarios of correspondence may be equally applicable.

Illustratively, the key area a stores N key entries of the instruction a, where N is an integer greater than or equal to N. The AD area a stores N AD data of the instruction a, which correspond one-to-one to N branch instructions of the instruction a.

In a possible implementation manner, the ith key entry in the key area a corresponds to the ith AD data in the AD area a, and i is an integer in [1, N ]. That is to say, the N key entries in the key area a correspond to the N AD data in the AD area a one-to-one, and the relative position of the ith key entry in the key area a is the same as the relative position of the ith AD data in the AD area a.

It can also be understood that the N key entries and the N AD data are stored in the key area a and the AD area a, respectively, according to the same storage sequence. For example, fig. 3 exemplarily shows the storage order of 8 key entries in the key area a. As shown in fig. 3, the key area a includes 8 key entries, and the 8 key entries are sequentially stored according to the sequence from a1 to A8. Fig. 4 exemplarily shows a storage order of 8 AD data (AD data 1 to 8) in the AD area a, and as shown in fig. 4, the 8 AD data of the AD area a are sequentially stored in the order of 1 to 8. The AD data 1 to 8 sequentially correspond to the key entries a1 to A8, that is, the key entry a1 corresponds to the AD data 1, the key entry a2 corresponds to the AD data 2, and so on.

It should be understood that the above-described storage order is defined on the basis of the reading order of the first memory 202 and the second memory 203. For example, the reading order of the first memory 202 and the second memory 203 is from left to right, from top to bottom, in which case the first memory 202 shown in fig. 3 and the second memory 203 shown in fig. 4 have the same storing order. It is understood that the reading order of the first memory 202 and the second memory 203 may also be from right to left, from bottom to top, and so on, which is not listed again in the embodiments of the present application.

The corresponding relationship between other key regions and the AD region is the same, and will not be described again. In addition, there may be some unused area in the second memory 203.

It should be noted that, in the embodiment of the present application, the processor 100 may instruct the controller 201 to search for data according to the first memory 202 and the second memory 203. Specifically, in the embodiment of the present application, the processor 100 may configure the storage structures of the first memory 202 and the second memory 203, or may configure the storage structures of the first memory 202 and the second memory 203 by other devices. For example, the storage structures of the first memory 202 and the second memory 203 may be configured by other devices installed with a compiler, in which case the devices may transmit the configuration information of the first memory 202 and the second memory 203 to the processor 100, so that the processor 100 may instruct the controller 201 to search for data according to the configuration information.

For example, as shown in fig. 5, the data searching method provided in the embodiment of the present application mainly includes the following steps:

s501: the processor 100 sends the target key entry and the position indication information to the controller 201.

The target key entry may be a key entry for executing the target conditional instruction. In the embodiment of the present application, the position indication information may indicate the target key area and the target AD area. The target key area may be understood as a key area corresponding to the target conditional instruction in the first memory 202, and the target AD area may be understood as an AD area corresponding to the target key area in the second memory.

In one possible implementation manner, the configuration information includes a correspondence relationship among a plurality of conditional instructions, a plurality of key areas, and a plurality of AD areas. The processor 100 may determine, according to the configuration information, that the key region corresponding to the target conditional instruction is a target key region, and the AD region corresponding to the target conditional instruction is a target AD region. Since the position indication information in the embodiment of the present application may directly indicate the target key area and the target AD area, even if there is not a one-to-one correspondence relationship among the conditional instructions, the plurality of key areas, and the plurality of AD areas, it does not affect the controller 201 to search for the target data according to the position indication information.

S502: the controller 201 uses the target key entry to perform matching search in the target key region, and obtains the position of the matched entry. In the embodiment of the present application, the matched entry position may be understood as a relative position of the target key entry in the target key area, and may also be understood as a storage sequence of the target key entry in the target key area.

S503: the controller 201 obtains the target data from the target AD area according to the matched entry position. In the embodiment of the application, the relative position of the ith key entry in the target key area is the same as the relative position of the ith AD data in the target AD area, so that the AD data corresponding to the target key entry, that is, the target data, can be obtained from the matched entry position in the target AD area according to the matched entry position.

Generally, after obtaining the target data, the controller 201 may continue to execute S504 to return the target data to the processor 100. So that the processor 100 may continue to execute the target branch instruction corresponding to the target data.

Next, the position indication information provided by the embodiments of the present application is further exemplified. In this embodiment of the application, the position indication information may include the area identifiers of the target key area and the target AD area, or may include starting storage addresses of a plurality of key areas and starting storage addresses of a plurality of AD areas. That is, the processor 100 may indicate the target key area and the target AD area to the controller 201 by the start memory address.

For example, the correspondence relationship between the plurality of conditional instructions, the starting storage addresses of the plurality of key regions, and the starting storage addresses of the plurality of AD regions may be as shown in table two below:

watch two

Taking instruction a as an example, instruction a corresponds to key area a and AD area a, and as shown in table two, the initial storage address of key area a is address a, and the initial storage address of AD area a is address a. The location indication information corresponding to instruction a may indicate address a and address a.

For example, if the instruction B corresponds to the key area B and the AD area B, the start memory address of the key area B is the address B, and the start memory address of the AD area B is the address B, as shown in table two. The position indication information corresponding to the instruction B may indicate an address B and an address B. In table two, the corresponding relationship between other conditional instructions and the initial storage address can refer to instruction a and instruction B, which is not described again.

In view of this, the processor 100 may acquire the starting storage addresses of the target key area and the target AD area according to the configuration information, and directly indicate the starting storage addresses of the target key area and the target AD area to the controller 201 through the position indication information. So that the controller 201 can directly determine the storage locations of the target key area and the target AD area according to the location indication information.

Assuming that the target key area is a key area a, as shown in fig. 3, the storage address of the upper left bit of the key area a is ad11, the storage address of the upper right bit is ad18, the storage address of the lower left bit is ad81, and the storage address of the lower right bit is ad 88. The key area a includes 8 key entries, and thus, the depth information of the key area a is 8. The starting memory address of key region a may be any one of ad11, ad18, ad81, and ad88 in fig. 3. The same reason for the starting position information of the AD area a is not repeated.

The controller 201 may determine the target key area from the first memory 202 according to the starting storage address of the target key area, and further determine the table entry position of the target key table entry matching in the target key area.

For example, the controller 201 may match the search target key region starting from the starting storage address of the target key region, thereby determining the matching entry position of the target key entry in the target key region. For example, the target key area is the key area a shown in fig. 3, the controller 201 may sequentially match the target key entry with the key entries a1 to a8 from the start storage address (address a is ad11) of the target key area, and assuming that the target key entry is successfully matched with the key entry a5, it may also be understood that the target key entry is the key entry a5, the matching entry position of the target key entry in the target key area (key area a) may be determined to be 5.

The controller 201 may then determine the target AD area from the second memory 203 according to the starting storage address of the target AD area, and further obtain the target data from the target AD area according to the matched entry position. For example, the controller 201 may determine AD data whose relative position coincides with the matching entry position as target data, starting from the start storage address of the target AD area.

For example, assuming that the target AD area is the AD area a, the controller 201 may determine the 5 th AD data since then as the target data, starting from the starting storage address (address a) of the target AD area, and thus the controller 201 may determine the 5 th AD data (AD data 5) in the AD area a as the target data.

As can be seen from the flow shown in fig. 5, in the embodiment of the present application, the controller 201 may determine the target key area from the first memory 202 directly according to the position indication information, and determine the target AD area from the second memory 203. And obtaining target data from the target AD area by using the matched table entry position of the target key table entry in the target key area. In the embodiment of the present application, the controller 201 does not need to calculate the position index of the target data according to the mapping relationship between the maximum storage length of the first storage 202 and the maximum storage length of the second storage 203, so that the storage structures of the first storage 202 and the second storage 203 can be configured more flexibly, which is further beneficial to improving the storage density of the first storage 202 and/or the second storage 203 under the condition that the lengths of the key entries in the first storage 202 are not consistent.

In addition, in the embodiment of the present application, the processor 100 may directly indicate the target key area and the target AD area through the position indication information, so that the controller 201 may determine the target key area from the first memory 202 and determine the target AD area from the second memory 203 according to the position indication information, and a process of traversing the first memory 202 and the second memory 203 by the controller 201 is omitted, which is beneficial to improving a search speed of the controller 201 and improving performance of the data search system as a whole.

Moreover, other key areas that are not the target key area may also include the same key entry as the target key entry, and if the controller 201 directly traverses the first memory 202 for searching, a mismatch may also occur. In the embodiment of the present application, the key area is indicated by the position indication information, which is also beneficial to preventing the controller 201 from misjudging, thereby being beneficial to improving the accuracy of the data search system.

In a possible implementation manner, the configuration information may further include depth information of a plurality of key areas in the first memory 202. The depth information of each key area can be understood as the number of key entries in the key area. It can be understood that, between the key region and the AD region having the corresponding relationship, the number of key entries in the key region is the same as the number of AD data in the AD region, and therefore the depth information may also be understood as the number of AD data in the AD region.

When searching for the target key area in a matching manner, the controller 201 may determine the number of key entries in the target key area according to the depth information. The controller 201 may also determine the number of AD data in the target AD area according to the depth information when searching for the target AD area. Therefore, the controller 201 can determine the target key area and the target AD area more accurately.

In the embodiment of the present application, the key entry has a flexible storage manner in the first memory 202. For example, 1 or more key entries may occupy a storage width of 1bit, that is, 1 or more key entries may be located in the same row of storage units of the first memory 202, or 1 key entry may occupy a storage width of multiple bits.

For example, the maximum storage length of the first memory 202 is 40 bits. If the data length of the key table entry in the key area is 20 bits, 40 × 1 bits can be occupied by two key table entries in the key area²Wherein, the storage width is 1 bit. If the data length of the key table entry in the key area is 80 bits, 1 key table entry in the key area occupies 40 multiplied by 2 bits²Wherein, the storage width is 2 bits. By adopting the above storage method, the storage space of the first memory 202 can be used more flexibly, which is beneficial to further improving the storage density of the first memory 202.

It should be understood that, in the embodiment of the present application, the storage length of the key entry may be the same as or different from the data length. As in the above example, in the case that the maximum storage length of the first memory 202 is 40 bits, the storage length of the key entry with the data length of 20 bits is also 20 bits. And for the key table entry with the data length of 80 bits, the storage length is 40 bits.

In order to enable the controller 201 to more accurately identify the target key area in the first memory 202, in a possible implementation manner, the configuration information may further include storage lengths of a plurality of key areas. The processor 100 may acquire the storage length of the target key area according to the configuration information, and transmit the first length information to the controller. The first length information may indicate a storage length of the target key region in the first memory 202.

According to the embodiment of the application, the storage length of the target key area is indicated through the first length indication information, so that the controller 201 can accurately identify the storage area of the target key area from the first storage 202 according to the storage length indicated by the position indication information, and the accuracy of the data search system is improved on the whole.

In the embodiment of the present application, the data lengths of the N AD data in the same AD area may be the same or different. In order to further increase the storage density of the second memory 203, in this embodiment, in any AD region, one or more AD data may be located in the same row of memory cells of the second memory 203, that is, the one or more AD data occupy a storage width of 1 bit.

For example, in fig. 4, 8 pieces of AD data of the AD area a may be stored in the order from left to right, from top to bottom. The address of the upper left corner of the AD area A is the initial storage address of the AD area A. After the AD data 1 is stored in the first row (the first unit maximum storage area), the first row still has room to continue storing the AD data 2 and the AD data 3. After the first line stores AD data 3, the first line has no space to store AD data 4, and then continues to store AD data 4 on the left side of the second line (the second unit maximum storage area). After the second line has stored AD data 4, the second line has still room to continue storing AD data 5 to 7. When the second line stores AD data 7, the second line has no space to store AD data 8, and then AD data 8 is stored in the third line.

By adopting the storage mode, the AD area A occupies 3bit storage width. If the current storage mode that each AD data occupies 1bit of storage width independently is adopted, the AD area A occupies 8 bits of storage width. Therefore, the storage method provided by the embodiment of the present application can further improve the storage density of the second memory 203.

In this case, in order to facilitate the controller 201 to obtain the target data from the target AD area, in a possible implementation, the configuration information may further include length information of each AD data in each AD area. The processor 100 may further obtain an AD length message corresponding to the target AD area according to the configuration information. Wherein the AD length message may include data length information of one or more AD data in the target AD area. The processor 100 transmits the AD length information to the controller 201.

For example, length identifiers corresponding to different data lengths may be included in the configuration information. For example, if there are 4 data lengths in the AD data stored in the second memory 203, the length identifier corresponding to the 4 data lengths in the configuration information may be as shown in fig. 6.

In which AD data of 4 data lengths coexist. If the length mark corresponding to the first data length is 0, the AD data belonging to the first data length includes control information (ctrl in fig. 6) and two pieces of instruction counter information (PC in fig. 6), where 9b indicates that the control information has 9 bits in total, and 21b indicates that one piece of instruction counter information has 21 bits in total. Also for example, the length corresponding to the second data length is denoted by 1, and AD data belonging to the second data length includes ctrl information, 4 PC information, and one reserved (RSV in fig. 6) information. Wherein, the RSV information is 9 bit. The third data length and the fourth data length are similar to those described above and are not described again.

Fig. 6 also exemplarily shows a storage structure of one AD area based on the data length and the length identification shown in fig. 6. As shown in fig. 6, the AD region includes 20 pieces of AD data, wherein one or more pieces of AD data occupy a storage width of 1 bit.

In this case, the AD length message sent by the processor 100 may carry the data length identification of the 20 pieces of AD data. Illustratively, the AD length message may include a bitmap as shown in fig. 7, wherein each indicator bit occupies 2 bits, which may represent a length indicator of AD data. The bitmap shown in fig. 7 has 20 indicator bits (AT0 to AT19), and may sequentially carry length flags of the 1 st to 20 th AD data in the AD region in order from left to right. Taking the AD area shown in fig. 6 as an example, the bitmap carried in the AD length message corresponding to the AD area may be 0000000000000100010001000001010010100011.

It is to be understood that the data length of each AD data in the target AD area may be indicated by the AD length message in case that the number of bits that the AD length message can carry is sufficient. In case the number of bits that the AD length message can carry is not sufficient, in one possible implementation, the excess AD data in the AD area may be configured to be of uniform data length. For example, for the AD length message shown in fig. 7, a data length of 20 AD data at the maximum is indicated. Then, if the depth information of the AD area is greater than 20, if the AD area B includes 25 AD data, the first 20 AD data can be flexibly configured to the storage structure, and the last 5 AD data are configured to the uniform storage length.

In another possible implementation, multiple AD length messages may also be sent to indicate the data length of each AD data in the target AD zone. For example, the AD area B includes 25 AD data, and one AD length message may indicate a data length of 13 AD data at most, in which case the processor 100 may transmit two AD length messages. One of the AD length messages indicates data lengths of 1 st to 13 th AD data, and the other AD length message indicates data lengths of 14 th to 25 th AD data.

In this embodiment, the AD length message may also be referred to as an Associated Data Type (ADT) instruction. Fig. 7 illustrates a specific structure of the AD length message, and 1 to 49 indicate the number of bits of the AD length message. The AD length message carries start indication information (opcode) for indicating that the message is an AD length message. In addition, the AD length message also carries start indication location information (AD _ start) for indicating the start storage address of the first AD data indicated by the ADT instruction.

As in the above example, the processor 100 transmits two AD length messages, where AD _ start in one AD length message is used to indicate the starting storage address of the first AD data in the target AD region, and AD _ start in the other AD length message is used to indicate the starting storage address of the 14 th AD data in the target AD region.

In one possible implementation, the AD length message may be carried by a null instruction to reduce instruction overhead.

In this embodiment, the controller 201 may obtain the target data from the target AD area according to the AD length message and the matched entry position. For example, the controller 201 may determine the data length of the AD data located before the target data in the target AD region according to the matched entry position and the AD length message. Further, the start memory address of the target data can be determined based on the start memory address of the target AD area and the data length of the AD data located before the target data.

Assuming that the AD area shown in fig. 4 is the target AD area and the currently matched entry position is 5, the controller 201 may obtain the data lengths of the AD data 1 to 4 according to the AD length message, and may determine the address interval between the target data (AD data 5) and the start storage address of the target AD area according to the sum of the data lengths of the AD data 1 to 4. Therefore, the initial storage address of the target data can be obtained according to the initial storage address of the target AD area.

In a possible implementation manner, the processor 100 may further obtain data length information of the target data according to the configuration information, and send second length indication information to the controller 201, where the second length indication information may indicate the data length of the target data.

After determining the start storage address of the target data, the controller 201 determines the target data from the second memory 203 according to the length information that can be based on the target data. It is to be understood that the processor 100 may not send the second length indication information, in which case the controller 201 may also determine the length information of the target data according to the AD length message.

Taking the AD area a shown in fig. 4 as an example, assume that the starting memory address of the AD area a is a₀The storage order of the target data in the target AD area is 5. It is assumed that the data length of the AD data 1 to AD data 3 is 20 bits, and the data length of the AD data 4 is 15 bits. Then, the controller 101 may determine that the start storage address of the target data (AD data 5) is a₀+75 bit. The controller 101 further determines that the target data is 15 bits according to the length information of the target data, and then the controller 101 may determine that the target data is a₀+75bit to a₀The target data is obtained in +90 bit.

In one particular embodiment, the controller 201 may execute the following pseudo code to look up the target data:

the AD _ START is a starting storage address of the target AD area, the offset is a representation position of the target key table entry in the target key area, and the AD _ TYPE [ i ] represents length information of the ith AD data. AD _ INDEX represents the current lookup location.

AD _ INDEX >2, i.e. one row (maximum storage length) of the target AD region comprises 4 base lengths, which may be understood as the greatest common divisor of the different data lengths allocated to the AD data. The target AD is read based on AD _ TYPE (length information of target data) and AD _ INDEX [1:0] (representing a base length).

That is, if the length information of the target data is 0, the data length of the target data is 1 basic length, if the length information of the target data is 1, the data length of the target data is 2 basic lengths, if the length information of the target data is 2, the data length of the target data is 3 basic lengths, and if the length information of the target data is 3, the data length of the target data is 4 basic lengths.

In a possible implementation manner, in this embodiment of the application, information such as the starting storage address of the target key area, the starting storage address of the target AD area, the depth information, the storage width of the target key entry, and the second length indication information may be carried by the Kswitch instruction shown in fig. 8.

As shown in fig. 8, the opcode of the Kswitch instruction is used to indicate that the instruction is the Kswitch instruction, where the second length indication information is used to indicate the data length of the target data, the Bucket Start is used to indicate the starting storage address of the target key area, AD _ Start is used to indicate the starting storage address of the target AD area, k _ sz is the first length indication information used to indicate the storage width of the target key area, and the Bucket depth is used to indicate the depth information.

In one possible implementation, processor 100 may be a multi-core processor, and multiple cores of processor 100 may instruct controller 201 to look up the target data in parallel. In this case, the Kswitch instruction may further include a kernel identification (Slice ID, SLID), so that the controller 201 may search for target data for multiple kernels at the same time.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

A data lookup system, comprising: the device comprises a controller, a first memory and a second memory, wherein the first memory is a Content Addressable Memory (CAM);

the first memory comprises a plurality of key areas, wherein each key area comprises a plurality of key table entries;

the second memory includes a plurality of associated data AD areas, wherein each AD area includes a plurality of AD data;

the controller is configured to:

receiving a target key table item and position indication information for searching target data, wherein the position indication information is used for indicating a target key area and a target AD area which are associated with the target data;

matching and searching in the target key area by using the target key table item to obtain a matched table item position;

and obtaining the target data from the target AD area according to the matched table entry position.
The data lookup system as claimed in claim 1 wherein said target key entry is used to execute a target conditional instruction;

the data lookup system further includes a processor configured to:

obtaining the position indication information according to configuration information of the first memory and the second memory and the target conditional instruction, wherein the configuration information comprises a plurality of conditional instructions, a corresponding relation between the plurality of key areas and the plurality of AD areas, the key area corresponding to the target conditional instruction is the target key area, and the AD area corresponding to the target conditional instruction is the target AD area;

and sending the target key table item and the position indication information to the controller.
The data lookup system of claim 2 wherein the controller is further configured to:

and sending the target data to the processor.
The data lookup system as claimed in claim 2 or 3 wherein the processor is further configured to:

and receiving the configuration information.
The data lookup system as claimed in any one of claims 2 to 4 wherein the configuration information further includes depth information for the plurality of key regions;

the processor is further configured to:

acquiring depth information of the target key area according to the configuration information, and sending the depth information to the controller;

the controller is further configured to:

and according to the position indication information and the depth information, respectively determining the target key area from the first memory and determining the target AD area from the second memory.
The data lookup system as claimed in claim 5 wherein the configuration information further includes a storage length of the plurality of key regions;

the processor is further configured to:

determining the storage length corresponding to the target key area according to the configuration information, and sending first length indication information to the controller, wherein the first length indication information is used for indicating the storage length of the target key area;

the controller is specifically configured to:

and determining the target key area from the first memory according to the position indication information, the depth information and the first length indication information.
The data lookup system as claimed in any one of claims 2 to 6 wherein in each AD zone, one or more AD data are located in the same row of memory locations of the second memory.
The data lookup system as claimed in claim 7 wherein the configuration information further includes length information of each AD data in each AD area;

the processor is further configured to:

according to the configuration information, obtaining an AD length message corresponding to the target AD area, wherein the AD length message comprises data length information of one or more AD data in the target AD area, and each data length information is used for indicating the data length of the AD data corresponding to each data length information;

transmitting the AD length message to the controller.
The data lookup system as claimed in claim 8 wherein the configuration information further includes a starting memory address for each key region, and a starting memory address for each AD region;

the location indication information includes a start storage address of the target key area and a start storage address of the target AD area.
The data lookup system of claim 9 wherein the controller is specifically configured to:

acquiring the data length of AD data before the target data in the AD length message according to the matched table entry position;

determining a starting storage address of the target data according to the starting storage address of the target AD area and the data length of AD data before the target data;

and acquiring the target data from the target AD area according to the initial storage address of the target data.
The data lookup system as claimed in claim 10 wherein the processor is further configured to:

determining the data length of the target data according to the configuration information, and sending second length indication information to the controller, wherein the second length indication information is used for indicating the data length of the target data;

the controller is specifically configured to:

and acquiring the target data from the target AD area according to the initial storage address of the target data and the data length of the target data.
A method for data retrieval, comprising:

the method comprises the steps that a controller receives a target key table entry and position indication information, wherein the target key table entry is used for searching target data, the position indication information is used for indicating a target key area which is associated with the target data in a first memory and a target AD area which is associated with the target data in a second memory, the first memory is a Content Addressing Memory (CAM), the first memory comprises a plurality of key areas, each key area comprises a plurality of key table entries, the second memory comprises a plurality of associated data AD areas, and each AD area comprises a plurality of AD data;

the controller uses the target key table item to carry out matching search in the target key area to obtain the position of the matched table item;

and the controller obtains the target data from the target AD area according to the matched table entry position.
The method of claim 12, wherein the target key entry is used for executing the target conditional instruction, and before the controller receives the target key entry and the location indication information for searching the target data, the method further comprises:

the processor obtains the position indication information according to configuration information of the first memory and the second memory and the target conditional instruction, wherein the configuration information comprises a plurality of conditional instructions, a corresponding relation between the plurality of key areas and the plurality of AD areas, the key area corresponding to the target conditional instruction is the target key area, and the AD area corresponding to the target conditional instruction is the target AD area;

and the processor sends the target key table item and the position indication information to the controller.
The method of claim 13, wherein the controller, after obtaining the target data from the target AD region according to the matched entry location, further comprises:

the controller sends the target data to the processor.
The method according to claim 13 or 14, wherein before the processor obtains the position indication information according to the configuration information of the first memory and the second memory and the target condition instruction, the method further comprises:

the processor receives the configuration information.
The method of any of claims 13 to 15, wherein the configuration information further comprises depth information of the plurality of key regions;

the controller uses the target key entry to perform matching search in the target key area, and before obtaining the position of the matched entry, the method further includes:

the processor acquires the depth information of the target key area according to the configuration information and sends the depth information to the controller;

the controller determines the target key area from the first memory and the target AD area from the second memory according to the position indication information and the depth information.
The method of claim 16, wherein the configuration information further includes a storage length of the plurality of key regions;

before the controller uses the target key entry to perform matching search in the target key area to obtain a matched entry position, the method further includes:

the processor determines the storage length corresponding to the target key area according to the configuration information, and sends first length indication information to the controller, wherein the first length indication information is used for indicating the storage length of the target key area;

the controller determines the target key area from the first memory according to the position indication information and the depth information, including:

the controller determines the target key area from the first memory according to the position indication information, the depth information, and the first length indication information.
The method according to any of claims 13 to 17, wherein one or more AD data are located in the same row of memory cells of the second memory in each AD region.
The method of claim 18, wherein the configuration information further includes length information of each AD data in each AD area;

before the controller obtains the target data from the target AD region according to the matched entry position, the controller further includes:

the processor acquires an AD length message corresponding to the target AD area according to the configuration information, wherein the AD length message comprises data length information of one or more AD data in the target AD area, and each data length information is used for indicating the data length of the AD data corresponding to each data length information;

the processor sends the AD length message to the controller.
The method of claim 19, wherein the configuration information further includes a start memory address of each key region, and a start memory address of each AD region;

the location indication information includes a start storage address of the target key area and a start storage address of the target AD area.
The method of claim 20, wherein the controller obtains the target data from the target AD region according to the matched entry location, comprising:

acquiring the data length of AD data before the target data in the AD length message according to the matched table entry position;

determining a starting storage address of the target data according to the starting storage address of the target AD area and the data length of AD data before the target data;

and acquiring the target data from the target AD area according to the initial storage address of the target data.
The method of claim 21, wherein before the controller obtains the target data from the target AD region according to the matched entry location, further comprising:

the processor determines the data length of the target data according to the configuration information, and sends second length indication information to the controller, wherein the second length indication information is used for indicating the data length of the target data;

acquiring the target data from the target AD area according to the initial storage address of the target data, wherein the method comprises the following steps:

and the controller acquires the target data from the target AD area according to the initial storage address of the target data and the data length of the target data.