CN114730288A - 一种内存的管理方法及电子设备 - Google Patents

一种内存的管理方法及电子设备 Download PDF

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Publication number
CN114730288A
CN114730288A CN202080079353.9A CN202080079353A CN114730288A CN 114730288 A CN114730288 A CN 114730288A CN 202080079353 A CN202080079353 A CN 202080079353A CN 114730288 A CN114730288 A CN 114730288A
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CN202080079353.9A
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Inventor
王涛
翟奇
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Honor Device Co Ltd
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Honor Device Co Ltd
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Publication of CN114730288A publication Critical patent/CN114730288A/zh
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5022—Mechanisms to release resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0253—Garbage collection, i.e. reclamation of unreferenced memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7205—Cleaning, compaction, garbage collection, erase control

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

一种内存的管理方法及电子设备，涉及电子设备技术领域，有利于避免对频繁访问的物理页面进行多次不必要的回收检查，加速了操作系统对物理页面的回收效率，提升操作系统的性能，该方法具体包括：电子设备针对每一个内存区域使用多个不活跃链表和一个活跃链表实现回收物理页面的功能。或者，针对每一个内存区域使用一个不活跃链表和多个活跃链表实现回收物理页面的功能。又或者，针对每一个内存区域使用多个不活跃链表和多个活跃链表实现回收物理页面的功能。

Description

PCT国内申请，说明书已公开。

Claims (28)

  1. PCT国内申请，权利要求书已公开。
CN202080079353.9A 2019-11-15 2020-11-02 一种内存的管理方法及电子设备 Pending CN114730288A (zh)

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CN2019111189359 2019-11-15
CN201911118935.9A CN112817736B (zh) 2019-11-15 2019-11-15 一种内存的管理方法及电子设备
PCT/CN2020/125947 WO2021093626A1 (zh) 2019-11-15 2020-11-02 一种内存的管理方法及电子设备

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CN114730288A true CN114730288A (zh) 2022-07-08

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CN201911118935.9A Active CN112817736B (zh) 2019-11-15 2019-11-15 一种内存的管理方法及电子设备
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US (1) US12079118B2 (zh)
EP (1) EP4030301B1 (zh)
CN (3) CN115757193B (zh)
DE (1) DE202020006014U1 (zh)
WO (1) WO2021093626A1 (zh)

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CN115328856B (zh) * 2022-07-05 2023-05-09 荣耀终端有限公司 一种文件页管理的方法、装置及电子设备
CN116049024A (zh) * 2023-01-06 2023-05-02 广州匠芯创科技有限公司 内存页面回收优化方法及其系统、电子设备、存储介质

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115412893A (zh) * 2022-10-19 2022-11-29 成都锐成芯微科技股份有限公司 低功耗蓝牙属性访问方法及低功耗蓝牙系统

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WO2021093626A1 (zh) 2021-05-20
US20240111666A1 (en) 2024-04-04
CN115757193A (zh) 2023-03-07
CN112817736A (zh) 2021-05-18
CN112817736B (zh) 2022-10-21
EP4030301A4 (en) 2022-11-09
US12079118B2 (en) 2024-09-03
EP4030301B1 (en) 2024-01-17
CN115757193B (zh) 2023-11-03
DE202020006014U1 (de) 2024-03-19
EP4030301A1 (en) 2022-07-20

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