CN114721217A - Method and system for improving optical near-end correction technology - Google Patents

Abstract

Embodiments of the present invention relate to methods and systems for improving optical proximity correction techniques. A method and system for improving layout is disclosed. One method comprises the following steps: receiving a design layout; determining a first optical model and a first subset of photoresist correction terms for the photoresist model; performing model-based optical proximity correction (MOPC) according to the first optical model and the first subset of the photoresist model and updating the design layout to obtain a first updated design layout; determining a second optical model and a second subset of the photoresist correction terms for the photoresist model; performing MOPC according to the second optical model and the second subset of the photoresist model and updating the first design layout to obtain a second updated design layout; and manufacturing a photomask according to the second updated layout.

Description

Method and system for improving optical near-end correction technology

Technical Field

Embodiments of the present invention relate to methods and systems for improving optical proximity correction techniques.

Background

In advanced semiconductor technology, the ever-decreasing device sizes and increasingly complex circuit arrangements make the design and fabrication of Integrated Circuits (ICs) more challenging and costly. Before a circuit is delivered for mass production, it must be confirmed that the circuit design meets design specifications and manufacturing criteria to improve manufacturing yield. To detect design errors or defects as early as possible, circuit designers employ computer-aided circuit design tools that are widely used in the industry to assist designers in identifying potential design defects. However, as circuit complexity and device density continue to increase, the software processes involved in circuit design and verification consume an increasingly large amount of time and computational resources. Accordingly, there is a need for an improved circuit design flow to reduce design time while maintaining the quality of the circuit design.

Disclosure of Invention

Embodiments herein disclose a method of improving a layout, comprising: receiving a design layout; determining a first optical model and a first subset of photoresist correction terms for the photoresist model; performing model-based optical proximity correction (MOPC) according to the first optical model and the first subset of the photoresist model and updating the design layout to obtain a first updated design layout; determining a second optical model and a second subset of the photoresist correction terms for the photoresist model; performing MOPC according to the second optical model and the second subset of the photoresist model and updating the first design layout to obtain a second updated design layout; and manufacturing a photomask according to the second updated layout.

Embodiments herein disclose a method of improving a layout, comprising: receiving a design layout; determining an initial subset of photoresist correction terms as a new subset; determining a photoresist model from the new subset; determining an optical model; performing model-based optical proximity correction (MOPC) based on the optical model and the photoresist model and updating the design layout to a second updated layout; judging whether the second design layout meets the design specifications; and in response to the second design layout not meeting the design specification, performing the following steps: updating the new subset by maintaining original photoresist correction terms or including more photoresist correction terms; and MOPC is carried out on the second design layout according to the updated subset, and the second design layout is updated to obtain a third design layout.

Embodiments herein disclose a design layout system comprising one or more processors and one or more programs storing instructions that, when executed by the one or more processors, cause the system to perform the steps of: receiving a design layout; determining a first optical model and a first subset of photoresist correction terms for the photoresist model; performing model-based optical proximity correction (MOPC) and updating the design layout to obtain a first updated design layout based on the first optical model and the first subset of the photoresist model; determining a second optical model and a second subset of the photoresist correction terms for the photoresist model; performing MOPC according to the second optical model and the second subset of the photoresist model and updating the first design layout to obtain a second updated design layout; and manufacturing a photomask according to the second updated layout.

Various objects, features, aspects and advantages of embodiments of the present invention will become more apparent from the detailed description of preferred embodiments of the invention when taken in conjunction with the accompanying drawings in which like reference characters identify similar elements.

Drawings

Aspects of embodiments of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily expanded or reduced for clarity of presentation.

FIG. 1 is a schematic diagram of an Integrated Circuit (IC) manufacturing system according to some embodiments.

FIG. 2 is a schematic diagram of a photomask layout preparation subsystem according to some embodiments.

Fig. 3A to 3C are schematic diagrams of a design layout according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a model optical proximity correction module according to an embodiment of the present invention.

Fig. 5A and 5B are schematic diagrams of optical models according to some embodiments.

FIG. 6 is a flow diagram of a method of photoresist model training, according to some embodiments.

FIG. 7 is a schematic diagram of the iterative complexity of an optical near-end correction method according to some embodiments.

FIG. 8 is a flow chart of a method of optical proximity correction according to some embodiments.

FIG. 9 is a flow chart of a method of optical proximity correction according to some embodiments.

FIG. 10 is a system diagram implementing an optical proximity correction method according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. To simplify the embodiments of the present invention, specific examples of components and arrangements are described below. Of course, these are merely examples and are not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This is repeated for simplicity and clarity and does not in itself represent a relationship between the various embodiments and/or arrangements.

Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other directions (90 degrees or at other angles) and the spatially relative terms used in this specification are therefore to be interpreted accordingly.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the differences found in their respective testing measurements. Also, as used herein, the terms "about," "approximately," and "approximately" generally mean within 10%, 5%, 1%, or 0.5% of a particular value or range. Alternatively, the terms "about", "approximately" and "approximately" are intended to be within an acceptable standard error of the mean, as considered by one of ordinary skill in the art. Except in the operating/working examples, or where otherwise explicitly indicated, all numerical ranges, amounts, values and percentages disclosed herein (e.g., amounts of materials, durations, temperatures, operating conditions, quantitative ratios, etc.) are to be understood as modified in any instance by the terms "about", "substantially" or "substantially". Accordingly, unless indicated to the contrary, the numerical parameters set forth in the examples of the invention and the attached claims are approximations that may vary depending upon the desired properties. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges may be expressed herein as from one end point to another end point or between two end points. Unless otherwise indicated, all ranges disclosed herein are inclusive of the endpoints.

The terms "layout," "design layout," and "photomask layout" as used herein refer to the geometric pattern content of an Integrated Circuit (IC) corresponding to the components of the IC, such as the metal, dielectric, or semiconductor layers that make up the components of the IC. In some examples, the terms "layout," "design layout," and "photomask layout" also include associated data files of machine-readable code or text strings that may be converted into geometric patterns. In addition, the file of the design layout may also include additional information (e.g., IC-related parameters translated from geometric patterns) to improve IC design and process.

The terms "optical lithography" and "photolithography" as used herein refer to the process of transferring a geometric pattern on a photomask associated with a circuit to a layer on a substrate. The geometric pattern included on the photomask may be defined by the design layout pattern of the photomask. Optical lithography or photolithography processes typically use light of a specific wavelength as a light source, which is modulated and transmitted by an optical system and then irradiated onto a photomask, which may be transmissive or reflective, depending on the nature of the incident light source. In some cases, the geometric pattern transferred to the substrate may be misaligned with the desired pattern on the photomask layout due to interaction of the light source (plus the passing optics) with the substrate (or photoresist thereon), thereby degrading the performance of the manufactured semiconductor device. Therefore, it is often desirable to modify the geometric patterns on the photomask for lithography refinement engineering of the photomask layout to ensure that the geometric patterns ultimately transferred to the substrate conform to the design specifications for the errors between the design layout patterns of the original photomask.

Furthermore, for the lithography technique (EUV lithography, EUVL) using extreme ultraviolet light (EUV) as a light source for exposure, the lithography improvement engineering may be more complicated because various optical effects (e.g., diffraction and interference) caused by EUVL have a more significant effect on the lithography performance than other light sources of longer wavelength. While improvements in EUVL lithography are being considered, costs and time must be kept within acceptable limits.

An improved process for simplifying existing lithography techniques is presented herein. Improvements in existing lithography include Optical Proximity Correction (OPC) techniques, which allow the pattern transferred from an updated photomask layout pattern to gradually approximate the original desired pattern by repeatedly correcting the photomask layout pattern. Currently, in the iterative process of OPC, the parameter complexity of the optical model and the photoresist model used in each round is fixed to the highest level, so as to satisfy the correction requirement of the polygon with the highest complexity in the layout pattern. The improvement proposed here is to use different iterative rounds of OPC for the optical model or photoresist model with different complexity of parameter combinations. For example, in the first few OPC rounds, a less complex optical model or photoresist model may be used to achieve the initial calibration. And in the last few times of OPC, the optical model or the photoresist model can be recovered to the most complete optical model for correction. The OPC improving mode adopting different model complexity in different rounds can correct simpler layout patterns by using simpler models in several rounds of OPC in the initial stage, so that the operation cost is lower and the correction result is not reduced too much; on the other hand, the more complex layout pattern can be corrected by using the more complex model in the final several OPC loops, and finally, the correction accuracy of the complex pattern is not sacrificed. The method can reduce the overall operation cost, and the improved result of the layout pattern can still achieve the expected target, thereby accelerating the overall design and manufacturing efficiency.

FIG. 1 is a schematic diagram showing an IC manufacturing system 100 according to some embodiments. The IC manufacturing system 100 is configured to manufacture IC devices 160 by a plurality of entities, such as design companies 120, photomask factories 130, and IC manufacturers (wafer factories or foundry) 150. Different entities in the IC manufacturing system 100 may be connected by communication pipes (e.g., wired or wireless pipes) and interact with each other through a network (e.g., an intranet or the internet). In one embodiment, the design company 120, the photomask factory 130, and the IC manufacturer 150 may be owned by the same entity or operated independently.

A design company (or design team) 120 is responsible for generating a design layout 122 for manufacturing an IC device 160 during an IC design phase. The design layout 122 includes various geometric patterns that may perform predetermined performance of the IC device and meet manufacturing constraints. The geometric patterns in the design layout 122 represent circuit elements of various IC components in the fabricated IC device 160, such as metal layers, dielectric layers, or semiconductor layers, for example, to form metal lines, vias, or insulating layers in active regions, gate electrodes, source and drain, and inter-level interconnects, for example. In one embodiment, design company 120 performs a circuit design process to generate design layout 122. The circuit design process may include, but is not limited to: logic design, physical circuit design, simulation before layout, wire arrangement and winding, time sequence analysis, parameter extraction, design rule check and simulation after layout. The design layout 122 may be converted into a visual graphic via a textual representation of the document to adequately display the physical layout to be represented, such as the size, shape, and location of the depicted pattern. In one embodiment, the design layout 122 may be represented in a GDSII, DFII, or OASIS file format.

The photomask factory 130 receives the design layout 122 from the design company 120 and manufactures one or more photomasks according to the design layout 122. In one embodiment, photomask factory 130 includes photomask layout preparation subsystem 132, photomask manufacturing subsystem 144, and photomask inspection subsystem 146. The photomask layout preparation subsystem 132 is used to modify the design layout 122 so that the updated design layout 134 may facilitate a photomask writer in transcribing the design layout 122 as desired. When the photomask is manufactured, the photomask may be used to repeatedly transfer a pattern in the photomask to different cells in a semiconductor wafer, and the photomask projects a patterned light source to an exposure area of a predetermined size for pattern transfer in each exposure process. In addition, scribe line regions may exist between different units of the semiconductor wafer, and the test structure may be formed in spaces of the scribe line regions.

Photomask manufacturing subsystem 144 is configured to process a photomask substrate to form a photomask according to design layout 134. In a photolithography process, a lithographic light source projects a pattern of the design layout 134 and patterned light is projected onto the photoresist, which can then be etched to leave the same pattern as the design layout on the photomask substrate. In one embodiment, photomask manufacturing subsystem 144 conducts an inspection process to ensure that the layout pattern meets the requirements of a photomask writer or photomask manufacturer, and that the layout pattern may be used to create a photomask as desired. The layout pattern transfer process in fabricating the photomask may be performed using an electron beam (e-beam) apparatus. In addition, photomasks may be fabricated using a variety of other techniques. In one embodiment, a photomask is fabricated using a binary technique, where a binary photomask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chrome) coated on the photomask. In another example, a photomask is fabricated using a phase shifting technique, such as a phase shifting Photomask (PSM).

After the photomask is fabricated, photomask inspection subsystem 146 is used to inspect the fabricated photomask to determine if any defects, such as full height and non-full height defects, are present in the fabricated photomask. If any defects are detected, consideration is given to either discarding the photomask or modifying the design layout in the photomask.

IC manufacturer 150 is used to produce a variety of different IC products and may contain multiple manufacturing facilities. IC manufacturer 150 uses the photomasks produced by photomask factory 130 to produce semiconductor wafer 152, where semiconductor wafer 152 includes a plurality of IC devices 160. Semiconductor wafer 152 may be a silicon substrate or other suitable substrate, and various layers may be present on semiconductor wafer 152 to form various photomask patterns. In one embodiment, IC manufacturer 150 includes IC test subsystem 154 configured to test wafer 152 such that IC device 160 complies with physical manufacturing specifications and mechanical and/or electrical performance specifications. In some embodiments, test structures formed on wafer 152 may be utilized to generate test data as a quality indicator. After wafer 152 passes through the testing process performed by wafer test subsystem 154, wafer 152 may be diced along dicing street regions to form individual IC devices 160. The cutting process may be accomplished by dicing and singulation, and may be performed by means of a mechanical saw or laser cutting.

FIG. 2 is a schematic diagram of a photomask layout preparation subsystem 132 in the IC manufacturing system 100 of FIG. 1 according to some embodiments. The photomask layout preparation subsystem 132 includes a regular-based OPC (ROPC) module 210, a boundary separation module (BD) 220, a model-based OPC (MOPC) module 230, and a photolithography process check (LPC) module 240.

The ROPC module 210 is configured to verify the design layout 122 in order to modify the design layout 122 according to predetermined photomask manufacturing rules. The ROPC module 210 receives a rule table composed of manufacturing specifications of various manufacturers to check the design layout 122. If the design layout 122 does not comply with the rules table of the ROPC module 210, the design layout 122 will be modified accordingly by the ROPC module 210 until the modified design layout 122 complies with the rules. The rule table may include design specifications for the geometric types of the patterns in the design layout 122, such as minimum length, minimum pitch, maximum number of patterns, and the like.

FIG. 3A is a schematic diagram of a design layout 300A according to an embodiment of the present invention. Referring to fig. 2 and 3A, a design layout 300A may be a portion of the design layout 122 that includes an exemplary pattern 302, where the pattern 302 may be a pattern that has been inspected and modified by the ROPC module 210 and thus conforms to the design specifications in the rule table of the ROPC module 210.

Referring back to FIG. 2, the design layout 122 is edge partitioned via the BD module 220. Referring to fig. 2 and 3B, in the pattern 300B, an edge 302B defining the pattern 302 is divided into a plurality of edge segments 302S, for example, the edge segments 302S numbered from (1) to (5). The segmented design layout becomes the updated design layout 202. Each edge segment 302S of the pattern 302 is the smallest unit of the lithography correction process, and each edge segment 302S can be individually modified in the lithography improvement method, so that the updated pattern 302 can obtain better lithography effect. The length of the edge segment 302S may be adjusted as desired. The smaller the length of the edge segment 302S, the more accurate the correction result of the updated pattern 302 obtained by the lithography improvement method can be obtained, however, it is also possible that more computing resources must be used because the total number of the edge segments 302S of the pattern 302 is increased.

In one embodiment, the BD module 220 classifies each edge segment 302S simultaneously when performing edge segmentation on the design layout 300A. In one embodiment, the classification of the edge segment 302S is determined according to its complexity as belonging to a one-dimensional or two-dimensional graph. For example, the edge segments 302S numbered (1) and (2) can be classified as one-dimensional graphics because they are straight lines with low complexity and are not close to the corners or pattern ends of the pattern 302. The edge segment 302S numbered (3), (4), and (5) is classified as a two-dimensional graph because it is close to the corner or the end of the pattern 302 itself, and thus has high complexity. The above classification is merely exemplary, and the BD module 220 herein may perform edge segment classification according to other features. For example, edge segments 302S classified as in one-dimensional graphics may be further classified as sparse one-dimensional graphics and dense one-dimensional graphics depending on the distance of the pattern 302 from other neighboring patterns. Further, the edge segments 302S classified as two-dimensional graphics can be further classified as sparse two-dimensional graphics and dense two-dimensional graphics depending on the distance between the pattern 302 and other adjacent patterns or the width of the pattern 302 at the edge segments 302S.

In another embodiment, the edge segment 302S can be classified according to the pattern 302 itself or the Critical Dimension (CD) of the pattern 302 in the edge segment 302S. Since the optical model and the photoresist model of the OPC produce different correction effects for patterns with different critical dimensions, classifying the critical dimensions corresponding to the edge segment 302S of the design layout 300B helps to simplify the correction work of the OPC and improve the correction performance. In one embodiment, the edge segments 302S can be classified into different categories, such as small size, medium size, and large size. In one embodiment, the BD module 220 may perform multiple classifications of the edge segments 302S, such as a more detailed classification for both one-dimensional/two-dimensional graphics characteristics and critical dimensions.

After edge segment segmentation and classification, the lithography improvement method provided herein performs model-based optical proximity correction (MOPC) on the design layout 300B with the MOPC module 230. In some embodiments, MOPC module 230 is configured to apply predetermined optical models and photoresist models and to simulate the optical path of a lithography light source and the simulated pattern imaging resulting from the exposure of a design layout pattern (e.g., pattern 302 of FIG. 3A) to light intensity distribution values on a semiconductor substrate via various optical effects. In one embodiment, MOPC module 230 may collect imaging errors between the simulated pattern image and the desired pattern, such as from diffraction, interference, or other optically related effects, or effects related to photoresist composition or process effects.

In some embodiments, the OPC module 230 takes into account the glare effect or the slit effect caused by defects present in the optical elements of the lithography system. In one embodiment, the glare effect generally refers to the combined effect of stray light incident on the photomask causing undesirable reflection or scattering by the optical elements. In one embodiment, the slit effect is used to simulate the effect of an arc-shaped exposure slit, wherein the azimuthal angle of incident light passing through the arc-shaped exposure slit from the center portion to the end portion of the arc-shaped exposure slit produces an uneven distribution. The variation of the azimuth angle may cause non-uniformity of intensity, phase, and polarization of light passing through the slit, thereby generating an imaging error.

In one embodiment, the MOPC module 230 may further compensate, i.e., perform optical proximity correction, for the collected imaging error data using photolithography improvement techniques. In one embodiment, the enhancement features or patterns (e.g., scattering bars, serifs, and/or hammerheads) are added to or removed from the design layout 122 according to an established optical model or rule. For example, MOPC module 230 may perform the correction in any of the following ways: redefining the boundary of the original pattern; attaching sub-resolution assist features to the original pattern; or adding scattering bars to the original design layout.

In one embodiment, the simulation of the exposure intensity distribution of the design layout pattern and the correction of the pattern 302 of the design layout 300B can be performed for the pattern 302 as a whole or for each edge segment 302S individually. FIG. 3C is a schematic diagram of a design layout 300C according to an embodiment of the present invention. Design layout 300C includes a pattern 304 that represents an updated pattern generated after pattern 302 has undergone a calibration process by the MOPC module. The edge 304B of the pattern 304 is shown in dashed lines, wherein a portion of the edge segment 304S of the edge 304B overlaps the original edge 302S, indicating that the position of the edge segment does not need to be modified after the correction process of the MOPC module 230. On the other hand, another portion of the edge segment 304S of the edge 304B is spaced apart from the original edge 302S, which represents that the edge segments need to be shifted for better lithography after the correction process of the MOPC module 230.

In one embodiment, the edge segments 304S of the pattern 304 of the design layout 300C are obtained through multiple iterations, each iteration calculating the distance to be translated or not to be translated. After the multi-pass correction and convergence process, each edge segment 304S converges to the ideal position.

Referring back to FIG. 2, the LPC module 240 is used to simulate the manufacturing process performed by the IC manufacturer 150, and the simulated range may cover all or a portion of the design layout (e.g., layout 202). In this embodiment, the LPC module 240 models the design layout 300C of the design layout 202 as improved by the MOPC module 230. In some embodiments, LPC module 240 is configured to examine final design layout 300C to determine if there are any problematic regions (also referred to as "hot spots"). The term "hot spot" may be used to represent an area or feature of IC device 160 that negatively impacts performance. Hot spots may be caused by circuit design and/or process control inaccuracies, and symptoms exhibited by hot spots include squeeze/necking of features, bridging (shorts), dishing, erosion, RC delay, line thickness variation, etch residue, and other possible aspects.

When the final design layout 300C passes the verification of the LPC module, the design layout 134 is generated, which, as previously described, may be used by the photomask manufacturing subsystem 144 for the manufacture of a photomask.

FIG. 4 is a schematic diagram of a model optical proximity correction Module (MOPC)230 according to an embodiment of the present invention. The MOPC module includes a segment selection module 410, an optical model module 420, a photoresist model module 430, and a segment correction module 440. In one embodiment, multiple iteration iterations may be performed in the MOPC module 230 to correct the pattern in the design layout 202, wherein the correction process consisting of the segment selection module 410, the optical model module 420, the photoresist model module 430, and the segment correction module 440 may be repeated to gradually converge the correction results. In addition, each of the above-mentioned constituent modules of the MOPC module 230 may adopt different operation parameters for different rounds to save operation time and improve calibration effect, the details of which will be described in the following paragraphs.

In one embodiment, the fragment selection module 410 receives the design layout 202 and performs fragment category selection of the pattern edges. As described above, the pattern edges in the design layout 202 are also classified into edge segments 302S after being divided by the BD module 220, for example, into different categories such as one-dimensional graphics and two-dimensional graphics. In one embodiment, the clip selection module 410 will select only a portion (e.g., one-dimensional graphics) of the pattern clips of the design layout 202 to be corrected during the first round of correction by the MOPC module 132, and not perform any processing on other unselected portions (e.g., two-dimensional graphics), based on the classification of the edge clips 302S. In one embodiment, the snippet selection module 410 selects uncorrected portions of the pattern snippets (e.g., two-dimensional graphics) of the design layout 202 for correction in the next few iterations of the MOPC module 132. In another embodiment, the snippet selection module 410 corrects all pattern snippets of the design layout 202, regardless of their classification, in the next few iterations of the MOPC module 132. The number of iterations of the iteration MOPC can be determined according to requirements, and is not necessarily fixed.

In one embodiment, the design layout 202 enters the optical model module 420 through the selected edge segment 302S. The optical model module 420 provides a model of the optical projection path to simulate the exposure intensity distribution illuminated by the light source at each location on the design layout 202. In one embodiment, the design layout 202 is set to an initial pattern that is not MOPC processed. This initial pattern is represented by a matrix H, which consists of matrix elements of P columns and Q rows, P and Q being positive integers, where the (P, Q) -th element is represented as H (P, Q). Next, the matrix elements H (p, q) of the design layout 202 are binarized and set. For example, the matrix elements H (p, q) that overlap the selected edge segment 302S are set to "1", while the other matrix elements H (p, q) that do not overlap the selected edge segment 302S are set to "0".

In one embodiment, the optical model Φ selected by the optical model module 420 is interacted with the matrix H to obtain the light intensity received by the initial pattern. In one embodiment, for an edge segment located on a matrix element H (p, q), a local area near the matrix element H (p, q) may be set as an operation area, and the operation area is used as a range to perform convolution (convolution) on the matrix element H (p, q) and the optical model Φ to obtain an initial pattern received light intensity matrix I, as represented by the following formula.

Wherein the operand

Representing a convolution operation, function phi_iThe ith component function, a weight value λ, representing the optical model Φ_iRepresenting a composition function phi_iThe weight value occupied.

In one embodiment, the MOPC module also includes an optical database 402 that includes the types of different optical models Φ and related parameters. The optical model Φ can be selected from the optical database 402 according to different types of optical data to obtain the light intensity matrix I, wherein the physical meaning and the model complexity of the parameters of different optical models Φ are different. For example, referring to FIG. 5A, the optical model Φ can be a Normal Incidence (NI) model, which assumes that light rays 504 incident on a target 502 (e.g., a photoresist) are both incident normal to the surface of the target 502. In another embodiment, referring to FIG. 5B, the optical model Φ may be an off-axis illumination (OAI) model, which assumes that the light 506 incident on the object 502 (e.g., a photoresist or a photomask) may include different angles between the vertical and oblique angles with respect to the surface of the object 502. Generally, the calculation requirement of the vertical incidence model is low, and the method can be used for photoetching improvement engineering with low pattern complexity; on the other hand, the off-axis illumination model can be used to simulate more complicated (e.g., two-dimensional pattern) lithography improvement engineering, but also has to bear higher computational requirements.

In one embodiment, the optical database 402 further includes three-dimensional distribution information of the surface topography of the photoresist, which simulates the exposure intensity variation of the photoresist material due to the non-ideal surface of the photoresist material when exposed to the photolithography process.

In one embodiment, the initial pattern is processed by the optical model module 420 and then enters the photoresist model module 430 to simulate the photochemical reaction of the photoresist material with light, post-lithography baking, and development processes to predict the resulting photoresist pattern. In one embodiment, the MOPC module includes a photoresist database 404 that includes correction terms, models thereof, and related parameters related to photoresist or other lithographic process materials. For example, photoresist correction terms of photoresist database 404 may include photoresist material, etch chemistry type, acid concentration profile values, base concentration profile values, photo acid diffusion, binary mask related derivative values (e.g., density differences), curvature tangent vectors, curvature forward vectors, and the like.

In one embodiment, the light intensity matrix I of the optical model module 420 is operated by the photoresist model θ selected by the photoresist model module 430 to obtain a light intensity matrix J of the photoresist pattern. In one embodiment, for the edge segment located on the matrix element H (p, q), taking the above-mentioned operation area as the range, the light intensity matrix I and the photoresist model Θ can be convolved to obtain the light intensity matrix J, which is represented by the following formula.

Wherein theta is_iFunction representing the i th photoresist correction term of the photoresist model theta, weight value gamma_iRepresentative function theta_iThe occupied weight, N, represents the total number of composition functions of the photoresist model Θ.

In one embodiment, to simulate a development or etching process, for the light intensity matrix J, if the intensity of an element is greater than the development threshold T, then the position represented by the element is represented, leaving a pattern after the development process. Conversely, if the intensity of the element light is less than the development threshold T, the location represented by the element is removed after the development process. The predicted photoresist pattern profile can be obtained by this calculation, which is expressed by a matrix K, and the element values are expressed by binary values, which can be obtained by the following calculation formula.

In one embodiment, the correction module 440 compares the photoresist pattern profile K with the pattern profile of the design layout 122 of FIG. 1 to determine how to correct the edge segments 302S of the patterns of the design layout 122 or 202, thereby obtaining the updated design layout 300C of FIG. 3C. In another embodiment, the correction module 440 determines how to correct the edge segment 302S of the pattern of the design layout 202, and thus the edge segment 302S of the pattern of the design layout 202, according to the difference between the light intensity matrix J of the photoresist pattern and the development threshold T by comparing the pattern profile of the design layout 122 of FIG. 1, to obtain the updated design layout 300C of FIG. 3C.

In one embodiment, the correction module 440 determines whether the one or more edge segments 302S of the design layout 300C have moved to the optimal position by computing a previous pass. In other words, the segment selection module 410, the optical model module 420, the photoresist model module 430 and the correction module 440 require a plurality of iterations to converge the final photoresist pattern profile K, i.e., the deviation between the photoresist pattern profile K and the pattern profile of the design layout 122 is lower than the design specification). While in each round of computation, the correction module 440 may consider some edge segments 302S to have not converged and move them, while other edge segments 302S do not move any more if they have converged.

In one embodiment, each edge segment 302S is further processed by the optical model module 420 and the photoresist model module 430 during each round of calculation, regardless of whether the edge segment needs to be moved again. Since the proportion of the calculation resources occupied by the optical model module 420 and the photoresist model module 430 for calculating the predicted photoresist pattern profile K to the entire MOPC is quite high, in order to overcome the disadvantage of excessive calculation amount in the prior art, different optical models Φ or photoresist models Θ can be selected to be adopted in different rounds of iteration. Moreover, by properly arranging the complexity of the optical model Φ or the photoresist model Θ in different rounds, i.e., the direction from low to high, the method has the advantage of saving the computation workload and can maintain the correction effect of the photoresist pattern profile K without dropping.

In one embodiment, the photoresist model Θ of different complexity has a different total number of photoresist correction terms N. Notably, each photoresist correction term function θ in the photoresist model Θ_iCorresponding weight value gamma_iCorrection of the item function theta, possibly with other photoresists_iBut varies. Therefore, when determining that different photoresist correction items constitute photoresist models Θ of different complexities, the optimal weight values γ thereof_iAnd also retrained to get. FIG. 6 is a flow diagram of a photoresist model training method according to some embodiments. Additional steps may be provided before, during, and after the steps shown in fig. 6, and some of the steps described in method 600 may be removed or replaced with other steps in some embodiments. In some embodiments, the order of the steps in method 600 may be reversed.

At step 602, a first photoresist correction item function θ for a photoresist model Θ is received_iAnd corresponding first weight value gamma_i. In one embodiment, the photoresist model Θ is an unreduced photoresist model, and the first photoresist correction term function Θ_iThe total number of (B) is A. At step 604, the subset function number B is determined as a second photoresist correction term function for the photoresist model Θ

Total number of B<A。

In step 606, according to the first weight value γ_iSize selection of B first photoresist correction item functions theta_iSecond photoresist correction term function as the photoresist model Θ

Wherein the second photoresist correction item function

With a corresponding first weight value gamma_i. In one embodimentThe second photoresist correction item function

Is a first photoresist correction term function theta_iA subset of (2). In one embodiment, B maximum weight values γ are selected_iFirst photoresist correction term function theta_iAs a function of a second photoresist correction term

In one embodiment, the B first photoresist correction item functions θ are selected according to the photomask process characteristics_iAs a function of a second photoresist correction term

At step 608, it is determined whether to retrain the second photoresist correction project function

First weight value gamma of_i. If it is determined that retraining is not to be used, the method 600 proceeds to step 610, a second photoresist item function according to the photoresist model Θ

And a first weight value gamma_iThe MOPC of fig. 4 is performed (e.g., the operation of photoresist model module 430 is performed).

If it is determined that the first weight value gamma needs to be retrained_iThen the method 600 proceeds to step 612 where the second photoresist correction term function for the photoresist model Θ is trained using the known photomask pattern

To obtain a corresponding second weight value

Which replaces the original first weight value gamma_i. In one embodiment, the second weight value is obtained by regression method using the known photomask pattern

In one embodiment, the second weight value

And a first weight value gamma_iAre not the same. In one embodiment, the second photoresist item function is trained using a circuit pattern of a known semiconductor device

To obtain a second weight value

At step 614, a second photoresist item function according to the photoresist model Θ

And a second weight value

The MOPC of fig. 4 is performed (e.g., the operation of photoresist model module 430 is performed).

The above photoresist model Θ, due to the number of functions A>B, therefore it applies the first photoresist correction term function theta_iThe model complexity is greater than applying the second photoresist correction item function

However, all can be used in the photoresist model module 430 provided herein. In one embodiment, although a second photoresist correction item function is used

The operation of the photoresist model module 430 is performed, thereby saving the operation resources, however, if the second weight value is used

Due to its retrained optimization, its performance is better than using the first weight value γ_iSecond photoresist correction item function of

As previously described, the MOPC method presented herein performs progressive design layout pattern correction in an iterative manner, and each round of iteration can select a different complexity set of edge segments, optical model Φ, or photoresist model Θ. Figure 7 is a MOPC method iteration complexity diagram 700, according to some embodiments. The 16 histograms in diagram 700 represent 16 iterations (N16) of the MOPC, respectively, and end at 16 th iteration (N16). Each histogram consists of three short columns representing the set of edge segments, optical model Φ, and photoresist model Θ used in the iteration, respectively, with different short column patterns representing different complexities. In one embodiment, the MOPC method presented herein employs an un-simplified set of edge segments, and un-simplified optical and photoresist models, at least once in the last pass (n-16). In one embodiment, the set or model employed by each of fragment select module 410, optical model module 420, and photoresist model module 430 has the same or lower complexity for the initial round (i.e., n is smaller) compared to the later round (i.e., n is larger).

For example, the segment selection module 410 employs a first edge segment set when the iteration round n is 1-5, a second edge segment set when the iteration round n is 6-10, and a third edge segment set when the iteration round n is 11-16, wherein the first edge segment set may be a small-sized one-dimensional graph, the second edge segment set may be a one-dimensional graph of all sizes, and the third edge segment set may be a graph of all sizes (including a one-dimensional graph and a two-dimensional graph).

In another embodiment, the optical model module 420 employs a first optical model in the iteration round n is 1-8 and a second optical model in the iteration round n is 8-16, wherein the first optical model may be a normal incidence model and the second optical model may be an off-axis illumination model. In an embodiment, the complexity of the second optical model is greater than the complexity of the first optical model.

In yet another embodiment, the photoresist model module 430 employs N in the iteration rounds N1-4₁The photoresist correction item function adopts N when the iteration round N is 5-8₂The photoresist correction item function is adopted when the iteration round N is 9-12₃A photoresist correction item function is used, and N is adopted when the iteration round N is 13-16₄A photoresist correction item function, where N₁≤N₂≤N₃≤N₄. In one embodiment, N₄The total number of all photoresist correction term functions representing the photoresist model.

FIG. 8 is a flow chart of an optical proximity correction method 800 according to some embodiments. The method 800 provided herein may provide additional steps before, during, and after the steps shown in fig. 8, and some of the steps described in the method 800 may be removed or replaced with other steps in some embodiments. In some embodiments, the order of the steps in method 800 may be reversed.

In step 802, a design layout is received. In step 804, ROPC is performed on the design layout. In step 806, a first optical model and a first subset of photoresist correction terms for the photoresist model are determined. In one embodiment, the first subset is a second photoresist correction term function for the photoresist model Θ in method 600

In step 808, a first number of iterations is determined. In step 810, MOPC is performed for the first iteration number according to the first optical model and the first subset of photoresist models Θ, and the design layout is updated to obtain a first updated design layout.

In step 812, a second optical model and a second subset of the photoresist correction terms for the photoresist model are determined. In one embodiment, the second subset is the first photoresist correction term function θ for the photoresist model Θ in method 600_i. In step 814, a second number of iterations is determined. In step 816, the MOPC of the second iteration number is performed according to the second optical model and the second subset of photoresist models Θ, and the first design layout is updated to obtain a second updated design layout. In step 818, a photomask is fabricated according to the second updated layout. In step 820, a semiconductor device is fabricated according to the photomask.

FIG. 9 is a flow chart of an optical proximity correction method 900 according to some embodiments. The method 900 provided herein may provide additional steps before, during, and after the steps shown in fig. 9, and some of the steps described for the method 900 may be removed or replaced with other steps in some embodiments. In some embodiments, the order of the steps in method 900 may be reversed.

In step 902, a design layout is received. In step 904, ROPC is performed on the design layout. In step 906, an initial subset of photoresist correction terms for the photoresist model is determined as a new subset. In step 908, a photoresist model is determined from the new subset. In an embodiment, weight values corresponding to an initial subset of photoresist correction terms in the photoresist model are received or determined from the initial subset.

In step 910, an optical model is determined. In step 912, model-based OPC is performed based on the optical model and the photoresist model and the design layout is updated. In step 914, a determination is made as to whether the updated design layout complies with the design specification. In one embodiment, a determination is made as to whether the updated design layout complies with a design specification as to whether the updated design layout error is less than a default value.

If the updated design layout is determined to have errors that meet the design specifications, then a photomask is manufactured according to the updated layout in step 916. If the updated design layout determines that the errors do not meet the design specifications, then in step 918 a new subset is formed by maintaining the original photoresist correction terms or including more photoresist correction terms, and the method 900 proceeds back to step 908 until the updated design layout is determined that its errors meet the design specifications, or the method 900 has reached a default number of iterations, and the method 900 stops.

FIG. 10 is a schematic diagram of a system 1000 implementing an optical proximity correction method according to some embodiments. The system 1000 includes a processor 1001, a network interface 1003, an input/output (I/O) device 1005, a storage device 1007, a memory 1009, and a bus 1008. The bus 1008 connects the network interface 1003, the I/O device 1005, the storage device 1007, the memory 1009, and the processor 1001 to each other.

The processor 1001 is configured to execute program instructions, including tool instructions, configured to perform the methods as described and depicted in the figures herein. Thus, the tool is configured to perform steps such as providing design specifications, generating design layout data, performing OPC steps, performing LPC steps, extracting layout dependent parameters, performing model training, and correcting design layout patterns.

The network interface 1003 is configured to access program instructions and data, where the data may be stored remotely over a network (not shown) and accessed by the program instructions.

The I/O devices 1005 include input devices and output devices configured to enable a user to interact with the system 1000. In some embodiments, input devices include, for example, keyboards, mice, and other devices. In addition, output devices include, for example, displays, printers, and other devices.

The storage device 1007 is configured to store program instructions and data accessed by the program instructions. In some embodiments, storage device 1007 comprises a non-transitory computer-readable storage medium, such as a magnetic disk and an optical disk.

The memory 1009 is configured to store program instructions that are executed by the processor 1001 and data that is accessed by the program instructions. In some embodiments, memory 1009 includes any combination of Random Access Memory (RAM), other volatile storage, Read Only Memory (ROM), and other non-volatile storage.

Embodiments herein disclose a method of improving a layout, comprising: receiving a design layout; determining a first optical model and a first subset of photoresist correction terms for the photoresist model; performing model-based optical proximity correction (MOPC) and updating the design layout to obtain a first updated design layout based on the first optical model and the first subset of the photoresist model; determining a second optical model and a second subset of the photoresist correction terms for the photoresist model; performing MOPC according to the second optical model and the second subset of the photoresist model and updating the first design layout to obtain a second updated design layout; and manufacturing a photomask according to the second updated layout.

Embodiments herein disclose a method of improving a layout, comprising: receiving a design layout; determining an initial subset of photoresist correction terms as a new subset; determining a photoresist model from the new subset; determining an optical model; performing model-based optical proximity correction (MOPC) based on the optical model and the photoresist model and updating the design layout to a second updated layout; judging whether the second design layout meets the design specifications; and in response to the second design layout not meeting the design specification, performing the following steps: updating the new subset by maintaining original photoresist correction terms or including more photoresist correction terms; and MOPC is carried out on the second design layout according to the updating subset, and the second design layout is updated to obtain a third design layout.

Embodiments herein disclose a design layout system comprising one or more processors and one or more programs storing instructions that, when executed by the one or more processors, cause the system to perform the steps of: receiving a design layout; determining a first optical model and a first subset of photoresist correction terms for the photoresist model; performing model-based optical proximity correction (MOPC) and updating the design layout to obtain a first updated design layout based on the first optical model and the first subset of the photoresist model; determining a second optical model and a second subset of the photoresist correction terms for the photoresist model; performing MOPC according to the second optical model and the second subset of the photoresist model and updating the first design layout to obtain a second updated design layout; and manufacturing a photomask according to the second updated layout.

The foregoing describes features of several embodiments and thus those skilled in the art will more fully appreciate aspects of the embodiments of the invention. Those skilled in the art should appreciate that they may readily use the present embodiments as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the embodiments of the present disclosure.

Description of the symbols

100 Integrated Circuit (IC) manufacturing system

120 design company

122 design layout

130 photo mask factory

132 photomask layout preparation subsystem

134 design layout

144 photomask fabrication subsystem

146 photomask inspection subsystem

150 integrated circuit manufacturer

152 semiconductor wafer

154 integrated circuit test subsystem

160 Integrated Circuit (IC) device

202 design layout

210 regular optical proximity correction module

220 edge segmentation module

230 model type optical near-end correction module

240 photoetching process inspection module

402 optical database

404 photoresist database

410 fragment selection module

420 optical model module

430 photoresist model module

440 segment correction module

502 target object

504 ray

600 method

Step 602

Step 604

Step 606

608 step

610 step

612 step

614 step

700 iterative complexity schematic

800 method

802 step

Step 804

806 step

808 step

Step 810

Step 812

814 step

816 step

818 step

820 step

900 method

902 step

904 step

Step 906

908 step

910 step

912 step

914 step

916 step

918 step

1001 processor

1003 network interface

1005 input/output (I/O) device

1007 storage device

1008 bus

1009 memories

n iteration rounds.

Claims (10)

1. A method of improving a layout, comprising:

receiving a design layout;

determining a first optical model and a first subset of photoresist correction terms for the photoresist model;

performing model-based optical proximity correction (MOPC) according to the first optical model and the first subset of the photoresist model and updating the design layout to obtain a first updated design layout;

determining a second optical model and a second subset of the photoresist correction terms for the photoresist model;

performing MOPC according to the second optical model and the second subset of the photoresist model and updating the first design layout to obtain a second updated design layout; and

a photomask is manufactured according to the second updated layout.

2. The method of claim 1, further comprising fabricating a semiconductor device according to the photomask.

3. The method of claim 1, further comprising: retraining the photoresist model to obtain corresponding weight values for the first subset, wherein MOPC according to the first optical model and the first subset of the photoresist model comprises MOPC according to the corresponding weight values for the first subset.

4. The method of claim 1, wherein the second subset includes the first subset.

5. The method of claim 1, wherein the first optical model is a normal incidence model and the second optical model is an off-axis illumination model.

6. The method of claim 1, further comprising partitioning pattern edges of the design layout into a plurality of edge segments and classifying the edge segments into at least a first set of edge segments and a second set of edge segments, wherein MOPC the design layout according to the first subset and the first subset of the optical model comprises MOPC only the first set of edge segments, wherein MOPC the design layout according to the second optical model and the second subset of the photoresist model comprises MOPC the first set of edge segments and the second set of edge segments.

7. The method of claim 6, wherein classifying the edge segments into at least a first set of edge segments and a second set of edge segments comprises classifying one-dimensional graphics and two-dimensional graphics in the edge segments into the first set of edge segments and the second set of edge segments, respectively.

8. A method of improving a layout, comprising:

receiving a design layout;

determining an initial subset of photoresist correction terms as a new subset;

determining a photoresist model from the new subset;

determining an optical model;

performing model-based optical proximity correction (MOPC) according to the optical model and the photoresist model and updating the design layout to a second updated layout;

judging whether the second design layout meets the design specifications; and

in response to the second design layout not meeting the design specification, performing the following steps:

updating the new subset by maintaining original photoresist correction terms or including more photoresist correction terms; and

and MOPC is carried out on the second design layout according to the updating subset, and the second design layout is updated to obtain a third design layout.

9. The method of claim 8, further comprising segmenting pattern edges of the design layout into a plurality of edge segments and classifying the edge segments into at least a first set of size edge segments and a second set of size edge segments according to a critical dimension of the pattern edges, wherein performing a model-based optical proximity correction (MOPC) according to an optical model and the photoresist model comprises MOPC only on the first set of size edge segments.

10. A design layout system comprising one or more processors and one or more programs storing instructions that, when executed by the one or more processors, cause the system to perform the steps of:

receiving a design layout;

determining a first optical model and a first subset of photoresist correction terms for the photoresist model;

performing model-based optical proximity correction (MOPC) according to the first optical model and the first subset of the photoresist model and updating the design layout to obtain a first updated design layout;

determining a second optical model and a second subset of the photoresist correction terms for the photoresist model;

performing MOPC according to the second optical model and the second subset of the photoresist model and updating the first design layout to obtain a second updated design layout; and

a photomask is fabricated according to the second updated layout.

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