CN114709303A - Semiconductor process - Google Patents

Semiconductor process Download PDF

Info

Publication number
CN114709303A
CN114709303A CN202210319161.1A CN202210319161A CN114709303A CN 114709303 A CN114709303 A CN 114709303A CN 202210319161 A CN202210319161 A CN 202210319161A CN 114709303 A CN114709303 A CN 114709303A
Authority
CN
China
Prior art keywords
layer
etching
mask layer
active layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210319161.1A
Other languages
Chinese (zh)
Inventor
李玮乐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Naura Microelectronics Equipment Co Ltd
Original Assignee
Beijing Naura Microelectronics Equipment Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Naura Microelectronics Equipment Co Ltd filed Critical Beijing Naura Microelectronics Equipment Co Ltd
Priority to CN202210319161.1A priority Critical patent/CN114709303A/en
Publication of CN114709303A publication Critical patent/CN114709303A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials

Landscapes

  • Led Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The invention provides a semiconductor process method, which comprises the following steps: a first mask layer forming step, namely depositing a first mask layer on the top surface of the semiconductor epitaxial wafer, wherein the top layer of the semiconductor epitaxial wafer is an active layer of the semiconductor epitaxial wafer; a second mask layer forming step of manufacturing a patterned photoresist layer on the surface of the first mask layer; etching the first mask layer and the active layer; and the heat-resistant temperature of the first mask layer is higher than the preset process temperature of the etching step. The semiconductor process method provided by the invention can reduce the roughness of the side wall of the semiconductor epitaxial wafer after the active layer is etched by the dry method, thereby reducing the electric leakage of the light-emitting diode chip.

Description

Semiconductor process
Technical Field
The invention relates to the technical field of semiconductor equipment, in particular to a semiconductor process method.
Background
A Light-Emitting Diode (abbreviated as LED) is a commonly used Light-Emitting device and has a wide application in modern society. Aluminum gallium indium phosphide ((Al) lattice-matched to gallium arsenide (GaAs) substratexGa1-x)0.5In0.5P) material when x<0.53 it is a direct band gap material, has wide direct band gap, can cover visible light with wavelength of 560nm-650nm, and can be used for preparing red yellow light (wavelength range)560nm-940nm) of light emitting diode chip.
Dry etching is a key step in the process of preparing a red-yellow light emitting diode chip, an active layer (such as an aluminum gallium indium phosphorus layer) of a sapphire substrate epitaxial wafer needs to be subjected to dry etching, and in order to obtain a sidewall morphology with an inclination angle of 50-65 degrees, Positive photoresist (also called Positive photoresist) is usually selected for photoetching.
However, the heat resistance of the positive photoresist is poor, and the heat generated by Inductively Coupled Plasma (ICP) dry etching exceeds the tolerance range of the positive photoresist, so that during the dry etching, the surface of the positive photoresist is wrinkled or even shrunk, the positive photoresist cannot play a good protection role for the active layer of the semiconductor device, the sidewall is wrinkled or even shrunk along the surface of the positive photoresist, the sidewall after the dry etching is rough, the insulating layer is abnormally prepared, and the light emitting diode chip leaks electricity.
Disclosure of Invention
The invention aims to solve at least one technical problem in the prior art, and provides a semiconductor process method which can reduce the roughness of the side wall of an insulating layer of a semiconductor epitaxial wafer, so that the electric leakage of a light-emitting diode chip can be reduced.
To achieve the object of the present invention, a semiconductor process method is provided, which comprises the following steps:
a first mask layer forming step, namely depositing a first mask layer on the top surface of a semiconductor epitaxial wafer, wherein the top layer of the semiconductor epitaxial wafer is an active layer of the semiconductor epitaxial wafer;
a second mask layer forming step of manufacturing a patterned photoresist layer on the surface of the first mask layer;
an etching step of etching the first mask layer and the active layer;
and the heat-resistant temperature of the first mask layer is higher than the preset process temperature of the etching step.
Optionally, the etching step includes:
a first etching step of introducing a first etching gas and ionizing the first etching gas to etch the first mask layer;
and a second etching step, wherein second etching gas is introduced and ionized to etch the active layer.
Optionally, the second etching gas includes Cl2Either HBr or Cl2And H2Mixed gas of (2), or Cl2And HBr.
Optionally, the second etching gas further includes BCl3。
Optionally, the second etching gas is Cl2HBr and BCl3Mixed gas of (2), said Cl2The flow rate of the HBr is 3sccm to 15sccm, the flow rate of the HBr is 20sccm to 120sccm, and the BCl is3The flow rate of (b) is 5sccm to 20 sccm.
Optionally, the first etching gas is the same as the second etching gas.
Optionally, the cavity pressure of the first etching step is the same as that of the second etching step and is 2mTorr to 10mTorr, the upper rf power of the first etching step is the same as that of the second etching step and is 500W to 1000W, and the lower rf power of the first etching step is the same as that of the second etching step and is 300W to 500W.
Optionally, the thickness of the first mask layer is 200nm to 400 nm.
Optionally, the first mask layer is made of silicon oxide or silicon nitride.
Optionally, after the etching step, the semiconductor process further includes:
and removing the first mask layer, and depositing an insulating layer on the etched active layer.
Optionally, the semiconductor epitaxial wafer includes a sapphire substrate, and a gallium phosphide layer and an aluminum gallium indium phosphide layer formed on the sapphire substrate in sequence, where the aluminum gallium indium phosphide layer is the active layer.
The invention has the following beneficial effects:
the semiconductor process method provided by the invention comprises the steps of depositing a first mask layer on an active layer before etching the active layer, manufacturing a patterned photoresist layer on the surface of the first mask layer, and etching the first mask layer and the active layer through an etching step to realize the etching of the active layer, wherein the first mask layer does not generate folds due to the high temperature of the etching step in the etching step, namely the etching process of the active layer is realized, and the first mask layer is positioned between the photoresist layer and the active layer, so that the active layer can be protected by the first mask layer in the etching step, namely the etching process of the active layer, the influence of folds and even shrinkage of the photoresist layer on the active layer is reduced, the degree of folds generated on the side wall of the etched active layer due to the fact that the side wall of the etched active layer is smooth is reduced, the roughness of the side wall of the etched active layer can be reduced, the side wall of the etched active layer is smoother, the coating performance of an insulating layer prepared on the active layer subsequently can be improved, the abnormity of the insulating layer is reduced, and the electric leakage of a light-emitting diode chip can be reduced.
Drawings
FIG. 1 is a flow chart of a semiconductor processing method according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a semiconductor epitaxial wafer after a first mask layer is prepared on an active layer by using a semiconductor process method provided by an embodiment of the invention;
fig. 3 is a schematic structural diagram of a semiconductor epitaxial wafer after a patterned photoresist layer is formed on the surface of the first mask layer by using the semiconductor process method according to the embodiment of the present invention;
fig. 4 is a schematic structural diagram of a semiconductor epitaxial wafer after a first mask layer is etched by using the semiconductor process method provided by the embodiment of the invention;
fig. 5 is a schematic structural diagram of a semiconductor epitaxial wafer after an active layer is etched by using the semiconductor process method provided by the embodiment of the invention;
fig. 6 is a schematic structural diagram of a semiconductor epitaxial wafer after an electrode and an insulating layer are prepared on an active layer by using a semiconductor process method provided by an embodiment of the invention;
fig. 7 is an image of sidewalls of the photoresist layer and the active layer after etching the first mask layer and the active layer by using the semiconductor process method provided by the embodiment of the present invention;
FIG. 8 is a flowchart of an etching step of a semiconductor processing method according to an embodiment of the present invention;
FIG. 9 is another flow chart of a semiconductor processing method according to an embodiment of the present invention;
description of reference numerals:
1-a sapphire substrate; 21-a gallium phosphide layer; 22-an active layer; 3-a first mask layer; 4-a photoresist layer; 5-an electrode; 6-an insulating layer; 7-a bonding layer.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the semiconductor processing method provided by the present invention is described in detail below with reference to the accompanying drawings.
As shown in fig. 1 and fig. 2 to 5, an embodiment of the present invention provides a semiconductor processing method, including the steps of:
s1, a first mask layer 3 forming step, depositing a first mask layer 3 on the top surface of the semiconductor epitaxial wafer, where the top layer of the semiconductor epitaxial wafer is the active layer 22 of the semiconductor epitaxial wafer (as shown in fig. 2);
s2, a second mask layer forming step, forming a patterned photoresist layer 4 on the surface of the first mask layer 3 (as shown in fig. 4);
s3, an etching step, etching the first mask layer 3 and the active layer 22 (as shown in fig. 5);
the heat-resistant temperature of the first mask layer 3 is higher than the preset process temperature of the etching step.
In the semiconductor process method provided by the embodiment of the invention, before the active layer 22 is etched, the first mask layer 3 is deposited on the active layer 22, the patterned photoresist layer 4 is formed on the surface of the first mask layer 3, and then the first mask layer 3 and the active layer 22 are etched through the etching step to realize the etching of the active layer 22, because the heat-resistant temperature of the first mask layer 3 (i.e., the temperature before the strength of the first mask layer 3 starts to be significantly reduced) is higher than the preset process temperature of the etching step (i.e., the preset process temperature when the first mask layer 3 and the active layer 22 are etched), in the etching step, i.e., the etching of the active layer 22 is realized, the first mask layer 3 cannot generate wrinkles due to the high temperature of the etching step, and because the first mask layer 3 is located between the photoresist layer 4 and the active layer 22, in the etching step, that is, in the process of implementing the etching of the active layer 22, the first mask layer 3 may protect the active layer 22, reduce the influence of the wrinkle or even the shrinkage of the photoresist layer 4 on the active layer 22, and reduce the degree of the wrinkle generated on the sidewall of the etched active layer 22 due to the smooth extension of the photoresist layer 4, thereby reducing the roughness of the sidewall of the etched active layer 22, making the etched sidewall of the active layer 22 smoother (as shown in fig. 7), further improving the cladding performance of the insulating layer 6 subsequently prepared on the active layer 22, reducing the abnormality of the insulating layer 6 preparation, and further reducing the leakage current of the light emitting diode chip, so that when the active layer 22 is an algan-ga-p layer, and the algan-ga-p layer is etched by using the inductively coupled plasma dry etching process, the roughness of the sidewall of the algan-ga-p layer after dry etching can be reduced, making the sidewall of the algan-ga-p layer after dry etching be smoother, therefore, the coating performance of the insulating layer 6 prepared on the AlGaInP layer subsequently can be improved, the abnormity of the insulating layer 6 preparation can be reduced, and the electric leakage of the light-emitting diode chip can be reduced.
It should be noted that the first mask layer 3 is deposited on the top surface of the semiconductor epitaxial wafer, the top layer of the semiconductor epitaxial wafer is the active layer 22 of the semiconductor epitaxial wafer, that is, the active layer 22 is the top layer of the semiconductor epitaxial wafer, and the upper surface of the active layer 22 is the top surface of the semiconductor epitaxial wafer, so that the first mask layer 3 is deposited on the top surface of the semiconductor epitaxial wafer, that is, the first mask layer 3 is deposited on the active layer 22.
In a preferred embodiment of the present invention, the thickness of the first mask layer 3 may be 200nm to 400 nm.
The reason for this design is that if the thickness of the first mask layer 3 is too small (too thin), the first mask layer 3 cannot effectively protect the active layer 22, and cannot effectively reduce the influence of wrinkles and even shriveling of the photoresist layer 4 on the active layer 22, and if the thickness of the first mask layer 3 is too large (too thick), the inclination angle of the etched sidewall of the active layer 22 is too large, so that the sidewall of the etched active layer 22 is not prone to form a sidewall shape with an inclination angle of 50 ° -65 °.
As shown in fig. 2 to 6, in a preferred embodiment of the present invention, the semiconductor epitaxial wafer may include a sapphire substrate 1 and a gallium phosphide (GaP) layer 21 and an aluminum gallium indium phosphide (AlGaInP) layer, which is an active layer 22, sequentially formed on the sapphire substrate 1.
Alternatively, the photoresist used for the photoresist layer 4 may include a positive photoresist.
As shown in fig. 8, in a preferred embodiment of the present invention, S3, the etching step may include:
s31, a first etching step, wherein a first etching gas is introduced and ionized to etch the first mask layer 3;
s31, a second etching step, introducing a second etching gas, and ionizing the second etching gas to etch the active layer 22.
Since the first mask layer 3 is deposited on the active layer 22, in the etching step, when the first mask layer 3 and the active layer 22 are etched, the first mask layer 3 needs to be etched first, and then the active layer 22 needs to be etched, that is, in the etching step, the first mask layer 3 and the active layer 22 need to be etched in sequence, and the first mask layer 3 is etched first, when the first mask layer 3 is etched until the active layer 22 located below the first mask layer is exposed, the active layer 22 starts to be etched, and finally, the exposed first mask layer 3 not covered by the photoresist layer 4 is etched clean, and the exposed active layer 22 not covered by the first mask layer 3 is etched to a target depth to form a target topography.
When the first mask layer 3 is etched, the first etching gas may be ionized to form plasma by ionizing the first etching gas, so that the first mask layer 3 is etched by the plasma formed by ionizing the first etching gas, and when the active layer 22 is etched, the second etching gas may be ionized to form plasma by ionizing the second etching gas, so that the active layer 22 is etched by the plasma formed by ionizing the second etching gas.
It should be noted that this only indicates an etching step, and the etching of the first mask layer 3 and the active layer 22 is sequential, but does not indicate an etching step, and the etching of the first mask layer 3 and the active layer 22 must be performed in two steps, respectively, for example, when the first etching gas and the second etching gas are the same, the etching step may be performed in one step, and when the first etching gas and the second etching gas are different, the etching step may be performed in two steps, respectively, for etching the first mask layer 3 and the active layer 22.
In a preferred embodiment of the present invention, the first etching gas may be the same as the second etching gas.
By such a design, the semiconductor process for etching the first mask layer 3 and the active layer 22 can be continuously performed without switching the process gas and re-ionizing the process gas for re-ignition, so that the etched sidewall of the active layer 22 can be further smoothed.
In a preferred embodiment of the present invention, the material of the first mask layer 3 may be silicon oxide or silicon nitride.
Alternatively, the silicon oxide may be SiO2(silica).
Alternatively, the silicon nitride may comprise SiN, SiN2、SiN3Or SiN4。
Alternatively, in the etching step, the first mask layer 3 and the active layer 22 may be etched by using an Inductively Coupled Plasma (ICP) dry etching process.
Alternatively, in the step of forming the first mask layer 3, the first mask layer 3 may be deposited on the top surface of the semiconductor epitaxial wafer by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process.
For example, the process temperature for depositing the first mask layer 3 made of silicon nitride on the active layer 22 by using the plasma enhanced chemical vapor deposition process may be 200 ℃ to 300 ℃, and the heat-resistant temperature of the first mask layer obtained at the temperature is higher than the preset process temperature for etching the first mask layer 3 and the active layer 22 by using the inductively coupled plasma dry etching process, for example, 200 ℃, so that the first mask layer 3 made of silicon nitride deposited on the active layer 22 by using the plasma enhanced chemical vapor deposition process does not generate wrinkles due to the high temperature for etching the first mask layer 3 and the active layer 22 by using the inductively coupled plasma dry etching process.
In a preferred embodiment of the present invention, the first mask layer 3 is formed by depositing the first mask layer 3 on the top surface of the semiconductor epitaxial wafer at a chamber pressure of 60Pa (pascal) -140Pa, a High Frequency (HF) power of 50W (watt) -200W, a Low Frequency (Low Frequency) power of 50W-200W, a process temperature of 200 ℃ (celsius) -300 ℃, and a flow rate and type of the process gas may include a flow rate of 40sccm (milliliter Per Minute under Standard conditions) -80sccm of SiH4(silane), NH at a flow rate in the range of 20sccm to 80sccm3(Ammonia gas) and N at a flow rate in the range of 300sccm to 1200sccm2(Nitrogen).
Alternatively, the frequency of the high frequency radio frequency may be 13.56MHz (megahertz) or 27.12 MHz.
Alternatively, the frequency of the low frequency radio frequency may be 125kHz (kilohertz) or 133 kHz.
In a preferred embodiment of the present invention, the second etching gas may include Cl2(chlorine gas), or HBr (hydrogen bromide), or Cl2And H2(hydrogen) mixed gas, or Cl2And HBr.
In practice, Cl is ionized2Capable of generating Cl (chlorine radicals), and in particular, the relevant reactions may include: cl2→ 2Cl (chlorine gas generates chlorine radicals), when the first mask layer 3 is silicon nitride and the active layer 22 is algan, Cl can react with silicon nitride and algan to generate volatile gas, and the volatile gas can be pumped by a vacuum system of the process chamber, so that the first mask layer 3 made of silicon nitride and the active layer 22 made of algan can be etched. Specifically, Cl and aluminum galliumThe reaction associated with the reaction of indium phosphorous to produce volatile gases may include: indium In AlGaInP reacts with chlorine free radical to produce indium trichloride (In + Cl → InCl)3) The aluminum in the Al-Ga-in-P reacts with chlorine free radical to generate aluminum trichloride (Al + Cl → AlCl)3) The gallium in the AlGaInP reacts with the chlorine free radical to generate gallium trichloride (Ga + Cl → GaCl)3) Phosphorus in the aluminum-gallium-indium-phosphorus reacts with chlorine free radical to generate phosphorus trichloride and phosphorus pentachloride (P + Cl → PCl)3+PCl5)。
In practical applications, ionizing HBr can produce H (hydrogen radicals) and Br (bromine radicals), and in particular, the relevant reactions may include: HBr → H + Br (bromine radical is generated by hydrogen bromide), when the first mask layer 3 is silicon nitride and the active layer 22 is AlGaInP, Br can react with silicon nitride and AlGaInP to generate volatile gas, and the volatile gas can be pumped away by a vacuum-pumping system of the process chamber, so that the first mask layer 3 made of silicon nitride and the active layer 22 made of AlGaInP can be etched. Specifically, the relevant reaction of Br with algan to generate volatile gases may include: indium In the AlGaInP reacts with bromine radicals to produce indium tribromide (In + Br → InBr)3) The aluminum in the aluminum-gallium-indium-phosphorus reacts with bromine free radical to generate aluminum bromide (Al + Br → AlBr), and the gallium in the aluminum-gallium-indium-phosphorus reacts with bromine free radical to generate gallium tribromide (Ga + Br → GaBr)3) And phosphorus in AlGaInP reacts with bromine radicals to produce phosphorus tribromide and pentabromide (P + Br → PBr)3+PBr5)。
Moreover, because ionized HBr can also generate H (hydrogen radicals), which can play a passivation protection role on the aluminum gallium indium phosphide, the roughness of the etched side wall of the active layer 22 can be further reduced, the etched side wall of the active layer 22 can be further smooth, the coating performance of the insulating layer 6 prepared on the active layer 22 in the following process can be further improved, the preparation abnormity of the insulating layer 6 can be further reduced, and the electric leakage of the light emitting diode chip can be further reduced.
In practical application, when the second etching gas is Cl2And H2In the case of a mixed gas of (hydrogen gas), ionized Cl may be used2Generated Cl with silicon nitride andthe AlGaInP reaction generates volatile gas, so that the first mask layer 3 made of silicon nitride and the active layer 22 made of AlGaInP can be etched, and ionization H can be used2The generated H plays a role in passivation protection on the AlGaInP, so that the roughness of the side wall of the active layer 22 after etching can be further reduced, the side wall of the active layer 22 after etching is further smoother, the coating property of the insulating layer 6 prepared on the active layer 22 subsequently can be further improved, the abnormity of the insulating layer 6 can be further reduced, and the electric leakage of the light-emitting diode chip can be further reduced.
In practical application, when the second etching gas is Cl2And HBr, ionized Cl can be used2The generated Cl and Br generated by ionizing HBr react with silicon nitride and aluminum gallium indium phosphide to generate volatile gas, so that the first mask layer 3 made of silicon nitride and the active layer 22 made of aluminum gallium indium phosphide can be etched, H generated by ionizing HBr can be used for performing passivation protection on the aluminum gallium indium phosphide, the roughness of the side wall of the active layer 22 after etching can be further reduced, the etched side wall of the active layer 22 is further smooth, the cladding performance of the insulating layer 6 prepared on the active layer 22 subsequently can be further improved, the abnormity of the insulating layer 6 can be further reduced, and the electric leakage of the light-emitting diode chip can be further reduced.
In a preferred embodiment of the present invention, the second etching gas may further include BCl3(boron trichloride).
In practical applications, BCl is ionized3Capable of generating Cl, in particular, the relevant reactions may include: (BCl)3→BClx+ Cl (x ═ 0, 1, 2)), when the second etching gas is BCl3Then, ionized BCl can be utilized3The generated Cl reacts with the silicon nitride and the aluminum gallium indium phosphide to generate volatile gas, thereby realizing the etching of the first mask layer 3 made of the silicon nitride and the active layer 22 made of the aluminum gallium indium phosphide, and the BCl is used for etching the first mask layer 3 made of the silicon nitride and the active layer 22 made of the aluminum gallium indium phosphide3Can increase the plasma bombardment energy, and BClxCan also react with oxygen (O) to remove impurities from the semiconductor epitaxial wafer in the process chamberOxygen in the film layer prevents the aluminum gallium indium phosphide from reacting with oxygen to generate aluminum oxide (Al)2O3) Thereby enabling the bottom wall of the active layer 22 to be smoothed.
In a preferred embodiment of the present invention, the second etching gas may be Cl2HBr and BCl3Mixed gas of (2), Cl2The flow rate of the HBr can be 3sccm to 15sccm, and the flow rate of the HBr can be 20sccm to 120sccm, BCl3The flow rate of (c) may be 5sccm to 20 sccm.
So that Cl can be bound2HBr and BCl3The advantages of the three gases include that on one hand, the first mask layer 3 made of silicon nitride and the active layer 22 made of aluminum gallium indium phosphide can be etched, on the other hand, the passivation protection effect of H on the aluminum gallium indium phosphide can be utilized, the roughness of the etched side wall of the active layer 22 is further reduced, the etched side wall of the active layer 22 is further smooth, the coating performance of the insulating layer 6 prepared on the active layer 22 in the follow-up process can be further improved, the abnormity of the insulating layer 6 is further reduced, the electric leakage of the light emitting diode chip can be further reduced, on the other hand, the BCl can be utilizedxPerforming oxidation reaction with oxygen to remove oxygen from each film layer on the semiconductor epitaxial wafer in the process chamber, thereby preventing aluminum oxide (Al) from being generated by the reaction of aluminum gallium indium phosphide and oxygen2O3) Thereby enabling the bottom wall of the active layer 22 to be smoothed.
In a preferred embodiment of the present invention, the chamber pressure of the first etching step and the second etching step can be the same and can be 2mTorr to 10mTorr, the upper radio frequency power (SRF) of the first etching step and the second etching step can be the same and can be 500W to 1000W, and the lower radio frequency power (BRF) can be the same and can be 300W to 500W. The first etching step and the second etching step can be continuously carried out, the continuity and the stability of the process can be ensured by the same process gas and process parameters, and the formed side wall is more smooth.
As shown in fig. 9, optionally, after the etching step of etching the first mask layer 3 and the active layer 22 at S3, the semiconductor processing method may further include:
s4, the first mask layer 3 is removed, and the insulating layer 6 is deposited on the etched active layer 22.
The insulating layer 6 can prevent leakage current. Alternatively, the insulating layer 6 may comprise SiO2And (3) a membrane.
Optionally, removing the first mask layer 3 may include the steps of:
soaking the semiconductor epitaxial wafer in etching liquid for removing the first mask layer 3;
and washing and drying the semiconductor epitaxial wafer.
Alternatively, the etching solution may include a Buffered Oxide Etch (BOE for short). The buffered oxide etching solution can etch the silicon-containing material, thereby etching the first mask layer 3 made of silicon oxide or silicon nitride.
Alternatively, the time for immersing the semiconductor epitaxial wafer in the etching solution for removing the first mask layer 3 may be 120s (seconds) to 360 s.
As shown in fig. 6, alternatively, the step of sequentially forming the gallium phosphide layer 21 and the aluminum gallium indium phosphide layer on the sapphire substrate 1 may include: preparing a gallium arsenide (AsGa) substrate; epitaxially growing a gallium phosphide layer 21 on the gallium arsenide substrate, and epitaxially growing an aluminum gallium indium phosphide layer on the gallium phosphide layer 21; stripping the gallium arsenide substrate from the gallium phosphide layer 21 and the aluminum gallium indium phosphide layer; preparing a bonding layer 7 on the sapphire substrate 1; and bonding the stripped gallium phosphide layer 21 and the aluminum gallium indium phosphide layer with the bonding layer 7. Thus, a gallium phosphide layer 21 and an aluminum gallium indium phosphide layer can be formed in this order on the sapphire substrate 1.
Optionally, in S3, after the etching step of etching the first mask layer 3 and the active layer 22, in S4, before removing the first mask layer 3 and depositing the insulating layer 6 on the etched active layer 22, the semiconductor process method may further include the steps of: the photoresist layer 4 is removed.
Optionally, S2, the step of forming a second mask layer, forming the patterned photoresist layer 4 on the surface of the first mask layer 3, may include: spin-coating a photoresist on the first mask layer 3; baking the photoresist layer 4 to form the photoresist layer 4 on the first mask layer 3; exposing the photoresist layer 4, namely, performing mark photoetching; developing the photoresist layer 4 to form a pattern; the photoresist layer 4 is rinsed and dried.
As shown in fig. 6, optionally, after the etching step of etching the first mask layer 3 and the active layer 22 at S3, the semiconductor processing method may further include: the electrode 5 is prepared on the active layer 22.
Alternatively, the electrode 5 may include a positive electrode and a negative electrode.
In summary, the semiconductor process method provided by the embodiment of the invention can reduce the roughness of the side wall after the aluminum gallium indium phosphorus layer is etched by the dry method, so that the electric leakage of the light emitting diode chip can be reduced.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention, and these changes and modifications are to be considered as within the scope of the invention.

Claims (11)

1. A semiconductor process method is characterized by comprising the following steps:
a first mask layer forming step, namely depositing a first mask layer on the top surface of a semiconductor epitaxial wafer, wherein the top layer of the semiconductor epitaxial wafer is an active layer of the semiconductor epitaxial wafer;
a second mask layer forming step of manufacturing a patterned photoresist layer on the surface of the first mask layer;
an etching step of etching the first mask layer and the active layer;
and the heat-resistant temperature of the first mask layer is higher than the preset process temperature of the etching step.
2. The semiconductor processing method according to claim 1, wherein the etching step comprises:
a first etching step of introducing a first etching gas and ionizing the first etching gas to etch the first mask layer;
and a second etching step of introducing a second etching gas and ionizing the second etching gas to etch the active layer.
3. The semiconductor processing method of claim 2, wherein the second etching gas comprises Cl2Either HBr or Cl2And H2Mixed gas of (2), or Cl2And HBr.
4. The semiconductor processing method of claim 3, wherein the second etching gas further comprises BCl3。
5. The semiconductor processing method according to claim 3, wherein the second etching gas is Cl2HBr and BCl3Mixed gas of (2), said Cl2The flow rate of the HBr is 3sccm to 15sccm, the flow rate of the HBr is 20sccm to 120sccm, and the BCl is3The flow rate of (b) is 5sccm to 20 sccm.
6. The semiconductor processing method according to claim 2, wherein the first etching gas is the same as the second etching gas.
7. The semiconductor process method according to claim 2, wherein the chamber pressure of the first etching step is the same as that of the second etching step and is 2mTorr to 10mTorr, the upper rf power of the first etching step is the same as that of the second etching step and is 500W to 1000W, and the lower rf power of the first etching step is the same as that of the second etching step and is 300W to 500W.
8. The semiconductor processing method according to claim 1, wherein the thickness of the first mask layer is 200nm to 400 nm.
9. The semiconductor process of claim 1, wherein the first mask layer is made of silicon oxide or silicon nitride.
10. The semiconductor processing method according to claim 1, wherein after the etching step, the semiconductor processing method further comprises:
and removing the first mask layer, and depositing an insulating layer on the etched active layer.
11. The semiconductor process method according to claim 1, wherein the semiconductor epitaxial wafer comprises a sapphire substrate and a gallium phosphide layer and an aluminum gallium indium phosphide layer which are sequentially formed on the sapphire substrate, and the aluminum gallium indium phosphide layer is the active layer.
CN202210319161.1A 2022-03-29 2022-03-29 Semiconductor process Pending CN114709303A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210319161.1A CN114709303A (en) 2022-03-29 2022-03-29 Semiconductor process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210319161.1A CN114709303A (en) 2022-03-29 2022-03-29 Semiconductor process

Publications (1)

Publication Number Publication Date
CN114709303A true CN114709303A (en) 2022-07-05

Family

ID=82170729

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210319161.1A Pending CN114709303A (en) 2022-03-29 2022-03-29 Semiconductor process

Country Status (1)

Country Link
CN (1) CN114709303A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115632096A (en) * 2022-10-28 2023-01-20 北京北方华创微电子装备有限公司 Method for manufacturing light emitting device
CN115632096B (en) * 2022-10-28 2026-03-24 北京北方华创微电子装备有限公司 Method for manufacturing light-emitting device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6069091A (en) * 1997-12-29 2000-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ sequential silicon containing hard mask layer/silicon layer plasma etch method
KR20050070737A (en) * 2003-12-30 2005-07-07 동부아남반도체 주식회사 Method for manufacturing semiconductor devices
US20100244247A1 (en) * 2009-03-27 2010-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Via structure and via etching process of forming the same
CN102214567A (en) * 2010-04-02 2011-10-12 中芯国际集成电路制造(上海)有限公司 Method for forming grooves
CN105097539A (en) * 2014-05-21 2015-11-25 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6069091A (en) * 1997-12-29 2000-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ sequential silicon containing hard mask layer/silicon layer plasma etch method
KR20050070737A (en) * 2003-12-30 2005-07-07 동부아남반도체 주식회사 Method for manufacturing semiconductor devices
US20100244247A1 (en) * 2009-03-27 2010-09-30 Taiwan Semiconductor Manufacturing Company, Ltd. Via structure and via etching process of forming the same
CN102214567A (en) * 2010-04-02 2011-10-12 中芯国际集成电路制造(上海)有限公司 Method for forming grooves
CN105097539A (en) * 2014-05-21 2015-11-25 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115632096A (en) * 2022-10-28 2023-01-20 北京北方华创微电子装备有限公司 Method for manufacturing light emitting device
CN115632096B (en) * 2022-10-28 2026-03-24 北京北方华创微电子装备有限公司 Method for manufacturing light-emitting device

Similar Documents

Publication Publication Date Title
KR101377866B1 (en) Selective etch chemistries for forming high aspect ratio features and associated structures
JP5933694B2 (en) Method for dry stripping boron carbon films
KR20120098487A (en) Semiconductor device manufacturing method
CN1963999A (en) Method for forming trench using hard mask with high selectivity and isolation method for semiconductor device using the same
CN109690735B (en) Stripping method for high aspect ratio structures
CN116721915B (en) SiC etching method and equipment
TWI903825B (en) Method for manufacturing semiconductor device and semiconductor process equipment
CN107706108A (en) A method for fabricating a junction terminal of a silicon carbide device
CN117334574A (en) Post-processing of indium-containing compound semiconductors
Lee et al. Highly selective dry etching of III nitrides using an inductively coupled Cl 2/Ar/O 2 plasma
KR102070350B1 (en) Deposition of heteroatom-doped carbon films
US20040157435A1 (en) Methods of forming metal lines in semiconductor devices
CN114709303A (en) Semiconductor process
KR100549204B1 (en) Silicon anisotropic etching method
JP2013165262A (en) Optical semiconductor element manufacturing method
CN115911193B (en) Preparation method of quantum dot single photon source micro-column cavity and single photon source sample wafer
CN115376908B (en) Etching method of GaN substrate
CN113851376B (en) Methods of forming semiconductor structures
KR100190498B1 (en) Etching method for polysilicon film
JP2005150404A (en) Dry etching method of multilayer film comprising compound semiconductor
CN114373684A (en) Ga2O3Method for patterning material
JP3672585B2 (en) Method for manufacturing group 3 nitride semiconductor
JPH0485928A (en) Dry etching method
JPH05217965A (en) Manufacture of semiconductor device
CN116314006B (en) Method for manufacturing semiconductor structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20220705