CN114709142A - Fan-out stack packaging method, chip packaging structure and electronic equipment - Google Patents

Fan-out stack packaging method, chip packaging structure and electronic equipment Download PDF

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Publication number
CN114709142A
CN114709142A CN202210344643.2A CN202210344643A CN114709142A CN 114709142 A CN114709142 A CN 114709142A CN 202210344643 A CN202210344643 A CN 202210344643A CN 114709142 A CN114709142 A CN 114709142A
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China
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chip
layer
fan
redistribution layer
packaging method
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CN202210344643.2A
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Chinese (zh)
Inventor
王森民
孔德荣
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Yongsi Semiconductor Ningbo Co ltd
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Yongsi Semiconductor Ningbo Co ltd
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Priority to CN202210344643.2A priority Critical patent/CN114709142A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The application provides a fan-out stack packaging method, a chip packaging structure and electronic equipment, and relates to the field of semiconductors. The chip packaging structure and the packaging structure manufactured by the fan-out stack packaging method comprise a first rewiring layer, a second rewiring layer, a first plastic package body, a first chip, a second chip, a first tin ball and a routing bonding pad. The first chip and the first plastic package body are positioned between the first re-wiring layer and the second re-wiring layer, the first solder balls are positioned on the second re-wiring layer, the second chip is arranged on one side of the first re-wiring layer, which is far away from the first chip in an overlapping mode, and the first solder balls electrically connected to the second re-wiring layer and the routing bonding pads electrically connected to the first re-wiring layer can serve as signal connection points. The fan-out stack packaging method and the packaging structure can effectively reduce the packaging area and further improve the function integration level of unit area, thereby obtaining finer wiring line width and high-density packaging structure.

Description

Fan-out stack packaging method, chip packaging structure and electronic equipment
Technical Field
The application relates to the field of semiconductors, in particular to a fan-out stack packaging method, a chip packaging structure and electronic equipment.
Background
With the rapid development of the semiconductor industry, the fan-out packaging structure is widely applied to the semiconductor industry, but the fan-out packaging is limited to be spread on a plane, and the traditional fan-out packaging can cause the whole area to be too large for multi-chip integration.
Disclosure of Invention
The purpose of the present application includes providing a fan-out stack packaging method, a chip packaging structure and an electronic device, which can improve the function integration level of the packaging structure in unit area, and is beneficial to the miniaturization of the chip packaging structure and the electronic device.
The embodiment of the application can be realized as follows:
in a first aspect, the present application provides a fan-out stack packaging method, including:
manufacturing a first redistribution layer on the carrier, and manufacturing a first conductive pillar on the first redistribution layer;
the first chip is inversely mounted to the first re-wiring layer, wherein a second conductive pillar is arranged on the first chip in advance, and the first chip is electrically connected with the first re-wiring layer through the second conductive pillar;
manufacturing a first plastic packaging body to wrap the first chip, the first conductive column and the second conductive column and expose one end of the first conductive column, which is far away from the carrier;
manufacturing a second redistribution layer on the first plastic package body, and manufacturing a first solder ball on the second redistribution layer, wherein the second redistribution layer is electrically connected with the first redistribution layer through a first conductive pillar;
and separating the carrier from the first rewiring layer, arranging a second chip and a routing pad for externally connecting a lead on one side of the first rewiring layer, which is far away from the first plastic package body, and electrically connecting the routing pad and the second chip with the first rewiring layer.
In an optional embodiment, the step of providing the second chip and the wire bonding pad for external connection of the lead on the side of the first redistribution layer away from the first plastic package body includes:
a third rewiring layer is arranged on the first rewiring layer and electrically connected with the second rewiring layer, and a routing bonding pad is formed on one side, away from the second rewiring layer, of the third rewiring layer;
and the second chip is inversely arranged on the third re-new wiring layer.
In an optional embodiment, a third conductive pillar is disposed on the second chip, and the second chip is electrically connected to the third redistribution layer through the third conductive pillar; the fan-out stack packaging method further comprises:
and manufacturing a second plastic packaging body to wrap the third conductive post.
In an optional embodiment, the fan-out stack packaging method further comprises:
manufacturing a second conductive column on the wafer of the first chip;
and manufacturing a third conductive column on the wafer of the second chip.
In an optional embodiment, the fan-out stack packaging method further comprises:
electrically connecting the second rewiring layer with the substrate through the first solder balls;
and arranging a lead to electrically connect the routing bonding pad with the substrate.
In an alternative embodiment, the step of exposing an end of the first conductive pillar away from the carrier includes:
and grinding the first plastic package body to expose one end of the first conductive column far away from the carrier.
In an optional embodiment, after the step of separating the carrier from the first redistribution layer and before the step of disposing the second chip on the side of the first redistribution layer away from the first molding compound, the fan-out stack packaging method further includes: attaching the second rewiring layer to the carrier through the temporary film;
after the step of disposing the second chip on the side of the first redistribution layer away from the first plastic package body, the fan-out stack packaging method further includes: and removing the carrier and the temporary film on the second re-wiring layer.
In an alternative embodiment, the step of flip-chip mounting the first chip to the first re-wiring layer includes flip-chip mounting the plurality of first chips to the first re-wiring layer;
after the step of disposing the second chip on the side of the first redistribution layer away from the first plastic package body, the fan-out stack packaging method further includes: and cutting to form single chip packaging structures.
In an optional embodiment, the first conductive pillar and the second conductive pillar are both copper pillars.
In an optional embodiment, the fan-out stack packaging method further comprises:
manufacturing a second conductive column on the wafer of the first chip;
and manufacturing a third conductive column on the wafer of the second chip.
In a second aspect, the present application provides a chip package structure, including:
the first redistribution layer and the second redistribution layer are arranged at intervals and connected through the first conductive pillar;
a first chip disposed between the first re-wiring layer and the second re-wiring layer, the first chip being flip-mounted to the first re-wiring layer through the second conductive pillar;
the first plastic package body wraps the first chip, the first conductive column and the second conductive column;
the second chip is arranged on one side, away from the first plastic package body, of the first rewiring layer and is electrically connected with the first rewiring layer;
the routing bonding pad is used for connecting a lead, is arranged on one side of the first rewiring layer, which is far away from the first plastic package body, and is electrically connected with the first rewiring layer;
and the first solder balls are arranged on the second re-wiring layer.
In an alternative embodiment, the chip package structure further includes:
and the third re-wiring layer is arranged on one side of the first re-wiring layer, which is far away from the first plastic package body, and is electrically connected with the first re-wiring layer, the second chip is inversely arranged on the third re-wiring layer, and the routing bonding pad is formed on one side of the third re-wiring layer, which is far away from the first re-wiring layer, and is electrically connected with the third re-wiring layer.
In an alternative embodiment, the second chip is electrically connected to the third redistribution layer through the third conductive pillar; the chip packaging structure further comprises a second plastic packaging body, and the second plastic packaging body wraps the third conductive column.
In an optional embodiment, the chip package structure further includes a substrate electrically connected to the second redistribution layer through the first solder ball, and a lead electrically connecting the wire bonding pad to the substrate.
In a third aspect, the present application provides an electronic device including the chip packaging structure of the foregoing embodiment.
The beneficial effects of the embodiment of the application include:
the chip packaging structure and the packaging structure manufactured by the fan-out stack packaging method comprise a first rewiring layer, a second rewiring layer, a first plastic package body, a first chip, a second chip, a first tin ball and a routing bonding pad. The first chip and the first plastic package body are positioned between the first re-wiring layer and the second re-wiring layer, the first solder balls are positioned on the second re-wiring layer, the second chip is arranged on one side of the first re-wiring layer, which is far away from the first chip in an overlapping mode, and the first solder balls electrically connected to the second re-wiring layer and the routing bonding pads electrically connected to the first re-wiring layer can serve as signal connection points. The fan-out stack packaging method can realize the comprehensive packaging of the first chip, improves the packaging reliability, and has the characteristics of small volume and capability of carrying more signal connection points. The fan-out stack packaging method and the chip packaging structure can effectively reduce the packaging area and further improve the function integration level of a unit area, so that a more fine wiring line width and a high-density packaging structure are obtained, and heterogeneous integration can be achieved by combining a plurality of chips with different functions, so that higher function requirements can be met.
The electronic equipment provided by the embodiment of the application comprises the chip packaging structure, and multifunctional integration and miniaturization are easy to realize.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
FIG. 1 is a flow diagram of a fan-out stack packaging method in one embodiment of the present application;
fig. 2 to 13 are schematic views of a chip package structure in different forms during a manufacturing process according to an embodiment of the present application.
Icon: 010-chip package structure; 100-a first rewiring layer; 110 — a first line; 120-a first passivation layer; 130-a first conductive post; 200-a first chip; 210-a second conductive post; 220-chip passivation layer; 230-a second chip; 240-third conductive pillars; 300-a first plastic package body; 310-a second plastic package body; 400-a second rewiring layer; 410-a second line; 420-a second passivation layer; 430-first solder ball; 500-a third rewiring layer; 510-a third line; 520-a third passivation layer; 530-routing bonding pads; 600-a substrate; 610-second solder ball; 700-lead; 020-a carrier; 021-glue film; 022-temporary film.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present application, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. are used for indicating the orientation or positional relationship based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship which the present invention product is usually put into use, it is only for convenience of describing the present application and simplifying the description, but it is not intended to indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation and be operated, and thus, should not be construed as limiting the present application.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
It should be noted that the features of the embodiments of the present application may be combined with each other without conflict.
In the prior art, the connection between the chip and the external circuit can be realized by means of metal Wire Bonding (Wire Bonding), i.e. Wire Bonding technology. With the shrinking of the feature size of the chip and the increasing of the integration level of the integrated circuit, the wire bonding technology no longer meets the development requirement of the technology. As chips become smaller and smaller, the number of signal contacts increases, and the conventional package cannot meet the requirement of high number of contacts. Wafer level fan-out packaging technology (FOWLP) is a supplement to wafer level chip packaging technology, a chip signal contact port is led out in a wafer reconstruction mode, a solder ball or a bump is formed on a reconstructed plastic package body, and the packaging structure can replace a traditional lead key and solder ball array packaging or flip chip solder ball array packaging (the number of <500 signal contacts) in a certain range, and is suitable for the field of portable consumer electronics. The conventional fan-out package is generally spread on a plane, when a product needs more functions, the overall package area is too large due to the spread of the plane, chips carried on a reconstruction wafer are reduced, the package cost is relatively high, and the excessively large package area is easily affected by warpage when the chip is cut into a single chip, so that an abnormality is easily generated when the chip is subsequently mounted on a substrate.
In order to solve the above problems, embodiments of the present application provide a fan-out stack package method and a chip package structure, which can reduce a package area and increase signal connection points, thereby obtaining a finer wiring line width and a higher density package structure. Moreover, the chip packaging structure manufactured by the packaging method has better reliability, and better performance is ensured under the condition of reducing the packaging volume.
Fig. 1 is a schematic diagram of a chip package structure 010 according to an embodiment of the present disclosure. As shown in fig. 1, the chip package structure 010 of the embodiment of the present application includes:
first and second re-wiring layers 100 and 400 arranged at intervals, the first and second re-wiring layers 100 and 400 being connected by first conductive pillars 130;
a first chip 200 located between the first re-wiring layer 100 and the second re-wiring layer 400, the first chip 200 being flip-mounted to the first re-wiring layer 100 by the second conductive pillars 210;
the first plastic package body 300, the first chip 200, the first conductive pillar 130 and the second conductive pillar 210 are wrapped by the first plastic package body 300;
the second chip 230, the second chip 230 is disposed on a side of the first redistribution layer 100 away from the first plastic package body 300, and is electrically connected to the first redistribution layer 100;
a bonding pad 530 for connecting the lead 700, wherein the bonding pad 530 is disposed on a side of the first redistribution layer 100 away from the first plastic package body 300, and is electrically connected to the first redistribution layer 100;
and first solder balls 430 disposed on the second redistribution layer 400.
In the embodiment of the present application, the first conductive pillar 130 and the second conductive pillar 210 are both copper pillars. Further, the chip package structure 010 further includes a third redistribution layer 500, the third redistribution layer 500 is disposed on a side of the first redistribution layer 100 away from the first plastic package body 300 and electrically connected to the first redistribution layer 100, the second chip 230 is flip-chip mounted on the third redistribution layer 500, and the wire bonding pad 530 is formed on a side of the third redistribution layer 500 away from the first redistribution layer 100 and electrically connected to the third redistribution layer 500.
Further, the second chip 230 is electrically connected to the third redistribution layer 500 through the third conductive pillar 240; the chip package structure 010 further includes a second molding compound 310, and the second molding compound 310 wraps the third conductive pillar 240. In an alternative embodiment, the second molding compound 310 may further encapsulate the second chip 230. In the present embodiment, the chip package structure 010 includes one first chip 200 and two second chips 230.
In addition, the chip package structure 010 provided in the embodiment of the present application further includes a substrate 600, a lead 700, and a second solder ball 610, where the substrate 600 has a circuit thereon, the substrate 600 is electrically connected to the second redistribution layer 400 through the first solder ball 430, the lead 700 electrically connects the wire bonding pad 530 to the substrate 600, and the second solder ball 610 is disposed on a side of the substrate 600 away from the first chip 200 and the second chip 230. Specifically, one end of the lead 700 is connected to the bonding pad 530, and the other end is connected to a connection point on the substrate 600, where the connection point is a portion of the circuit of the substrate 600 exposed on the surface.
In this embodiment, the first chip 200 and the second chip 230 can perform information interaction, and the structure can realize the comprehensive encapsulation of the first chip 200, so that the reliability is improved. The chip package structure 010 provided by the embodiment of the application has a small volume and can carry more signal connection points. Compared with the conventional fan-out package which is usually developed only in a plane space, the chip package structure 010 can effectively reduce the package area and further improve the function integration level of a unit area, so that a more precise wiring line width and a high-density package structure are obtained, and higher function requirements in the future can be met.
FIG. 2 is a flow diagram of a fan-out stack packaging method in an embodiment of the present application; fig. 3 to 13 are schematic diagrams illustrating a chip package structure 010 in different forms during a manufacturing process according to an embodiment of the disclosure. As shown in fig. 2 to 13, a fan-out stack packaging method provided by the embodiment of the present application includes:
step S100 is to fabricate a first redistribution layer on the carrier, and fabricate a first conductive pillar on the first redistribution layer.
In an alternative embodiment, the material of the carrier 020 may be glass or silicon, and the first conductive pillar 130 may be a copper pillar. Specifically, as shown in fig. 3, an adhesive film 021 may be first laid on the carrier 020, and the first redistribution layer 100 is fabricated on the adhesive film 021, where the first redistribution layer 100 includes the first circuit 110 and the first passivation layer 120 covering the first circuit 110, the first circuit 110 is connected to the first conductive pillar 130 to implement signal transmission, and the first passivation layer 120 plays an insulating role. The first passivation layer 120 should expose a part of the first circuit 110 (such as exposing a pad), so as to facilitate the first conductive pillar 130 and the second conductive pillar 210 in subsequent process steps to connect the first circuit 110. Specifically, the first conductive pillar 130 may be soldered to the first circuit 110.
In the embodiment of the present invention, a chip region and a conductive pillar region may be firstly divided on the carrier 020, the conductive pillar region is used for disposing the first conductive pillar 130, and the chip region is used for mounting the first chip 200 in the subsequent steps.
In an alternative embodiment, the first redistribution layer 100 (both in the same plane) and the first conductive pillars 130 required by the multiple chip package structures 010 can be fabricated on the carrier 020 at one time, so that the fabrication of the multiple chip package structures 010 can be completed at one time. Fig. 3 shows that the first redistribution layer 100 and the first conductive pillar 130 required by the two chip package structures 010 are simultaneously disposed on the carrier 020.
Step S200, flip-chip mounting the first chip to the first redistribution layer, where a second conductive pillar is pre-disposed on the first chip, and the first chip is electrically connected to the first redistribution layer through the second conductive pillar.
Optionally, the fan-out stack packaging method of the embodiment of the present application further includes a step of disposing the second conductive pillars 210 on the first chip 200. As shown in fig. 4, the second conductive pillars 210 should be connected with pins of the first chip 200 to realize signal transmission. Optionally, the step of fabricating the second conductive pillars 210 on the first chip 200 may be performed on a wafer of the first chip 200, so as to facilitate processing of the plurality of first chips 200 on the same wafer, and form a plurality of first chips 200 having the second conductive pillars 210. Fig. 4 shows two first chips 200 on the same wafer without being separated. Optionally, the second conductive pillar 210 is a copper pillar. In this embodiment, a chip passivation layer 220 is disposed on the first chip 200, and the chip passivation layer 220 exposes the pins of the first chip 200, so that the second conductive pillars 210 can be connected to the pins of the first chip 200. Specifically, the second conductive pillars 210 may be soldered to pins of the first chip 200.
As shown in fig. 5, in the embodiment of the present application, the end portion of the second conductive pillar 210 is connected to the first line 110 of the first re-wiring layer 100 through the opening of the first passivation layer 120. Alternatively, the second conductive pillars 210 may be soldered to the first lines 110 of the first re-routing layer 100 (e.g., by tin or tin-silver solder).
Step S300, a first plastic package body is manufactured to wrap the first chip, the first conductive pillar and the second conductive pillar, and one end of the first conductive pillar, which is far away from the carrier, is exposed.
As shown in fig. 5, in the present embodiment, the overall height of the second conductive pillars 210 and the second chip 230 is smaller than the height of the first conductive pillars 130. Therefore, the first chip 200, the first conductive pillars 130 and the second conductive pillars 210 may be encapsulated by filling or molding the molding compound (as shown in fig. 6, the height of the first molding compound 300 is higher than that of the first conductive pillars 130), and then the first molding compound 300 is polished to expose one end of the first conductive pillars 130 away from the carrier 020 (as shown in fig. 7).
Step S400 is to fabricate a second redistribution layer on the first plastic package body, and fabricate a first solder ball on the second redistribution layer, where the second redistribution layer is electrically connected to the first redistribution layer through the first conductive pillar.
As shown in fig. 8, the second redistribution layer 400 includes a second line 410 and a second passivation layer 420 covering the second line 410, wherein the second line 410 is used for signal transmission, and the second passivation layer 420 is used for insulation. The second circuit 410 is connected to the first conductive pillar 130 to implement signal transmission. The second passivation layer 420 exposes the openings for ball attachment so that the first solder balls 430 can be connected to the second lines 410 in the second re-wiring layer 400 through the openings.
Step S500, separating the carrier from the first rewiring layer, and arranging a second chip and a routing pad for externally connecting a lead on one side of the first rewiring layer, which is far away from the first plastic package body, wherein the routing pad and the second chip are electrically connected with the first rewiring layer.
As shown in fig. 9, the carrier 020 is peeled off from the first rewiring layer 100, and the adhesive film 021 is also peeled off from the first rewiring layer 100. In order to improve the process stability and thus the product yield, in the present embodiment, after the step of separating the carrier 020 from the first redistribution layer 100 and before the step of disposing the second chip 230 on the side of the first redistribution layer 100 away from the first molding compound 300, the second redistribution layer 400 may be attached to the carrier 020 through a temporary film 022 (the carrier 020 may be a carrier that previously supported the first redistribution layer 100, or may not be a carrier), as shown in fig. 10. Then, the second chip 230 and the wire bonding pad 530 are disposed on the side of the first redistribution layer 100 away from the first plastic package body 300. In other words, in the embodiment shown in fig. 10, one side of the package structure (semi-finished product) is supported by the carrier 020 instead, so that the side where the first redistribution layer 100 is located can be processed conveniently, and the temporary film 022 can play a role of buffer, which has certain flexibility and can protect the first solder balls 430 from being damaged by stress. Meanwhile, the temporary film 022 also has a certain viscosity, so that the packaging structure can be adhered to the carrier 020 to play a positioning role, which is similar to the function of the adhesive film 021. After the package structure (semi-finished product) is supported by the surface change, a third redistribution layer 500 is disposed on the first redistribution layer 100, the third redistribution layer 500 is electrically connected to the second redistribution layer 400, and a wire bonding pad 530 is formed on a side of the third redistribution layer 500 away from the second redistribution layer 400; the second chip 230 is then flip-chip mounted on the third redistribution layer 500, resulting in the structure shown in fig. 11. The third rewiring layer 500 includes a third wire 510 and a third passivation layer 520, and the third passivation layer 520 should have an opening to expose the third wire 510 so that the second chip 230 can be connected to the third wire 510 through the opening. The third redistribution layer 500 is electrically connected to the first redistribution layer 100, specifically, the third line 510 is connected to the first line 110, so as to transmit signals between the two redistribution layers. In some alternative embodiments, the third redistribution layer 500 may not be disposed, and the second chip 230 and the wire bonding pad 530 may be disposed directly on the first redistribution layer 100. After the second chip 230 and the wire bonding pads 530 are disposed on the side of the first redistribution layer 100 away from the first plastic package body 300, the carrier 020 and the temporary film 022 on the second redistribution layer 400 can be removed.
After the second chip 230 and the wire bonding pads 530 are disposed, dicing may be performed to obtain a single chip package structure 010, as shown in fig. 12.
In this embodiment, the third conductive pillars 240 are disposed on the second chip 230, and the second chip 230 is electrically connected to the third redistribution layer 500 through the third conductive pillars 240, and the fan-out stack packaging method further includes: the second molding compound 310 is fabricated to wrap the third conductive pillars 240, so as to obtain the structure shown in fig. 13. It is understood that the fan-out stack packaging method may further include fabricating the third conductive pillars 240 on the wafer of the second chip 230 to obtain the second chip 230 having the third conductive pillars 240, which is similar to the method of fabricating the second conductive pillars 210 on the first chip 200 and will not be described herein again.
In addition, the fan-out stack packaging method of the embodiment of the application further includes: the second re-wiring layer 400 is electrically connected to the substrate 600 by the first solder balls 430; a lead 700 is provided to electrically connect bond pad 530 to substrate 600. The chip package structure 010 shown in fig. 1 is finally obtained.
In addition, an electronic device is further provided in an embodiment of the present application, including the chip packaging structure 010 provided in the foregoing embodiment, or including the chip packaging structure 010 manufactured by the foregoing fan-out stack packaging method.
In summary, the chip package structure 010 and the package structure manufactured by the fan-out stack package method according to the embodiment of the present application include the first redistribution layer 100, the second redistribution layer 400, the first plastic package body 300, the first chip 200, the second chip 230, the first solder balls 430, and the wire bonding pads 530. The first chip 200 and the first plastic package body 300 are located between the first redistribution layer 100 and the second redistribution layer 400, the first solder balls 430 are located on the second redistribution layer 400, and the second chip 230 is overlappingly disposed on the first redistribution layer 100 at a side away from the first chip 200, and the first solder balls 430 electrically connected to the second redistribution layer 400 and the bonding pads 530 electrically connected to the first redistribution layer 100 can be used as signal connection points. The fan-out stack packaging method can realize the comprehensive packaging of the first chip 200, so that the packaging reliability is improved, and the fan-out stack packaging method has the characteristics of small volume and capability of carrying more signal connection points. The fan-out stack packaging method can effectively reduce the packaging area and further improve the function integration level of a unit area, so that a more fine wiring line width and a high-density packaging structure are obtained, and heterogeneous integration can be achieved by combining a plurality of chips with different functions, so that higher function requirements can be met.
The electronic device provided by the embodiment of the application comprises the chip packaging structure 010, and multifunctional integration and miniaturization are easy to realize.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (14)

1. A fan-out stack packaging method, comprising:
manufacturing a first re-wiring layer on a carrier, and manufacturing a first conductive pillar on the first re-wiring layer;
flip-chip mounting a first chip to the first redistribution layer, wherein a second conductive pillar is pre-arranged on the first chip, and the first chip is electrically connected with the first redistribution layer through the second conductive pillar;
manufacturing a first plastic package body to wrap the first chip, the first conductive column and the second conductive column and expose one end of the first conductive column, which is far away from the carrier;
manufacturing a second redistribution layer on the first plastic package body, and manufacturing a first solder ball on the second redistribution layer, wherein the second redistribution layer is electrically connected with the first redistribution layer through the first conductive pillar;
and separating the carrier from the first rewiring layer, arranging a second chip and a routing pad for externally connecting a lead on one side of the first rewiring layer, which is far away from the first plastic package body, wherein the routing pad and the second chip are electrically connected with the first rewiring layer.
2. The fan-out stack packaging method of claim 1, wherein the step of providing a second chip and wire bond pads for external leads on a side of the first redistribution layer remote from the first molding compound comprises:
a third rewiring layer is arranged on the first rewiring layer and electrically connected with the second rewiring layer, and the routing bonding pad is formed on one side, away from the second rewiring layer, of the third rewiring layer;
and inversely installing the second chip on the third re-wiring layer.
3. The fan-out stack packaging method of claim 2, wherein a third conductive pillar is disposed on the second chip, and the second chip is electrically connected to the third redistribution layer through the third conductive pillar; the fan-out stack packaging method further comprises:
and manufacturing a second plastic package body to wrap the third conductive posts.
4. The fan-out stack packaging method of claim 3, further comprising:
manufacturing the second conductive column on the wafer of the first chip;
and manufacturing the third conductive column on the wafer of the second chip.
5. The fan-out stack packaging method of claim 1, further comprising:
electrically connecting the second re-wiring layer to a substrate through the first solder ball;
and arranging a lead to electrically connect the routing bonding pad with the substrate.
6. The fan-out stack packaging method of any of claims 1-5, wherein the step of exposing an end of the first conductive pillar away from the carrier comprises:
and grinding the first plastic package body to expose one end of the first conductive column far away from the carrier.
7. The fan-out stack packaging method of any of claims 1-5, wherein after the step of separating the carrier from the first re-wiring layer and before the step of disposing a second chip on a side of the first re-wiring layer away from the first molding compound, the fan-out stack packaging method further comprises: attaching the second rewiring layer to the carrier through a temporary film;
after the step of disposing a second chip on the side of the first redistribution layer away from the first plastic package body, the fan-out stack packaging method further includes: and removing the carrier and the temporary film on the second re-wiring layer.
8. The fan-out stack packaging method of any of claims 1-5, wherein the step of flip-chip mounting the first chip to the first re-routing layer comprises flip-chip mounting a plurality of the first chips to the first re-routing layer;
after the step of disposing a second chip on the side of the first redistribution layer away from the first plastic package body, the fan-out stack packaging method further includes: and cutting to form single chip packaging structures.
9. The fan-out stack packaging method of any of claims 1-5, wherein the first conductive pillars, the second conductive pillars are copper pillars.
10. A chip package structure, comprising:
the first redistribution layer and the second redistribution layer are arranged at intervals and connected through a first conductive pillar;
a first chip located between the first redistribution layer and the second redistribution layer, the first chip being flip-mounted to the first redistribution layer by a second conductive pillar;
the first plastic package body wraps the first chip, the first conductive column and the second conductive column;
the second chip is arranged on one side, away from the first plastic package body, of the first rewiring layer and is electrically connected with the first rewiring layer;
the routing bonding pad is used for connecting a lead, is arranged on one side, away from the first plastic package body, of the first redistribution layer and is electrically connected with the first redistribution layer;
and the first solder ball is arranged on the second re-wiring layer.
11. The chip package structure according to claim 10, further comprising:
the second chip is arranged in the third re-wiring layer in a reversed mode, and the routing bonding pad is formed on one side, away from the first re-wiring layer, of the third re-wiring layer and is electrically connected with the third re-wiring layer.
12. The chip package structure according to claim 11, wherein the second chip is electrically connected to the third redistribution layer through a third conductive pillar; the chip packaging structure further comprises a second plastic package body, and the third conductive column is wrapped by the second plastic package body.
13. The chip package structure of claim 10, further comprising a substrate electrically connected to the second redistribution layer via the first solder balls and leads electrically connecting the wire bonding pads to the substrate.
14. An electronic device comprising the chip packaging structure according to any one of claims 10 to 13.
CN202210344643.2A 2022-03-31 2022-03-31 Fan-out stack packaging method, chip packaging structure and electronic equipment Pending CN114709142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210344643.2A CN114709142A (en) 2022-03-31 2022-03-31 Fan-out stack packaging method, chip packaging structure and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210344643.2A CN114709142A (en) 2022-03-31 2022-03-31 Fan-out stack packaging method, chip packaging structure and electronic equipment

Publications (1)

Publication Number Publication Date
CN114709142A true CN114709142A (en) 2022-07-05

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
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