CN114709141A - Semiconductor package and manufacturing method thereof - Google Patents

Semiconductor package and manufacturing method thereof Download PDF

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Publication number
CN114709141A
CN114709141A CN202210345166.1A CN202210345166A CN114709141A CN 114709141 A CN114709141 A CN 114709141A CN 202210345166 A CN202210345166 A CN 202210345166A CN 114709141 A CN114709141 A CN 114709141A
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China
Prior art keywords
heat dissipation
chip
metal
heat
columns
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Withdrawn
Application number
CN202210345166.1A
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Chinese (zh)
Inventor
刘梦雪
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Jinan Xiaozhu Information Technology Co ltd
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Jinan Xiaozhu Information Technology Co ltd
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Priority to CN202210345166.1A priority Critical patent/CN114709141A/en
Publication of CN114709141A publication Critical patent/CN114709141A/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16—ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16L—PIPES; JOINTS OR FITTINGS FOR PIPES; SUPPORTS FOR PIPES, CABLES OR PROTECTIVE TUBING; MEANS FOR THERMAL INSULATION IN GENERAL
    • F16L59/00—Thermal insulation in general
    • F16L59/02—Shape or form of insulating materials, with or without coverings integral with the insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3733—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof

Abstract

The invention provides a semiconductor package and a manufacturing method thereof, in the manufacturing process of the semiconductor package, a heat dissipation plate is arranged to comprise a first heat dissipation area, a second heat dissipation area, a third heat dissipation area and a first heat insulation area, the first heat dissipation area comprises a plurality of first metal columns, the second heat dissipation area comprises a plurality of second metal columns, the third heat dissipation area comprises a plurality of third metal columns, the first heat insulation area comprises a plurality of resin columns, the plurality of first, second and third metal columns and the plurality of resin columns are fixedly connected together by a plurality of connecting wires, each metal column can freely move up and down due to the existence of the connecting wires, even if the semiconductor package is warped due to different coefficients of thermal expansion, because each metal column can freely move up and down, the heat dissipation plate can be tightly combined with each chip, and thus, the heat dissipation performance of the semiconductor package can be prevented from being lowered.

Description

Semiconductor package and manufacturing method thereof
Technical Field
The present invention relates to the field of semiconductor packaging technology, and more particularly, to a semiconductor package and a method for manufacturing the same.
Background
In a conventional semiconductor package, a semiconductor chip is usually flip-chip mounted on a circuit carrier substrate, and a heat dissipation substrate is further mounted on the circuit carrier substrate, such that the heat dissipation substrate covers the semiconductor chip, and a thermal interface material layer is disposed between the semiconductor chip and the heat dissipation substrate. In the actual use process of the semiconductor package, because the thermal expansion coefficients of the heat dissipation substrate, the thermal interface material layer and the semiconductor chip in the semiconductor package are different, the difference in thermal expansion coefficient among the parts can cause the warpage of the semiconductor package, and further cause the heat dissipation performance of the semiconductor package to be reduced.
Disclosure of Invention
It is an object of the present invention to overcome the above-mentioned deficiencies of the prior art and to provide a semiconductor package and a method for manufacturing the same.
In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor package, comprising the steps of:
providing a circuit packaging substrate, arranging a first high heat dissipation chip, a second high heat dissipation chip, a third high heat dissipation chip and a first low heat dissipation chip on the circuit packaging substrate, wherein the heat dissipation capacity of the first high heat dissipation chip is greater than that of the second high heat dissipation chip, and the heat dissipation capacity of the second high heat dissipation chip is greater than that of the third high heat dissipation chip.
And arranging a heat insulation block at the side edge of the first low heat dissipation chip.
The heating panel comprises a first heat dissipation area, a second heat dissipation area, a third heat dissipation area and a first heat insulation area, the first heat dissipation area comprises a plurality of first metal columns, the second heat dissipation area comprises a plurality of second metal columns, the third heat dissipation area comprises a plurality of third metal columns, the first heat insulation area comprises a plurality of resin columns, and a plurality of connecting wires are utilized to form a plurality of first, second and third metal columns which are fixedly connected together.
And arranging the heat dissipation plate on the first, second and third high heat dissipation chips and the first low heat dissipation chip, so that the heat insulation block supports the heat dissipation plate.
And an encapsulation layer is arranged between the circuit packaging substrate and the heat dissipation plate.
Preferably, the plurality of connecting wires comprise a plurality of transversely-arranged connecting wires and a plurality of longitudinally-arranged connecting wires, each transversely-arranged connecting wire is connected with the first metal column and the second metal column in the same row or is connected with the third metal column and the resin columns in the same row, and each longitudinally-arranged connecting wire is connected with the first metal column and the third metal column in the same column or is connected with the second metal columns and the resin columns in the same column.
Preferably, the first metal pillar has a thermal conductivity greater than that of the second metal pillar, and the second metal pillar has a thermal conductivity greater than that of the third metal pillar.
Preferably, the first, second and third high thermal dissipation chips are respectively provided with a first, second and third thermal conductive adhesive layer, and the first, second and third thermal dissipation areas are respectively thermally connected with the first, second and third high thermal dissipation chips by using the first, second and third thermal conductive adhesive layers.
Preferably, after the encapsulation layer is provided between the circuit package substrate and the heat dissipation plate, a plurality of electrical lead-out structures are provided on the bottom surface of the circuit package substrate.
The present invention also provides a semiconductor package, including: the circuit packaging substrate is provided with a first high heat dissipation chip, a second high heat dissipation chip, a third high heat dissipation chip and a first low heat dissipation chip, wherein the heat dissipation capacity of the first high heat dissipation chip is greater than that of the second high heat dissipation chip, and the heat dissipation capacity of the second high heat dissipation chip is greater than that of the third high heat dissipation chip.
The heating panel, the heating panel sets up first, second, third high radiating chip and on the first low radiating chip, the heating panel includes first radiating area, second radiating area, third radiating area and first heat-proof zone, first radiating area includes a plurality of first metal posts, and the second radiating area includes a plurality of second metal posts, the third radiating area includes a plurality of third metal posts, first heat-proof zone includes a plurality of resin posts, utilizes many connecting wires will be a plurality of first, second, third metal posts and a plurality of resin post fixed connection is in the same place.
An encapsulation layer is disposed between the circuit package substrate and the heat dissipation plate.
Preferably, the first, second and third high heat dissipation chips are power devices, and the first low heat dissipation chip is a control device.
Preferably, a plurality of heat insulating blocks are provided at both side edges of the first low heat dissipating chip, respectively, and the heat dissipating plate is supported by the plurality of heat insulating blocks.
Preferably, a plurality of electrical lead-out structures are provided on the bottom surface of the circuit package substrate.
Compared with the prior art, the invention has the following advantages:
in the manufacturing process of the semiconductor package of the present invention, by providing the heat dissipation plate including the first heat dissipation region, the second heat dissipation region, the third heat dissipation region and the first heat insulating region, the first heat dissipation area comprises a plurality of first metal columns, the second heat dissipation area comprises a plurality of second metal columns, the third heat dissipation area comprises a plurality of third metal columns, the first heat insulation area comprises a plurality of resin columns, the first, second and third metal columns and the resin columns are fixedly connected together by a plurality of connecting lines, each metal column can freely move up and down due to the existence of the connecting lines, even if the semiconductor package is warped due to the difference in thermal expansion coefficient, since each metal pillar can freely move up and down, thereby ensuring the close connection between the heat sink and each chip and preventing the heat dissipation performance of the semiconductor package from being reduced.
Because the heat dissipation plate comprises the first heat dissipation area, the second heat dissipation area and the third heat dissipation area, the heat conductivity coefficient of the first metal column is larger than that of the second metal column, the heat conductivity coefficient of the second metal column is larger than that of the third metal column, the structure can ensure that each heat dissipation area of the heat dissipation plate respectively corresponds to each high heat dissipation chip with different heat dissipation capacity, thereby facilitating each high heat dissipation chip, meanwhile, the first heat insulation area is arranged in the area of the heat dissipation plate corresponding to the first low heat dissipation chip, thereby facilitating the heat generated by other high heat dissipation chips not to be transferred to the first low heat dissipation chip, further avoiding other high heat dissipation chips from influencing the normal work of the first low heat dissipation chip, meanwhile, because the first heat insulation area is arranged on the first low heat dissipation chip, further when a package layer is formed by subsequent injection molding, the influence on the stability of the electrical connection of the first low heat dissipation chip caused by overlarge impact force of the resin material is avoided.
Drawings
Fig. 1-4 are schematic structural views illustrating a manufacturing process of a semiconductor package according to an embodiment of the present invention.
Detailed Description
The invention provides a manufacturing method of a semiconductor package, which comprises the following steps:
providing a circuit packaging substrate, arranging a first high heat dissipation chip, a second high heat dissipation chip, a third high heat dissipation chip and a first low heat dissipation chip on the circuit packaging substrate, wherein the heat dissipation capacity of the first high heat dissipation chip is greater than that of the second high heat dissipation chip, and the heat dissipation capacity of the second high heat dissipation chip is greater than that of the third high heat dissipation chip.
And arranging a heat insulation block at the side edge of the first low heat dissipation chip.
The heating panel comprises a first heat dissipation area, a second heat dissipation area, a third heat dissipation area and a first heat insulation area, the first heat dissipation area comprises a plurality of first metal columns, the second heat dissipation area comprises a plurality of second metal columns, the third heat dissipation area comprises a plurality of third metal columns, the first heat insulation area comprises a plurality of resin columns, and a plurality of connecting wires are utilized to form a plurality of first, second and third metal columns which are fixedly connected together.
And arranging the heat dissipation plate on the first, second and third high heat dissipation chips and the first low heat dissipation chip, so that the heat insulation block supports the heat dissipation plate.
And an encapsulation layer is arranged between the circuit packaging substrate and the heat dissipation plate.
In a specific embodiment, the connecting lines include a plurality of transversely-arranged connecting lines and a plurality of longitudinally-arranged connecting lines, each transversely-arranged connecting line is connected with the first metal column, the second metal column or the third metal column and the resin columns in the same row, and each longitudinally-arranged connecting line is connected with the first metal column, the third metal column or the second metal column and the resin columns in the same column.
In a specific embodiment, the thermal conductivity of the first metal pillar is greater than the thermal conductivity of the second metal pillar, and the thermal conductivity of the second metal pillar is greater than the thermal conductivity of the third metal pillar.
In a specific embodiment, a first thermal conductive adhesive layer, a second thermal conductive adhesive layer, and a third thermal conductive adhesive layer are respectively disposed on the first high thermal dissipation chip, the second high thermal dissipation chip, and the third thermal dissipation chip, and the first thermal conductive adhesive layer, the second thermal conductive adhesive layer, and the third thermal conductive adhesive layer are respectively used to thermally connect the first thermal dissipation area, the second thermal dissipation area, and the third thermal dissipation area to the first high thermal dissipation chip, the second thermal dissipation area, and the third thermal dissipation area.
In a specific embodiment, after the encapsulation layer is disposed between the circuit package substrate and the heat sink, a plurality of electrical lead-out structures are disposed on a bottom surface of the circuit package substrate.
The present invention also provides a semiconductor package, including: the circuit packaging substrate is provided with a first high heat dissipation chip, a second high heat dissipation chip, a third high heat dissipation chip and a first low heat dissipation chip, wherein the heat dissipation capacity of the first high heat dissipation chip is greater than that of the second high heat dissipation chip, and the heat dissipation capacity of the second high heat dissipation chip is greater than that of the third high heat dissipation chip.
The heating panel, the heating panel sets up first, second, third high heat dissipation chip and on the first low heat dissipation chip, the heating panel includes first radiating area, second radiating area, third radiating area and first heat-insulating zone, first radiating area includes a plurality of first metal posts, and the second radiating area includes a plurality of second metal posts, the third radiating area includes a plurality of third metal posts, first heat-insulating zone includes a plurality of resin posts, utilizes many connecting wires will be a plurality of first, second, third metal posts and a plurality of resin post fixed connection is in the same place.
An encapsulation layer is disposed between the circuit package substrate and the heat dissipation plate.
In a specific embodiment, the first, second and third high heat dissipation chips are power devices, and the first low heat dissipation chip is a control device.
In a specific embodiment, a plurality of heat insulation blocks are respectively disposed on two side edges of the first low heat dissipation chip, and the heat dissipation plate is supported by the plurality of heat insulation blocks.
In a specific embodiment, a plurality of electrical lead-out structures are disposed on a bottom surface of the package substrate.
The following is a detailed description of the manufacturing process of the semiconductor package in conjunction with the schematic structural diagrams of fig. 1-4.
Referring to fig. 1, a circuit package substrate 100 is provided, a first high thermal dissipation chip 201, a second high thermal dissipation chip 202, a third high thermal dissipation chip 203 and a first low thermal dissipation chip 204 are disposed on the circuit package substrate 100, a thermal dissipation amount of the first high thermal dissipation chip 201 is greater than a thermal dissipation amount of the second high thermal dissipation chip 202, and a thermal dissipation amount of the second high thermal dissipation chip 202 is greater than a thermal dissipation amount of the third high thermal dissipation chip 203.
In a specific embodiment, the circuit package substrate 100 may be one of a printed circuit board, a ceramic-based circuit substrate and a metal-based circuit substrate, wherein the ceramic-based circuit substrate includes a ceramic base and metal wiring layers disposed on upper and lower surfaces of the ceramic base, and a conductive through hole is disposed in the ceramic base, the metal wiring layers disposed on the upper and lower surfaces are electrically connected through the conductive through hole, and the metal-based circuit substrate includes a metal base, an upper insulating layer and a lower insulating layer disposed on the upper and lower surfaces of the metal base, a metal wiring layer disposed above the upper insulating layer, and a metal wiring layer disposed below the lower insulating layer.
In a specific embodiment, the first, second and third high heat dissipation chips 201-203 are all power devices, and the first low heat dissipation chip 204 is a control device, and more specifically, the first, second and third high heat dissipation chips 201-203 are power devices with different heat dissipation amounts, and the heat dissipation amounts of the first, second and third high heat dissipation chips 201-203 are larger than those of the control device. The heat dissipation amount of the control device serving as the first low heat dissipation chip 204 is relatively small, the ideal operating temperature of the control device is relatively low, and the heat dissipation amount of the power device is large, so that the operating temperature of the control device is easily influenced, and the control device is easily damaged.
In a specific embodiment, a heat insulation block 300 is disposed at a side of the first low-heat-dissipation chip 204. In a more specific embodiment, a plurality of heat insulation blocks 300 are respectively disposed on two sides of the first low-dissipation chip 204, where the heat insulation blocks are made of one of silicon dioxide, epoxy resin, silica gel, PMMA, PC, and PS, and more specifically, the two sides are a side of the first low-dissipation chip 204 close to the second high-dissipation chip 202 and a side of the first low-dissipation chip close to the third high-dissipation chip 203.
Referring to fig. 2, a heat dissipation plate 400 is provided, where the heat dissipation plate 400 includes a first heat dissipation area 401, a second heat dissipation area 402, a third heat dissipation area 403, and a first heat insulation area 404, the first heat dissipation area 401 includes a plurality of first metal posts 4011, the second heat dissipation area 402 includes a plurality of second metal posts 4021, the third heat dissipation area 403 includes a plurality of third metal posts 4031, the first heat insulation area 404 includes a plurality of resin posts 4041, and the plurality of first, second, third metal posts 4011 and 4031 and the plurality of resin posts 4041 are fixedly connected together by a plurality of connection lines 405.
In a specific embodiment, the connecting lines 405 include a plurality of connecting lines 405 arranged transversely and a plurality of connecting lines 405 arranged longitudinally, each connecting line 405 arranged transversely connects a plurality of the first and second metal posts 4011 and 4021 in the same row or connects a plurality of the third metal posts 4031 and a plurality of the resin posts 4041 in the same row, and each connecting line 405 arranged longitudinally connects a plurality of the first and third metal posts 4011 and 4031 in the same column or connects a plurality of the second metal posts 4021 and a plurality of the resin posts 4041 in the same column. Because the columns are fixedly connected through the connecting lines, each column can freely move up and down, and then the heat dissipation plate 400 is arranged on the circuit packaging substrate 100 subsequently, even if the semiconductor package is warped due to different thermal expansion coefficients, the heat dissipation plate can be ensured to be tightly combined with each chip due to the fact that each column can freely move up and down, and further the heat dissipation performance of the semiconductor package can be prevented from being reduced.
In a specific embodiment, the thermal conductivity of the first metal pillar 4011 is greater than the thermal conductivity of the second metal pillar 4021, and the thermal conductivity of the second metal pillar 4021 is greater than the thermal conductivity of the third metal pillar 4031. More specifically, first metal post 4011 is silver post, second metal post 4021 is the copper post, third metal post 4031 is the aluminium post, resin post 4041's material is one of epoxy, silica gel, PMMA, ABS, PC.
In a specific embodiment, the top surfaces of the first, second, and third metal pillars and the resin pillar are one of square, rectangular, or circular.
Referring to fig. 3, the fig. 3 is a schematic cross-sectional view along a third high thermal dissipating chip 203 and a first low thermal dissipating chip 204, the thermal plate 400 is disposed on the first, second, third high thermal dissipating chips 201 and 203 and the first low thermal dissipating chip 204, such that the thermal insulation block 300 supports the thermal plate.
In a specific embodiment, the heat dissipation plate 400 is supported by the heat insulation block 300, so that the heat dissipation plate can be effectively supported, and the risk of breaking the connection lines is reduced.
In a specific embodiment, a first, a second, and a third thermal conductive adhesive layers are respectively disposed on the first, the second, and the third high thermal dissipating chips 201 and 203, and then the first, the second, and the third thermal dissipating regions are respectively thermally connected to the first, the second, and the third high thermal dissipating chips by the first, the second, and the third thermal conductive adhesive layers, and meanwhile, an adhesive layer is disposed on the first low thermal dissipating chip 204, and then the resin pillar 4041 of the first thermal insulating region 404 is bonded by the adhesive layer.
Referring to fig. 4, an encapsulation layer 500 is disposed between the circuit package substrate 100 and the heat dissipation plate 400, where the encapsulation layer 500 may be epoxy resin, and in a specific embodiment, after the encapsulation layer 500 is disposed between the circuit package substrate 100 and the heat dissipation plate 400, a plurality of electrical lead-out structures 600 are disposed on the bottom surface of the circuit package substrate 100.
Referring to fig. 1-4, the present invention further provides a semiconductor package, including: the circuit packaging substrate 100 is provided with a first high heat dissipation chip 201, a second high heat dissipation chip 202, a third high heat dissipation chip 203 and a first low heat dissipation chip 204, wherein the heat dissipation capacity of the first high heat dissipation chip 201 is greater than that of the second high heat dissipation chip 202, and the heat dissipation capacity of the second high heat dissipation chip 202 is greater than that of the third high heat dissipation chip 203.
The first, second, and third high heat dissipation chips 201 and 203 are power devices, and the first low heat dissipation chip 204 is a control device.
The two sides of the first low heat dissipating chip 204 are respectively provided with a plurality of heat insulating blocks 300, the plurality of heat insulating blocks 300 support a heat dissipating plate 400, the heat dissipating plate 400 is arranged on the first, second and third high heat dissipating chips 201 and 203 and the first low heat dissipating chip 204, the heat dissipating plate 400 comprises a first heat dissipating region 401, a second heat dissipating region 402, a third heat dissipating region 403 and a first heat insulating region 404, the first heat dissipating region 401 comprises a plurality of first metal posts 4011, the second heat dissipating region 402 comprises a plurality of second metal posts 4021, the third heat dissipating region 403 comprises a plurality of third metal posts 4031, the first heat insulating region 404 comprises a plurality of resin posts 4041, and the plurality of first, second and third metal posts and the plurality of resin posts are fixedly connected together by using a plurality of connecting wires 405.
An encapsulation layer 500 is provided between the circuit package substrate 100 and the heat sink 400.
A plurality of electrical lead structures 600 are provided on the bottom surface of the circuit package substrate 100.
Compared with the prior art, the invention has the following advantages:
in the manufacturing process of the semiconductor package of the present invention, by providing the heat dissipation plate including the first heat dissipation region, the second heat dissipation region, the third heat dissipation region and the first heat insulating region, the first heat dissipation area comprises a plurality of first metal columns, the second heat dissipation area comprises a plurality of second metal columns, the third heat dissipation area comprises a plurality of third metal columns, the first heat insulation area comprises a plurality of resin columns, the first, second and third metal columns and the resin columns are fixedly connected together by a plurality of connecting lines, each metal column can freely move up and down due to the existence of the connecting lines, even if the semiconductor package is warped due to the difference in thermal expansion coefficient, since each metal pillar can freely move up and down, thereby ensuring the close connection between the heat sink and each chip and preventing the heat dissipation performance of the semiconductor package from being reduced.
Because the heat dissipation plate comprises the first heat dissipation area, the second heat dissipation area and the third heat dissipation area, the heat conductivity coefficient of the first metal column is larger than that of the second metal column, the heat conductivity coefficient of the second metal column is larger than that of the third metal column, the structure can ensure that each heat dissipation area of the heat dissipation plate respectively corresponds to each high heat dissipation chip with different heat dissipation capacity, thereby facilitating each high heat dissipation chip, meanwhile, the first heat insulation area is arranged in the area of the heat dissipation plate corresponding to the first low heat dissipation chip, thereby facilitating the heat generated by other high heat dissipation chips not to be transferred to the first low heat dissipation chip, further avoiding other high heat dissipation chips from influencing the normal work of the first low heat dissipation chip, meanwhile, because the first heat insulation area is arranged on the first low heat dissipation chip, further when a package layer is formed by subsequent injection molding, the influence on the stability of the electrical connection of the first low heat dissipation chip caused by overlarge impact force of the resin material is avoided.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (9)

1. A method of manufacturing a semiconductor package, characterized by: the method comprises the following steps:
providing a circuit packaging substrate, and arranging a first high heat dissipation chip, a second high heat dissipation chip, a third high heat dissipation chip and a first low heat dissipation chip on the circuit packaging substrate, wherein the heat dissipation capacity of the first high heat dissipation chip is greater than that of the second high heat dissipation chip, and the heat dissipation capacity of the second high heat dissipation chip is greater than that of the third high heat dissipation chip;
arranging a heat insulation block on the side edge of the first low heat dissipation chip;
providing a heat dissipation plate, wherein the heat dissipation plate comprises a first heat dissipation area, a second heat dissipation area, a third heat dissipation area and a first heat insulation area, the first heat dissipation area comprises a plurality of first metal columns, the second heat dissipation area comprises a plurality of second metal columns, the third heat dissipation area comprises a plurality of third metal columns, the first heat insulation area comprises a plurality of resin columns, and the first metal columns, the second metal columns, the third metal columns and the resin columns are fixedly connected together by a plurality of connecting lines;
disposing the heat spreader plate on the first, second, third high thermal dissipating chips and the first low thermal dissipating chip such that the heat insulating block supports the heat spreader plate;
and an encapsulation layer is arranged between the circuit packaging substrate and the heat dissipation plate.
2. The method of manufacturing a semiconductor package according to claim 1, wherein: many connecting wires include many connecting wires of transversely arranging and many connecting wires of vertically arranging, and each connecting wire of transversely arranging connects a plurality ofly on same line first, second metal column or connect a plurality ofly on same line third metal column and a plurality of resin column, a plurality of first, third metal column of a plurality of on same column or connect a plurality of second metal column and a plurality of on the same column of connecting line of vertically arranging.
3. The method of manufacturing a semiconductor package according to claim 1, wherein: the heat conductivity coefficient of the first metal column is larger than that of the second metal column, and the heat conductivity coefficient of the second metal column is larger than that of the third metal column.
4. The method of manufacturing a semiconductor package according to claim 1, wherein: and the first, second and third heat-conducting adhesive layers are respectively arranged on the first, second and third high-heat-dissipation chips, and the first, second and third heat-dissipation areas are respectively in thermal connection with the first, second and third high-heat-dissipation chips by utilizing the first, second and third heat-conducting adhesive layers.
5. The method of manufacturing a semiconductor package according to claim 1, wherein: after the encapsulation layer is disposed between the circuit package substrate and the heat dissipation plate, a plurality of electrical lead-out structures are disposed on a bottom surface of the circuit package substrate.
6. A semiconductor package, characterized by: the method comprises the following steps: the circuit packaging substrate is provided with a first high heat dissipation chip, a second high heat dissipation chip, a third high heat dissipation chip and a first low heat dissipation chip, wherein the heat dissipation capacity of the first high heat dissipation chip is greater than that of the second high heat dissipation chip, and the heat dissipation capacity of the second high heat dissipation chip is greater than that of the third high heat dissipation chip;
the heat dissipation plate is arranged on the first high heat dissipation chip, the second high heat dissipation chip, the third high heat dissipation chip and the first low heat dissipation chip and comprises a first heat dissipation area, a second heat dissipation area, a third heat dissipation area and a first heat insulation area, the first heat dissipation area comprises a plurality of first metal columns, the second heat dissipation area comprises a plurality of second metal columns, the third heat dissipation area comprises a plurality of third metal columns, the first heat insulation area comprises a plurality of resin columns, and the first metal columns, the second metal columns, the third metal columns and the resin columns are fixedly connected together through a plurality of connecting lines;
an encapsulation layer is disposed between the circuit package substrate and the heat dissipation plate.
7. The semiconductor package of claim 6, wherein: the first, second and third high heat dissipation chips are power devices, and the first low heat dissipation chip is a control device.
8. The semiconductor package of claim 6, wherein: and a plurality of heat insulation blocks are respectively arranged on two side edges of the first low heat dissipation chip and support the heat dissipation plate.
9. The semiconductor package of claim 6, wherein: and a plurality of electric leading-out structures are arranged on the bottom surface of the circuit packaging substrate.
CN202210345166.1A 2022-04-02 2022-04-02 Semiconductor package and manufacturing method thereof Withdrawn CN114709141A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210345166.1A CN114709141A (en) 2022-04-02 2022-04-02 Semiconductor package and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210345166.1A CN114709141A (en) 2022-04-02 2022-04-02 Semiconductor package and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN114709141A true CN114709141A (en) 2022-07-05

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210345166.1A Withdrawn CN114709141A (en) 2022-04-02 2022-04-02 Semiconductor package and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN114709141A (en)

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