CN114706717A

CN114706717A - Error information recording method and apparatus, electronic device, and storage medium

Info

Publication number: CN114706717A
Application number: CN202210242153.1A
Authority: CN
Inventors: 庞贤明; 张华赞
Original assignee: Zhuhai Xinye Measurement And Control Co ltd
Current assignee: Zhuhai Xinye Measurement And Control Co ltd
Priority date: 2022-03-11
Filing date: 2022-03-11
Publication date: 2022-07-05

Abstract

The embodiment of the invention provides an error information recording method and device, electronic equipment and a storage medium, and relates to the technical field of chip automation test equipment. The method comprises the steps that a plurality of digital board cards, a main control card and a memory are created, test vectors are operated, channel data are generated, the main control card controls the digital board cards to mark error data and corresponding station information according to preset rules to form first error information, the main control card controls the digital board cards to convert the first error information into second error information through a data transmission mode, the second error information sent by the digital board cards is received, third error information is analyzed from the second error information, fourth error information is screened from the third error information according to preset gating conditions, and the fourth error information is stored in the memory. The method can realize synchronous recording of error information for a plurality of test stations.

Description

Error information recording method and apparatus, electronic device, and storage medium

Technical Field

The invention relates to the technical field of chip automatic test equipment, in particular to an error information recording method and device, electronic equipment and a storage medium.

Background

In the chip testing technology, when a test vector of a chip is operated, an automatic testing device generates a corresponding clock cycle according to the requirement of the chip, provides input excitation for the chip in each clock cycle, and simultaneously compares output feedback levels to verify the correctness of the chip.

Disclosure of Invention

The present invention is directed to solving, at least in part, one of the technical problems in the related art. Therefore, the invention provides an error information recording method and device, electronic equipment and a storage medium, which can simultaneously record error information aiming at a plurality of different test stations.

In order to achieve the above object, a first aspect of the embodiments of the present invention provides an error information recording method applied to a test device, where the test device includes a plurality of digital boards, a master control card, and a memory, each of the digital boards includes a plurality of digital channels, the digital boards are respectively connected to the master control card, and the memory is connected to the master control card, and the method includes:

creating and operating a test vector to generate channel data;

controlling the digital board card to mark error data and corresponding station information in the channel data according to a preset rule to form first error information;

controlling the digital board card to convert the first error information into second error information in a data transmission mode;

receiving the second error information sent by the digital board card, and analyzing third error information from the second error information;

screening fourth error information from the third error information according to a preset gating condition;

and storing the fourth error information into the memory.

In some embodiments of the present invention, the controlling the digital board card to mark error data and corresponding station information in the channel data according to a preset rule to form first error information includes:

identifying error data in the channel data according to a truth table;

marking the error data;

and forming first error information according to the channel data with the error data marks and the corresponding station information.

In some embodiments of the present invention, the controlling the digital board card to convert the first error information into the second error information through a data transmission method includes:

sending the first error information to an encoder in a wired communication mode;

the encoder converts the first error information into encoded data;

adjusting the coded data through an equalizer to form the second error information;

and sending the second error information to the master control card through a driver.

In some embodiments of the present invention, receiving the second error information sent by the digital board, and analyzing third error information from the second error information, includes:

setting a receiving number counter;

receiving the second error information and calculating the number of rows;

parsing the second error information into parallel data through a decoder;

and obtaining the third error information according to the parallel data and the corresponding line number.

In some embodiments of the present invention, the screening out fourth error information from the third error information according to a preset gating condition includes:

screening the third error information through a recording mode gating condition to form recording mode error information;

and screening the recording mode error information through station information gating conditions to form the fourth error information.

In some embodiments of the present invention, the recording mode gating condition includes starting the recording mode according to the number of lines, recording the error information only recording mode, and starting the recording mode from the first line error information.

In some embodiments of the present invention, the screening the recording mode error information through a station information gating condition to form the fourth error information includes:

selecting a corresponding digital channel according to the station information;

taking non-operation back phases of failure flag bits of all digital channel stations in the station information to form station information gating conditions;

and screening the error information of the recording mode meeting the station information gating condition into fourth error information.

In order to achieve the above object, a second aspect of the embodiments of the present invention provides an error information recording apparatus, where the test apparatus includes a plurality of digital boards, a master control card, and a memory, each of the digital boards includes a plurality of digital channels, the digital boards are respectively connected to the master control card, and the memory is connected to the master control card, and the error information recording apparatus further includes:

the test vector creating and operating module is used for creating and operating a test vector to generate channel data;

the first error information generation module is used for controlling the digital board card to mark error data and corresponding station information in the channel data according to a preset rule to form first error information;

the second error information conversion module is used for controlling the digital board card to convert the first error information into second error information in a data transmission mode;

the third error information analysis module is used for receiving the second error information sent by the digital board card and analyzing third error information from the second error information;

the fourth error information screening module is used for screening fourth error information from the third error information according to a preset gating condition;

and the memory module is used for storing the fourth error information into the memory.

In order to achieve the above object, a third aspect of an embodiment of the present invention provides an electronic device, including:

at least one memory;

at least one processor;

at least one program;

the programs are stored in a memory, and a processor executes the at least one program to implement:

the error information recording method according to the first aspect described above.

To achieve the above object, a fourth aspect of the present invention proposes a storage medium which is a computer-readable storage medium storing computer-executable instructions for causing a computer to execute the error information recording method according to the first aspect.

The error information recording method and device, the electronic equipment and the storage medium provided by the embodiment of the invention are applied to a testing device, the testing device comprises a plurality of digital board cards, a main control card and a memory, one digital board card comprises a plurality of digital channels, the digital board cards are respectively connected with the main control card, the memory is connected with the main control card, a testing vector is firstly created and operated to generate channel data, the digital board card is controlled to mark error data and corresponding station information in the channel data according to a preset rule to form first error information, the digital board card is controlled to convert the first error information into second error information in a data transmission mode, the second error information sent by the digital board card is received, and third error information is analyzed from the second error information, and screening out fourth error information from the third error information according to a preset gating condition, and storing the fourth error information into the memory. According to the method and the device, error information can be recorded for a plurality of test stations while the test vectors are operated at a high speed.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.

FIG. 1 is a hardware block diagram of an error information recording method according to an embodiment of the present invention;

FIG. 2 is a flowchart of an error information recording method according to an embodiment of the present invention;

FIG. 3 is a flowchart of an error information recording method provided by one embodiment of step S120 in FIG. 2;

FIG. 4 is a flowchart of an error information recording method provided by one embodiment of step S130 in FIG. 2;

FIG. 5 is a flowchart of an error information recording method provided by one embodiment of step S140 in FIG. 2;

FIG. 6 is a flowchart of an error information recording method provided by one embodiment of step S150 in FIG. 2;

FIG. 7 is a diagram illustrating a preset gating condition of an error information recording method according to an embodiment of the present invention;

fig. 8 is a schematic diagram illustrating a line condition of an error information recording method according to an embodiment of the present invention;

FIG. 9 is a schematic diagram illustrating a workstation information gating condition of an error information recording method according to an embodiment of the present invention;

FIG. 10 is a flowchart of an error information recording method provided by one embodiment of step S520 in FIG. 6 according to the present invention;

FIG. 11 is a diagram illustrating an error message record of an error message recording method according to an embodiment of the present invention;

fig. 12 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.

In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number. If the description to the first and second is only for the purpose of distinguishing technical features, it is not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated, nor is it necessary to describe a particular order or sequence.

In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.

The embodiment of the invention provides an error information recording method and device, electronic equipment and a storage medium, which are applied to a testing device.A hardware frame comprises a plurality of digital board cards, a main control card and a memory, wherein one digital board card comprises a plurality of digital channels, the digital board cards are respectively connected with the main control card, the memory is connected with the main control card, a test vector is firstly created and operated to generate channel data, the digital board card is controlled to mark error data and corresponding station information in the channel data according to a preset rule to form first error information, the digital board card is controlled to convert the first error information into second error information in a data transmission mode, the second error information sent by the digital board card is received, third error information is analyzed from the second error information, fourth error information is screened from the third error information according to a preset gating condition, and storing the fourth error information into the memory. The prior art can not record error information simultaneously for a plurality of different test stations distributed on different test board cards, and the error information can be synchronously recorded for the plurality of test stations while the test vectors are operated at a high speed.

The embodiments of the present invention will be further explained with reference to the drawings.

As shown in fig. 1, fig. 1 is a hardware framework diagram of an error information recording method according to an embodiment of the present invention. In the example of fig. 1, the hardware framework includes a master control card 101, a digital board 102, a digital channel 103, and a memory 104.

Wherein the testing device comprises a plurality of digital boards 102, in some embodiments, one testing device comprises 8 digital boards 102, one digital board 102 comprises a plurality of digital channels 103, in some embodiments, a digital board 102 has 32 digital channels 103, and in some embodiments, 256 digital channels are arranged in the testing device, 8 digital board cards are arranged, the digital board cards send the collected first error information to the master control card, the master control card is connected with the memory, in some embodiments, to verify and analyze the function and performance of the chip, the testing device needs to test the test vector when the test vector has an error, the method comprises the steps that 1024 first error information including error line numbers, chip pin positions, high and low levels and the like are automatically recorded in an internal cache area of a digital board card, and a computer terminal reads out data of the internal cache area and displays the data after conversion, so that a test engineer and a chip design engineer can analyze and locate reasons.

Fig. 2 is an alternative flowchart of an error information recording method according to an embodiment of the present invention, and the method in fig. 2 may include, but is not limited to, steps S110 to S160.

Step S110, creating and operating a test vector to generate channel data;

step S120, controlling the digital board card to mark error data and corresponding station information in the channel data according to a preset rule to form first error information;

step S130, controlling the digital board card to convert the first error information into second error information in a data transmission mode;

step S140, receiving second error information sent by the digital board card, and analyzing third error information from the second error information;

s150, screening fourth error information from the third error information according to a preset gating condition;

in step S160, the fourth error message is stored in the memory.

In step S110 of some embodiments, a test vector is created and run, generating channel data; the master control card creates and runs test vectors, which may be up to 1600 ten thousand rows in some embodiments, generating channel data. In step S120 of some embodiments, the digital board card is controlled to mark error data and corresponding station information in the channel data according to a preset rule to form first error information; when the testing device performs multi-station simultaneous testing, each digital channel may be allocated to any station according to the design requirement of the chip testing board, so as to identify the current channel. In the running process of the test vector, the main control card controls the digital board card to mark error data generated in the test process according to a preset rule, station information corresponding to the error data and form first error information according to channel data with the error data mark and the corresponding station information. In some embodiments, a single enable bit is set in the master control card for each digital channel, and recording is stopped after the channel data recorded by the workstation corresponding to the channel reaches 1024. In some embodiments, channels of the same digital board are allocated to different stations, each station simultaneously corresponds to digital channels on different digital boards, and when a single station records 1024 rows of channel data, all digital channels of the station are notified to stop recording channel data so as not to cover previous useful information. But other stations that are less than 1024 channels will continue to record. In step S130 of some embodiments, the digital board card is controlled to convert the first error information into the second error information in a data transmission manner; the main control card controls the digital board card to convert the parallel data of the first error information into coded data through the coder in a data transmission mode, and the coded data is converted into second error information through the equalizer and is sent to the main control card. In step S140 of some embodiments, second error information sent by the digital board is received, and third error information is analyzed from the second error information; and the master control card receives the second error information sent by the digital board card, and analyzes third error information from the second error information through a decoder. In step S150 of some embodiments, a fourth error message is screened from the third error messages according to a preset gating condition; and setting preset gating conditions including recording mode gating conditions and station information gating conditions, and screening the third error information which meets the preset gating conditions to serve as fourth error information. In step S160 of some embodiments, the fourth error message is stored in the memory. And storing the fourth error information into the memory so as to look up and locate the error reason at a later period.

By the error information recording method provided by the embodiment of the steps, each digital channel is distributed with the station information, and when the test vectors of at most 1600 ten thousand rows are operated, the generated error information is recorded without being limited by the total row number of the test vectors and the test period of the test vector operation, so that the error information can be recorded for a plurality of test stations while the test vectors are operated at high speed.

Referring to fig. 3, in some embodiments, step S120 may include, but is not limited to including, steps S210 to S230;

step S210, identifying error data in the channel data according to the truth table;

step S220, marking error data;

step S230, forming first error information according to the channel data with the error data flag and the corresponding station information.

Specifically, in step S210 of some embodiments, error data in the channel data is identified according to a truth table; in the test process, the test signal comprises cmpen comparison enable and cmptruth correct result, the two values are budgets stored on a digital board card, comql and comqh are feedback signals of the chip to be tested and are divided into low-level signals and high-level signals, and cmpresult is a comparison result, when the comparison result is 1, the feedback signal represents that the chip is in error, otherwise, the comparison result is correct. The truth table is shown in table 1:

in step S220 of some embodiments, the error data is marked. According to the truth table of table 1, only when the cmpresult comparison result is 1, the chip feeds back an error, and the error data is marked. In step S230 of some embodiments, a first error message is formed according to the channel data with the error data flag and the corresponding station information. In some embodiments, the error data of the marks is of the digital channel 1 station and the digital channel 4 station, and the channel data with the error data marks and corresponding station information forms the first error information.

TABLE 1

cmpen	cmptruth	cmpql	cmpqh	cmpresult
					0	x	x	x	0
1	0	0	0	0
					1	0	0	1	1
1	0	1	0	1
					1	0	1	1	1
1	1	0	0	1
					1	1	0	1	1
1	1	1	0	1
					1	1	1	1	0

By the error information recording method provided by the embodiment of the above steps of the present invention, the truth table rule is used to form the first error information, and since each digital channel marks the station information, the formed first error information contains the station information, thereby positioning the position of the error occurring in the channel data.

Referring to fig. 4, in some embodiments, step S130 may include, but is not limited to including, steps S310 to S340;

step S310, sending the first error information to an encoder in a wired communication mode;

step S320, the encoder converts the first error information into encoded data;

step S330, the coded data is adjusted through an equalizer to form second error information;

in step S340, the second error information is sent to the master control card through the driver.

Specifically, in step S310 of some embodiments, the first error information is sent to the encoder through wired communication; the parallel first error information will be sent to the 8B/10B encoder via the interface FIFO. In step S320 of some embodiments, the encoder converts the first error information into encoded data; to avoid data containing too long a link 0 or a link 1. Then, the data is sent to the serializer for parallel data conversion into serial data, and in step S330 of some embodiments, the encoded data is adjusted by the equalizer to form second error information. In step S340 of some embodiments, the second error information is sent to the master control card by the driver.

In some embodiments, the clock and data are transmitted separately using two sets of low voltage differential signal lines, transmitting the first error information to the master control card.

According to the error information recording method provided by the embodiment of the steps, only one group of differential lines is needed by a serializer method, high-speed data transmission can be completed, the speed of more than 1Gbit/s can be achieved, and the requirement of high-speed transmission of a large amount of data can be met.

Referring to fig. 5, in some embodiments, step S140 may include, but is not limited to including, steps S410 to S440;

step S410, setting a receiving number counter;

step S420, receiving second error information and calculating the number of lines;

step S430, analyzing the second error information into parallel data through a decoder;

step S440, a third error message is obtained according to the parallel data and the corresponding row number.

Specifically, in step S410 of some embodiments, a reception number counter is set; and setting a receiving number counter at the main control card end to count the currently received test vector of the few lines. In step S420 of some embodiments, receiving second error information and calculating a number of rows; in step S430 of some embodiments, the second error information is parsed into parallel data by a decoder; at the host card end, in a clock and data recovery circuit, the sampling clock is recovered from the data by the second serial error information, and the sampling clock is converted into an aligned parallel signal by a deserializer. And decoding or descrambling is completed through an 8B/10B decoder to form parallel data, and corresponding channel data can be analyzed from the parallel data. In step S440 of some embodiments, third error information is derived from the parallel data and the corresponding number of rows. And correspondingly counting every time a line of test vectors is received, and obtaining third error information according to the parallel data and the corresponding line number.

Through the error information recording method provided by the embodiment of the steps of the invention, parallel data can be converted into serial data through a method of a deserializer, high-speed data transmission is realized, the line number of each error is recorded in a counting mode, the position of the error in channel data is accurately positioned, and meanwhile, the recording can be started at any line number position to carry out fixed-point debugging.

Referring to fig. 6, in some embodiments, step S150 may include, but is not limited to including, steps S510 to S520;

step S510, screening third error information through the gating condition of the recording mode to form error information of the recording mode;

step S520, the error information of the recording mode is screened through the station information gating condition to form fourth error information.

Specifically, in step S510 of some embodiments, the third error information is filtered through the recording mode gating condition to form the recording mode error information; in some embodiments, the recording mode gating condition includes starting the recording mode according to the number of lines, recording only the error information, and starting the recording mode from the first line error information. Recording subsequent maximum 1024 rows according to the position record of the line number beginning according to the line number beginning recording mode; recording only the error information in the error information recording mode, namely recording only the error information in the fourth error information, and recording 1024 rows at maximum; the first row of error information starts to record the position of the first error information in the fourth error information, and then starts to record the next maximum 1024 rows.

In step S520 of some embodiments, the recording mode error information is further filtered through the station information gating condition to form a fourth error information. And transmitting third error information and corresponding line number to a station information gating condition, wherein the third error information is channel data gated by a recording mode, error data marks and corresponding station information are carried in the channel data, because the channel of the same digital board card can be distributed to different station information, one station information can correspond to digital channels on different digital board cards, each digital channel contains a failure flag bit, the failure flag bit is inverted to obtain a gating flag bit, and all the gating flag bits are subjected to AND operation to obtain whether to start recording the error information. In some embodiments, at the beginning, no error information occurs, the failure flag bits of all digital channels are 0, the failure flag bits are inverted to obtain all the gating flag bits are 1, and the gating flag bits are subjected to an and operation to obtain a result 1. Representing that recording of error information has not started currently. When the failure flag bit of one digital channel is set from 0 to 1, that is, when one of the gating flag bits is set from 1 to 0, all the gating flag bits are subjected to an and operation to obtain a result of 0, which represents that error information starts to be recorded. The recorded error information is recorded until the recording mode selected in step S510 is satisfied, for example, the recording mode is selected to start according to the number of lines, then the number of lines is recorded to start the next 1024 lines of data, and the data set is the fourth error information.

Referring to fig. 7, a schematic diagram of preset gating conditions of the error information recording method according to an embodiment of the present invention includes third error information 701, a recording mode gating condition 702, a station information gating condition 703, and fourth error information 704. The third error message 701 is first screened by the recording mode gating condition 702, and then screened by the station information gating condition 703 to obtain a fourth error message 704.

Referring to fig. 8, a diagram of a line condition of an error information recording method according to an embodiment of the present invention includes a line selection register 801, a line counter 802, a line enable 803, and a line pass gate 804. In some embodiments, a value of 5 is prestored in the row number selection register 801, the master control card starts to accept data, the row number counter 802 starts to count, when the count value is 4, the row number selection register 801 does not coincide with the number of the row number counter 802, the row number enable 803 is not opened, when the count value of the row number counter 802 is 5, the row number selection register 801 coincides with the number of the row number counter 802, the row number enable 803 is opened, and the row number gate is opened for information recording.

Referring to fig. 9, a schematic diagram of station information gating conditions of the error information recording method according to an embodiment of the present invention includes a recording mode error information 901, a station information gating condition 703, and a fourth error information 704. The error information 901 contains channel 0 data, channel 0 fail flag bit, channel 1 data, channel 1 fail flag bit, and the like in the recording mode. The condition that the digital channels start to record error information is that all the digital channels contain a failure flag bit, and as long as one channel has a failure flag position 1, all the digital channels in the same station are opened to start to record error information. It also means that if there is a gating flag position 0, all digital channels in the station will be opened, and error information will be recorded. The condition that the digital channel stops recording the error information is that all gating zone bits are 1 when the failure zone bit positions of all channels are 0, and the gating zone bit phases are 1 after the gating zone bit phases are 1, and the recording of the error information is stopped.

In some embodiments, the recording mode gating condition is selected as a line number starting recording mode, a subsequent maximum 1024 lines are recorded according to position recording of the line number starting, a channel 0, a channel 1, a channel 2 and the like correspond to a station 1, a test vector starts to work, channel data starts to be transmitted, wherein an error occurs in the digital channel 1, a gating flag bit is set to 0 from 1, error data starts to be recorded, after the test vector runs for a period of time, the number of lines counted by the channel 1 reaches 1024 lines, the gating flag bit is set to 1 from 0, the gating flag bits of other channels are also set to 1 at present, and finally, an AND result is 1, and error information is stopped to be recorded.

Referring to fig. 10, in some embodiments, step S520 may include, but is not limited to including, steps S610 to S630;

step S610, selecting a corresponding digital channel according to the station information;

step S620, taking non-operation back phases of failure flag bits of all digital channel stations in the station information to form station information gating conditions;

step S630, screening the error information of the recording mode meeting the station information gating condition as fourth error information.

In step S610 of some embodiments, the corresponding digital channel is selected according to the workstation information. A plurality of digital channels are arranged in the same digital board card, but station information marked by the digital channels is different, and the digital channels belonging to the same station information are selected into a set. In step S620 of some embodiments, the fail flag bits of all digital channel workstations in the workstation information are negated to form a workstation information gating condition. And when the failure mark position 1 represents the channel to transmit the failure mark position, the failure mark position is subjected to non-operation to obtain a gating mark position, then the gating mark position is subjected to phase comparison, the result of the phase comparison is 0, the error information is continuously recorded, and when the result of the phase comparison is 1, the error information is stopped to be recorded. In step S630 of some embodiments, the recording mode error information meeting the station information gating condition is screened as the fourth error information. According to the embodiment, error information recorded by the station information gating condition in step S620 is used as fourth error information, the fourth error information includes the selected channel data and the corresponding line number, the channel data is stored in the test vector operation data memory, and the corresponding line number is stored in the line number memory.

Referring to fig. 11, after the fourth error information is stored in the memory, the terminal device may retrieve data in the memory to read the fourth error information, and after the terminal device reads the fourth error information, compare the running data with the correct test vector to mark a vector point where an error occurs, so that the running error information of the test vector is clear at a glance, and a chip designer can further visually see the running condition of the test vector, so as to further analyze the error condition.

An embodiment of the present invention further provides an error information recording apparatus, which can implement the above error information recording method, wherein the test apparatus includes a plurality of digital boards, a master control card, and a memory, each digital board includes a plurality of digital channels, the plurality of digital boards are respectively connected to the master control card, and the memory is connected to the master control card, and the error information recording apparatus further includes:

the third error information analysis module is used for receiving the second error information sent by the digital board card and analyzing the third error information from the second error information;

the fourth error information screening module is used for screening out fourth error information from the third error information according to a preset gating condition;

The specific implementation of the error information recording apparatus of this embodiment is substantially the same as the specific implementation of the error information recording method, and is not described herein again.

An embodiment of the present disclosure further provides an electronic device, including:

at least one memory;

at least one processor;

at least one program;

the program is stored in the memory, and the processor executes at least one program to implement the error information recording method of the present invention described above. The electronic device can be any intelligent terminal including a mobile phone, a tablet computer, a Personal Digital Assistant (PDA for short), a vehicle-mounted computer and the like.

Referring to fig. 12, fig. 12 illustrates a hardware structure of an electronic device according to another embodiment, where the electronic device includes:

the processor 1201 may be implemented by a general-purpose CPU (central processing unit), a microprocessor, an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits, and is configured to execute a related program to implement the technical solution provided in the embodiment of the present invention;

the memory 1202 may be implemented in the form of a ROM (read only memory), a static memory device, a dynamic memory device, or a RAM (random access memory). The memory 1202 may store an operating system and other application programs, and when the technical solution provided by the embodiments of the present disclosure is implemented by software or firmware, the relevant program codes are stored in the memory 1202, and the processor 1201 calls the error information recording method for executing the embodiments of the present disclosure;

an input/output interface 1203 for implementing information input and output;

the communication interface 1204 is used for realizing communication interaction between the device and other devices, and may realize communication in a wired manner (e.g., USB, network cable, etc.) or in a wireless manner (e.g., mobile network, WIFI, bluetooth, etc.);

a bus 1205 that transfers information between the various components of the device (e.g., the processor 1201, memory 1202, input/output interface 1203, and communication interface 1204);

wherein the processor 1201, the memory 1202, the input/output interface 1203 and the communication interface 1204 enable communication connections with each other within the device via the bus 1205.

The embodiment of the present disclosure also provides a storage medium, which is a computer-readable storage medium storing computer-executable instructions for causing a computer to execute the above-mentioned error information recording method.

The memory, which is a non-transitory computer readable storage medium, may be used to store non-transitory software programs as well as non-transitory computer executable programs. Further, the memory may include high speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory optionally includes memory located remotely from the processor, and these remote memories may be connected to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The embodiment described in the embodiment of the present invention is for more clearly illustrating the technical solution of the embodiment of the present invention, and does not constitute a limitation to the technical solution provided in the embodiment of the present invention, and it can be known by those skilled in the art that the technical solution provided in the embodiment of the present invention is also applicable to similar technical problems with the evolution of technology and the occurrence of new application scenarios.

It will be understood by those skilled in the art that the technical solutions shown in fig. 2 to 6 and 10 do not limit the embodiments of the present invention, and may include more or less steps than those shown, or combine some steps, or different steps.

The above-described embodiments of the apparatus are merely illustrative, wherein the units illustrated as separate components may or may not be physically separate, i.e. may be located in one place, or may also be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, and functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof.

The terms "first," "second," "third," "fourth," and the like in the description of the application and the above-described figures, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be implemented in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be understood that in the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" for describing an association relationship of associated objects, indicating that there may be three relationships, e.g., "a and/or B" may indicate: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may also be implemented in the form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes multiple instructions for causing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing programs, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, and are not intended to limit the scope of the embodiments of the invention. Any modifications, equivalents and improvements that may occur to those skilled in the art without departing from the scope and spirit of the embodiments of the present invention are intended to be within the scope of the claims of the embodiments of the present invention.

Claims

1. An error information recording method is characterized in that the method is applied to a testing device, the testing device comprises a plurality of digital board cards, a main control card and a memory, each digital board card comprises a plurality of digital channels, the digital board cards are respectively connected with the main control card, and the memory is connected with the main control card, and the method comprises the following steps:

creating and operating a test vector to generate channel data;

and storing the fourth error information into the memory.

2. The method of claim 1, wherein the controlling the digital board to mark the error data and the corresponding station information in the channel data according to a preset rule to form a first error message includes:

identifying error data in the channel data according to a truth table;

marking the error data;

3. The method as claimed in claim 2, wherein said controlling the digital board to convert the first error information into the second error information by data transmission comprises:

the encoder converts the first error information into encoded data;

4. The method according to claim 3, wherein the receiving the second error information sent by the digital board card and analyzing a third error information from the second error information includes:

setting a receiving number counter;

receiving the second error information and calculating the number of rows;

parsing the second error information into parallel data through a decoder;

5. The method according to claim 4, wherein the screening out fourth error information from the third error information according to a preset gating condition comprises:

6. The error information recording method according to claim 5, wherein the recording mode strobe condition includes a start of recording mode according to a number of lines, a record error information only recording mode, and a start of recording mode from the first line error information.

7. The method of claim 5, wherein the step of screening the recording mode error message by a station information gating condition to form the fourth error message comprises:

selecting a corresponding digital channel according to the station information;

8. The utility model provides an error message recorder, its characterized in that, testing arrangement includes a plurality of digital integrated circuit boards, master control card and memory, every contain a plurality of digital channels in the digital integrated circuit board, a plurality of digital integrated circuit boards are connected with the master control card respectively, the memory with the master control card is connected, still includes:

9. An electronic device, comprising:

at least one memory;

at least one processor;

at least one program;

the error information recording method according to any one of claims 1 to 7.

10. A storage medium that is a computer-readable storage medium having stored thereon computer-executable instructions for causing a computer to perform:

the error information recording method according to any one of claims 1 to 7.