CN114697168B - Hundred mega Ethernet digital baseband signal processing method and signal processing module - Google Patents

Hundred mega Ethernet digital baseband signal processing method and signal processing module Download PDF

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CN114697168B
CN114697168B CN202210612372.4A CN202210612372A CN114697168B CN 114697168 B CN114697168 B CN 114697168B CN 202210612372 A CN202210612372 A CN 202210612372A CN 114697168 B CN114697168 B CN 114697168B
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刘德良
欧阳翔
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Nanjing Qinheng Microelectronics Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H04L25/0307—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure using blind adaptation

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Abstract

The invention discloses a hundred mega Ethernet digital baseband signal processing method and a signal processing module, comprising the following steps: presetting a first iteration time threshold and a second iteration time threshold; carrying out amplitude adjustment and ADC sampling on the channel signal; carrying out DFE self-adaptive equalization on the sampled signal, and only starting the DFE self-adaptive equalization and not starting CDR phase tracking when the iteration number of the self-adaptive equalization does not reach a first iteration number threshold; when the iteration number of the self-adaptive equalization reaches a first iteration number threshold value, the DFE self-adaptive equalization is continued, and CDR phase tracking is started; in the DFE adaptive equalization process, different methods are selected according to the iteration number to adjust the coefficients of the feedforward filter and the feedback filter in the DFE. The invention can solve the problem of hundred mega Ethernet ISI, has high convergence rate, high precision and stable system, and can not influence each other among modules.

Description

Hundred mega Ethernet digital baseband signal processing method and signal processing module
Technical Field
The invention relates to the technical field of hundred-mega Ethernet communication, in particular to a hundred-mega Ethernet digital baseband signal processing method and a signal processing module.
Background
The 100Base-Tx adopts a baud rate of 125M to transmit a 100Mbps signal, and a receiving end needs to recover a channel signal and restore the signal to an original signal. In the twisted pair transmission channel adopted by 100Base-Tx, the signal has more serious high-frequency attenuation, so that more serious intersymbol interference (ISI) problem is generated, and therefore, the adaptive equalization needs to be completed at this stage.
In the Ethernet, a Decision Feedback Equalization (DFE) algorithm is generally adopted to eliminate the influence of ISI, but in 100Base-Tx, a MLT-3 three-level transmission mode is adopted, and if the processing is not good, the DFE algorithm is easy to generate a phenomenon of non-convergence, so that the normal transmission of signals is influenced.
Disclosure of Invention
The invention aims to: in order to solve the problems that in the prior art, the balance is not easy to converge in the process of hundred-mega Ethernet communication and the inter-code crosstalk cannot be solved, the invention provides a hundred-mega Ethernet digital baseband signal processing method and a signal processing module.
The technical scheme is as follows: a hundred mega Ethernet digital baseband signal processing method comprises the following steps:
presetting a first iteration time threshold and a second iteration time threshold;
receiving a channel signal, and performing amplitude adjustment and ADC (analog to digital converter) sampling on the channel signal, wherein the method specifically comprises the following steps:
detecting whether a channel signal is received by adopting a moving average method, specifically:
let r be the sampling signal sampled and output by the ADC with 125MHz clock frequency m ，r m Representing the sample value at the m-th instant, the corresponding absolute amplitude value being represented as mu m Then the output of the sliding filter can be expressed as:
Figure GDA0003808294710000011
wherein α is a moving average factor when
Figure GDA0003808294710000012
At the receiving end, it is considered that a signal, th, is received 0 M represents the mth moment;
amplifying the received channel signal by a programmable gain amplifier, then carrying out ADC sampling on the signal with the adjusted amplitude, and respectively inputting the obtained sampling signal into an analog AGC and a digital AGC, wherein the analog AGC adopts a peak AGC algorithm to adjust the gain of the programmable gain amplifier to ensure that the ADC output is effective; the digital AGC adjusts the amplitude of the sampling signal by adopting a successive approximation method;
the peak AGC algorithm specifically includes:
(a1) Presetting step length regulating threshold q 0 And q is 1 ，q 0 ＞q 1 More than 0, presetting two gain adjustment step lengths eta 0 、η 1 ，η 0 ＞η 1 Is greater than 0; gain to programmable gain amplifier
Figure GDA0003808294710000013
Adjustment value Λ 0 The initial setting is carried out and,
Figure GDA0003808294710000014
Λ 0 =0, number of iterations i =0;
(a2) Setting the actual gain of the programmable gain amplifier to
Figure GDA0003808294710000021
Λ i Representing the ith gain adjustment value of the analog AGC and waiting for the gain adjustment value to be effective;
(a3) Storing the sampling point output by ADC in window W, and simultaneously, the amplitude exceeds Th 0 Counting the number of sampling points stored in the window W to M 0 While exceeding Th 0 Total number of sampling points of (C) i ；
(a4) If C i ≥q 0 A then i+1 ＝Λ i -η 0 ；
If q is 1 ≤C i ＜q 0 Then a i+1 ＝Λ i -η 1 ；
If C i ＜q 1 A then i+1 ＝Λ i ；
(a5) Judging whether a circulation condition is satisfied, wherein the circulation condition is as follows:
Figure GDA0003808294710000022
in the gain adjustment range of the programmable gain amplifier
Figure GDA0003808294710000023
Inner and Λ i+1 ≠Λ i If the loop condition is satisfied, i = i +1, and the steps (a 2) to (a 5) are continuously executed in an iterative manner; if the circulation condition is not satisfied, ending the analog AGC adjustment;
performing DFE self-adaptive equalization on the sampled signal, and starting DFE self-adaptive equalization only and not starting CDR phase tracking when the iteration number of the self-adaptive equalization does not reach a first iteration number threshold; when the iteration number of the self-adaptive equalization reaches a first iteration number threshold value, the DFE self-adaptive equalization is continued, and CDR phase tracking is started;
in the self-adaptive equalization process of the DFE, selecting a corresponding method according to the iteration times to adjust coefficients of a feedforward filter and a feedback filter in the DFE, and when the iteration times of the self-adaptive equalization are less than a second iteration time threshold, adjusting by adopting a blind equalization algorithm suitable for MLT-3; when the iteration number of the self-adaptive equalization reaches a second iteration number threshold value, adjusting by adopting a coefficient-variable equalization algorithm;
setting the coefficients of a feedforward filter to
Figure GDA0003808294710000024
The coefficients of the feedback filter are
Figure GDA0003808294710000025
Wherein L is 0 And L 1 Respectively representing the order of the feedforward filter and the order of the feedback filter, and setting the signal entering the decision device as
Figure GDA0003808294710000026
The output signal of the decision device is
Figure GDA0003808294710000027
n denotes the number of iterations, l denotes the coefficient of the ith order,
the blind equalization algorithm applicable to MLT-3 specifically includes:
defining intermediate parameters e n If at all
Figure GDA0003808294710000028
Let E be n =0; if it is
Figure GDA0003808294710000029
Order to
Figure GDA00038082947100000210
The coefficients of the feedforward filter are adjusted to:
Figure GDA00038082947100000211
the coefficients of the feedback filter are adjusted as follows:
Figure GDA00038082947100000212
wherein λ is 0 Is an adjustment step size of a blind equalization algorithm suitable for MLT-3; r' n-l Is relative to r' n Lagging by l sample intervals of signal r' n An input signal adaptively equalized for the DFE;
Figure GDA00038082947100000213
representing the ith order coefficient of the coefficients of the feedforward filter at the nth iteration,
Figure GDA00038082947100000214
represents the ith order coefficient among the coefficients of the feedforward filter at iteration n +1,
Figure GDA00038082947100000215
representing the ith order coefficient of the coefficients of the feedback filter at the nth iteration,
Figure GDA00038082947100000216
represents the ith order coefficient among the coefficients of the feedback filter at the (n + 1) th iteration,
Figure GDA00038082947100000217
is relative to
Figure GDA00038082947100000218
A signal lagging by l-1 sampling intervals;
the equalization algorithm of the variable coefficient specifically comprises:
the coefficients of the feedforward filter are adjusted to:
Figure GDA00038082947100000219
the coefficients of the feedback filter are adjusted as follows:
Figure GDA0003808294710000031
wherein λ is 1 The adjustment step length of the equalization algorithm is variable coefficient; the decision error is
Figure GDA0003808294710000032
Further, in the coefficient-variable equalization algorithm, a third iteration number threshold is preset, and when the adaptive iteration number does not reach the third iteration number threshold, lambda is set 1 ＝λ 11 (ii) a When the adaptive iteration number reaches a third iteration number threshold value, lambda 1 ＝λ 12 (ii) a Wherein λ is 11 First adjustment step length in equalization algorithm for variable coefficient, lambda 12 Is of variable coefficientSecond adjustment step size, lambda, in the scale algorithm 12 ＜λ 11 。
Further, the method for the digital AGC to adopt successive approximation specifically includes:
(b1) Let the absolute amplitude of the digital AGC output signal at time t be v t (ii) a The ith gain adjustment step size is epsilon i ，ε i ∈[δ，Δ max ]Delta is epsilon i Minimum value of, Δ max Is epsilon i A maximum value that is desirable; epsilon 0 An initial value of a gain adjustment step length; delta of i The adjustment value of the programmable gain amplifier of the ith iteration;
presetting AGC output signal threshold as Th 1 (ii) a Gain g for programmable gain amplifier ini Adjustment value delta 0 Make an initialization setting, Δ 0 ＝0、ε 0 ＝Δ max The iteration number i =0;
(b2) Setting the actual gain of the programmable gain amplifier to g i+1 ＝g ini +Δ i Waiting for the validation;
(b3) Calculating an average amplitude value of a signal
Figure GDA0003808294710000033
M 1 For the number of samples used to calculate the average signal amplitude value, v t+l Represents the absolute magnitude of the digital AGC output signal at time (t + l);
(b4) If v is avg ＜Th 1 Then a is Δ i+1 ＝Δ i +ε i ；
If v is avg ≥Th 1 Then a is i+1 ＝Δ i -ε i ；
(b5)
Figure GDA0003808294710000034
Judging whether a circulation condition is satisfied, wherein the circulation condition is as follows: epsilon i+1 δ is larger than or equal to, if the loop condition is satisfied, i = i +1, and the steps (b 2) to (b 5) are continuously executed in an iteration mode; if the loop condition is not satisfied, the digital AGC adjustment is finished.
A hundred mega Ethernet digital baseband signal processing module adopts the method, which comprises a sampling amplifying unit, a decision feedback equalizing unit and a CDR phase tracking unit; the input end of the sampling amplification unit inputs a channel signal, and the output end of the sampling amplification unit is connected with the input end of the decision feedback equalization unit; the output end of the decision feedback equalization unit outputs the processed signal and is connected with the input end of the CDR phase tracking unit; the output end of the CDR phase tracking unit is connected with the sampling amplification unit; the sampling amplification unit comprises a programmable gain amplifier, an ADC sampling conversion unit, an analog AGC unit and a digital AGC unit; the input end of the programmable gain amplifier is connected with a channel signal, the output end of the programmable gain amplifier is connected with the ADC sampling conversion unit, the output end of the ADC sampling conversion unit is connected with the digital AGC unit and the analog AGC unit, the output end of the analog AGC unit is connected with the programmable gain amplifier, and the output end of the digital AGC unit is connected with the decision feedback equalization unit.
Compared with the prior art, the invention provides a hundred-mega Ethernet digital baseband signal processing method and a signal processing module, and has the following beneficial effects:
(1) The DFE part adopts a staged equalization algorithm, a blind equalization algorithm adaptive to MLT-3 is adopted for cold start when equalization is started, equalization errors are pulled to a reasonable interval, and then optimized equalization convergence performance is obtained by adopting a conventional equalization algorithm with variable coefficients, so that the whole adaptive equalization process can be converged more steadily, better precision can be achieved, and the problem of instability can be avoided.
(2) The two aspects of the self-adaptive equalization and the clock timing recovery are coordinated, and the start of the CDR is set to be delayed compared with the DFE properly, so that the mutual influence between the DFE and the CDR is reduced to the minimum, and the signal recovery effect is improved.
(3) The input signal to the DFE is adjusted to a suitable amplitude level using a dual AGC approach combining analog and digital AGC. Analog AGC targets the AGC convergence such that the peak value of the ADC output signal does not exceed a certain proportion of the maximum value of the ADC, so that the number of significant bits of the ADC output is as large as possible, accommodating baseline wander (BLW) issues with 100Base-Tx signals. The digital AGC takes the average value of the signal amplitude as an AGC convergence target, and provides guarantee for convergence of a subsequent DFE algorithm through a steady successive approximation type AGC method on the premise of guaranteeing the convergence speed, so that the DFE cannot have the problem of non-convergence in the coefficient self-adaptive adjustment process. Therefore, the signal sampling and amplifying process can provide guarantee for the convergence of the subsequent DFE algorithm on the premise of guaranteeing the convergence speed, and further avoid the problem that the DFE is not converged in the coefficient self-adaptive adjustment process.
(4) The baseband processing of the digital domain is carried out on the signal by adopting a baud rate processing mode, namely when ADC (analog to digital converter) sampling is carried out on the received analog signal, the frequency of a sampling clock is 125MHz, and the signal processing with low power consumption can be realized.
Drawings
Fig. 1 is a schematic structural diagram of a hundred mega ethernet digital baseband signal processing module;
FIG. 2 is a schematic diagram of a CDR phase tracking unit;
FIG. 3 is a diagram illustrating the convergence process of the equalization error in the actual measurement experiment;
FIG. 4 is a timing offset accumulation process in an actual measurement experiment;
fig. 5 is an indication of clock phase adjustment during measurement experiments.
Detailed Description
The invention is further explained below with reference to the figures and the specific embodiments.
A hundred mega ethernet digital baseband signal processing module, as shown in fig. 1, includes a sampling amplifying unit, a decision feedback equalizing unit (DFE) and a CDR phase tracking unit; the input end of the sampling amplification unit inputs a channel signal, and the output end of the sampling amplification unit is connected with the input end of the decision feedback equalization unit; the output end of the decision feedback equalization unit outputs the processed signal and is connected with the input end of the CDR phase tracking unit; the output end of the CDR phase tracking unit is connected with the sampling amplification unit.
The sampling amplification unit comprises a Programmable Gain Amplifier (PGA), an ADC sampling conversion unit, an analog AGC unit and a digital AGC unit; the input end of the programmable gain amplifier is connected with a channel signal, the output end of the programmable gain amplifier is connected with the ADC sampling conversion unit, the output end of the ADC sampling conversion unit is connected with the digital AGC unit (AGC 0) and the analog AGC unit (AGC 1), the output end of the analog AGC unit is connected with the programmable gain amplifier, and the output end of the digital AGC unit is connected with the decision feedback equalization unit.
The decision feedback equalization unit comprises a Feed Forward Filter (FFF), a feedback filter (FBF) and a decision device. The CDR phase tracking unit is used for providing a recovery phase for the ADC sampling conversion unit.
The hundred-mega Ethernet digital baseband signal processing module is realized by adopting the following hundred-mega Ethernet digital baseband signal processing method, and comprises the following steps:
1. and presetting a first iteration time threshold and a second iteration time threshold.
2. Receiving a channel signal, and performing amplitude adjustment and ADC (analog to digital converter) sampling on the channel signal, specifically comprising the following steps:
whether the channel signal is received or not is detected, and AGC work can be started after the channel signal is accurately detected. Amplifying the received channel signal by a programmable gain amplifier, then carrying out ADC sampling on the signal with the adjusted amplitude, and respectively inputting the obtained sampling signal into an analog AGC and a digital AGC, wherein the analog AGC adopts a peak AGC algorithm to adjust the gain of the programmable gain amplifier to ensure that the ADC outputs effective digits as much as possible under the condition of ensuring that the ADC input signal does not overflow; after the gain of the PGA is adjusted in place through the analog AGC, the digital domain gain is adjusted through the AGC1, and because the system adopts a continuous signal transmission mode and always transmits idle signals before both sides formally confirm, the digital AGC adopts a successive approximation method to adjust the amplitude of a sampling signal, so that the average amplitude is close to a preset threshold value.
The detection method for detecting whether the channel signal is received is a moving average method, and specifically includes:
let r be the sampling signal sampled and output by the ADC with 125MHz clock frequency m ，r m The value of the absolute amplitude corresponding to the sample value representing the m-th time instant is represented as mu m Then the output of the sliding filter can be expressed as:
Figure GDA0003808294710000051
wherein α is a moving average factor when
Figure GDA0003808294710000052
At the receiving end, it is considered that a signal, th, is received 0 For the signal detection threshold, m represents the mth time instant.
1. The peak AGC algorithm aims at that the amplitude of an ADC output signal is at a threshold Th 0 The method specifically comprises the following steps:
(a1) Presetting step length regulating threshold q 0 And q is 1 ，q 0 ＞q 1 Greater than 0, presetting two gain adjustment step lengths eta 0 、η 1 ，η 0 ＞η 1 Is greater than 0; gain to programmable gain amplifier
Figure GDA0003808294710000053
Adjustment value Λ 0 The initial setting is carried out and,
Figure GDA0003808294710000054
Λ 0 =0, number of iterations i =0; as the 100Base-TX adopts more than 5 types of network cables for transmission, the maximum transmission distance specified by the protocol is more than 100 meters. The signal transmission loss caused by the line is typically below 10dB,
Figure GDA0003808294710000055
the setting is suitably about 10 dB. Simultaneously setting a number of stored samples as M 0 The window W of (a).
(a2) Setting the actual gain of the programmable gain amplifier to
Figure GDA0003808294710000056
Λ i Represents the ith gain adjustment value of the analog AGC and waits for the effective time t AGCO I.e. the gain transformation effective time of the PGA;
(a3) Store the sampling points output by the ADC to the window W, while aligning the amplitudesOver Th 0 Counting the number of sampling points stored in the window W to M 0 While exceeding Th 0 Total number of sampling points of (C) i ；
(a4) If C i ≥q 0 Then a i+1 ＝Λ i -η 0 ；
If q is 1 ≤C i ＜q 0 Then a i+1 ＝Λ i -η 1 ；
If C i ＜q 1 Then a i+1 ＝Λ i ；
(a5) Judging whether a circulation condition is satisfied, wherein the circulation condition is as follows:
Figure GDA0003808294710000061
in the gain adjustment range of the programmable gain amplifier
Figure GDA0003808294710000062
Inner and Λ i+1 ≠Λ i If the loop condition is satisfied, i = i +1, and the steps (a 2) to (a 5) are continuously executed in an iterative manner; if the circulation condition is not satisfied, the analog AGC adjustment is finished.
2. The digital AGC adopts a successive approximation method, and the aim is to ensure that the average amplitude value of the output signal of the digital AGC is closest to a threshold Th 1 The method specifically comprises the following steps:
(b1) Let the absolute amplitude of the digital AGC output signal at time t be v t (ii) a The ith gain adjustment step length is epsilon i ，ε i ∈[δ，Δ max ]Delta is epsilon i Minimum value, Δ max Is epsilon i A maximum value that is desirable; epsilon 0 An initial value of a gain adjustment step length; delta i The adjustment value of the programmable gain amplifier of the ith iteration; presetting AGC output signal threshold as Th 1 (ii) a Gain g for programmable gain amplifier ini Adjustment value delta 0 Make an initialization setting, Δ 0 ＝0、ε 0 ＝Δ max (usually even), number of iterations i =0;
(b2) Setting the actual gain of the programmable gain amplifier to g i+1 ＝g ini +Δ i Waiting for the time of validation t AGC1 I.e. the gain transformation effective time of the PGA;
(b3) Calculating the mean amplitude value of the signal
Figure GDA0003808294710000063
M 1 For the number of samples used to calculate the average signal amplitude value, v t+l Represents the absolute amplitude of the digital AGC output signal at time (t + l);
(b4) If v is avg ＜Th 1 Then a is Δ i+1 ＝Δ i +ε i ；
If v is avg ≥Th 1 Then a is i+1 ＝Δ i -ε i ；
(b5)
Figure GDA0003808294710000064
Judging whether a circulation condition is satisfied, wherein the circulation condition is as follows: epsilon i+1 If the loop condition is satisfied, i = i +1, and the steps (b 2) to (b 5) are continuously executed in an iteration mode; if the loop condition is not satisfied, the digital AGC adjustment is ended.
3. After the AGC signal is adjusted to an appropriate amplitude level through the above steps, the signal recovery stage can be formally entered.
At this stage, the tasks of both adaptive equalization and clock timing recovery need to be completed. In the twisted pair transmission channel employed in 100Base-Tx, there is more severe high frequency attenuation, which will result in more severe inter-symbol interference (ISI) problems. There is therefore a need to overcome this effect by adaptive equalization. In addition, the transceiving clocks have the problem of inconsistent frequency and phase, so the receiving end needs to acquire clock synchronization of the transceiving end through clock tracking. And as the receiving end reduces the power consumption, a clock of 125MHz is adopted for signal sampling. Therefore, the receiving end needs to adopt a baud rate CDR (clock and data recovery) algorithm for clock tracking.
However, since the CDR and DFE are tightly coupled. Therefore, the DFE start-up phase is not suitable for CDR start-up due to large equalization error. Thus, the CDR needs to be formally initiated after the DFE is iterated for a period of time, such as a first threshold number of iterations. When the iteration times of the self-adaptive equalization do not reach a first iteration time threshold, only starting the DFE self-adaptive equalization and not starting the CDR phase tracking; when the iteration number of the self-adaptive equalization reaches a first iteration number threshold value, the DFE self-adaptive equalization is continued, and CDR phase tracking is started;
in the DFE self-adaptive equalization process, selecting a corresponding method according to the iteration times to adjust coefficients of a feedforward filter and a feedback filter in the DFE, and when the iteration times of the self-adaptive equalization is less than a second iteration time threshold, adjusting by adopting a blind equalization algorithm suitable for MLT-3; and when the iteration number of the self-adaptive equalization reaches a second iteration number threshold value, adjusting by adopting a coefficient-variable equalization algorithm.
Let the coefficients of the feedforward filter in the DFE be
Figure GDA0003808294710000071
The coefficients of the feedback filter are
Figure GDA0003808294710000072
Wherein L is 0 And L 1 Representing the order of the feedforward and feedback filters, respectively.
The FFF filtered signal is
Figure GDA0003808294710000073
The FBF-filtered signal is
Figure GDA0003808294710000074
The signal entering the decision device is
Figure GDA0003808294710000075
With a decision output of
Figure GDA0003808294710000076
In order to enable robust convergence of the DFE adaptive equalization algorithm, two equalization algorithms are employed as follows:
1. the blind equalization algorithm suitable for the MLT-3 specifically includes:
defining intermediate parameters e n If at all
Figure GDA0003808294710000077
Let e be n =0; if it is
Figure GDA0003808294710000078
Order to
Figure GDA0003808294710000079
The coefficients of the feedforward filter are adjusted to:
Figure GDA00038082947100000710
the coefficients of the feedback filter are adjusted as follows:
Figure GDA00038082947100000711
wherein λ is 0 Is an adjustment step size of a blind equalization algorithm applicable to MLT-3; r' n-l Is relative to r' n Signal r 'lagging by l sampling interval' n For DFE adaptive equalization of the input signal, n denotes the number of iterations, l denotes the coefficient of the l < th > order,
Figure GDA00038082947100000712
representing the ith order coefficient of the coefficients of the feedforward filter at the nth iteration,
Figure GDA00038082947100000713
representing the ith order coefficient among the coefficients of the feedforward filter at iteration n +1,
Figure GDA00038082947100000714
representing the ith order coefficient among the coefficients of the feedback filter at the nth iteration,
Figure GDA00038082947100000715
represents the ith order coefficient among the coefficients of the feedback filter at the (n + 1) th iteration,
Figure GDA00038082947100000716
is relative to
Figure GDA00038082947100000717
Lagging by l-1 sample interval.
2. The equalization algorithm of the variable coefficient specifically comprises:
the coefficients of the feedforward filter are adjusted to:
Figure GDA00038082947100000718
the coefficients of the feedback filter are adjusted as follows:
Figure GDA00038082947100000719
wherein λ is 1 The adjustment step length of the equalization algorithm is variable coefficient; is r' n-l Is relative to r' n Lagging by l sample intervals of signal r' n For adaptive equalization of the input signal by the DFE, the decision error is
Figure GDA0003808294710000081
In the variable coefficient equalization algorithm, a third iteration time threshold value can be preset, and when the self-adaptive iteration time does not reach the third iteration time threshold value, lambda is 1 ＝λ 11 (ii) a When the adaptive iteration number reaches a third iteration number threshold value, lambda 1 ＝λ 12 (ii) a Wherein λ is 11 First adjustment step length, lambda, in the equalization algorithm for variable coefficients 12 Second adjustment step size, lambda, in a coefficient-varying equalization algorithm 12 ＜λ 11 . So that the equalization error can converge to a smaller position.
Of course, the performance of the DFE algorithm is affected by the CDR algorithm, which are tightly coupled. If the CDR cannot adjust the phase of the clock in place instantaneously, the DFE is also very prone to divergence, resulting in failure of signal recovery. Here, a CDR algorithm based on phase interpolation is used, each clock cycle is divided into P phases, and each symbol period clock generation module advances or retreats by one clock phase according to the indication signal provided by the CDR module. The CDR module consists of phase detection, loop filtering, and offset accumulation, as shown in fig. 2. The phase detection part adopts the following baud rate phase detection algorithm:
Figure GDA0003808294710000082
the phase-discriminated output error signal will enter the following loop filter:
Figure GDA0003808294710000083
wherein K p For phase detection gain, β is a parameter of the loop filter, usually taking a small value. By adjusting the two parameters, different frequency offset tracking capabilities can be obtained.
Output ζ of loop filter n Will enter the offset accumulation section, which outputs τ n ＝τ n-1 +ζ n . When the temperature is higher than the set temperature
τ n ＞τ Th When the clock is in the forward phase, the CDR module inputs +1 to indicate the clock to adjust a phase forward; when tau is measured n ＞-τ Th The CDR block inputs-1, which instructs the clock to adjust one phase backwards.
In the CDR phase tracking process, phase discrimination and loop filtering are reasonably designed, and the clock synchronization of transmitting and receiving double-transmission is realized by adjusting the phase of the multi-phase clock.
Fig. 3 to 5 show the equalization error convergence process (fig. 3), the timing offset accumulation process (fig. 4), and the clock phase adjustment instruction (fig. 5) measured by experiment in the case of the network line length of 150 meters. In this experiment, the parameters of the DFE section were set as follows:
m 0 ＝2 8 、m 1 ＝2 9 、m 2 ＝2 8 、λ 0 ＝2 -6 、λ 1 ＝2 -7 、λ 2 ＝2 -9 . The parameters of the CDR portion are set as follows: number of clock phases P =32, K p And (5) 1/8. The actual measurement result shows that the stable transmission of the Ethernet signals can be realized under the condition that the length of the network cable reaches 150 meters.

Claims (4)

1. A hundred mega Ethernet digital baseband signal processing method is characterized by comprising the following steps:
presetting a first iteration time threshold and a second iteration time threshold;
receiving a channel signal, and performing amplitude adjustment and ADC (analog to digital converter) sampling on the channel signal, specifically comprising the following steps:
detecting whether a channel signal is received by adopting a moving average method, specifically:
let r be the sampling signal sampled and output by the ADC with 125MHz clock frequency m ，r m Representing the sample value at the m-th instant, the corresponding absolute amplitude value being represented as mu m Then the output of the sliding filter can be expressed as:
Figure FDA0003808294700000011
wherein α is a moving average factor when
Figure FDA0003808294700000012
At the receiving end, it is considered that a signal, th, is received 0 M represents the mth moment;
amplifying the received channel signal by a programmable gain amplifier, then carrying out ADC sampling on the signal with the adjusted amplitude, and respectively inputting the obtained sampling signal into an analog AGC (automatic gain control) and a digital AGC (automatic gain control), wherein the analog AGC adopts a peak AGC algorithm to adjust the gain of the programmable gain amplifier to ensure that the ADC output is effective; the digital AGC adjusts the amplitude of the sampling signal by adopting a successive approximation method;
the peak AGC algorithm specifically includes:
(a1) Presetting step length regulating threshold q 0 And q is 1 ，q 0 ＞q 1 More than 0, presetting two gain adjustment step lengths eta 0 、η 1 ，η 0 ＞η 1 Is greater than 0; gain to programmable gain amplifier
Figure FDA0003808294700000013
Adjustment value Λ 0 The initial setting is carried out and,
Figure FDA0003808294700000014
Λ 0 =0, number of iterations i =0;
(a2) Setting the actual gain of the programmable gain amplifier to
Figure FDA0003808294700000015
Λ i Representing the ith gain adjustment value of the analog AGC and waiting for the gain adjustment value to be effective;
(a3) Storing the sampling point output by ADC in window W, and simultaneously, the amplitude exceeds Th 0 Counting the sampling points, and counting the number of the sampling points stored in the window W to M 0 While exceeding Th 0 Total number of sampling points of (C) i ；
(a4) If C i ≥q 0 Then a i+1 ＝Λ i -η 0 ；
If q is 1 ≤C i ＜q 0 Then a i+1 ＝Λ i -η 1 ；
If C i ＜q 1 A then i+1 ＝Λ i ；
(a5) Judging whether a circulation condition is satisfied, wherein the circulation condition is as follows:
Figure FDA0003808294700000016
in the gain adjustment range of the programmable gain amplifier
Figure FDA0003808294700000017
Inner and Λ i+1 ≠Λ i If the loop condition is satisfied, i = i +1, and the steps (a 2) to (a 5) are executed iteratively; if the circulation condition is not satisfied, ending the analog AGC adjustment;
carrying out DFE self-adaptive equalization on the sampled signal, and only starting the DFE self-adaptive equalization and not starting CDR phase tracking when the iteration number of the self-adaptive equalization does not reach a first iteration number threshold; when the iteration number of the self-adaptive equalization reaches a first iteration number threshold value, the DFE self-adaptive equalization is continued, and CDR phase tracking is started;
in the DFE self-adaptive equalization process, selecting a corresponding method according to the iteration times to adjust coefficients of a feedforward filter and a feedback filter in the DFE, and when the iteration times of the self-adaptive equalization is less than a second iteration time threshold, adjusting by adopting a blind equalization algorithm suitable for MLT-3; when the iteration number of the self-adaptive equalization reaches a second iteration number threshold value, adjusting by adopting a coefficient-variable equalization algorithm;
setting the coefficients of a feedforward filter to
Figure FDA0003808294700000021
The coefficients of the feedback filter are
Figure FDA0003808294700000022
Wherein L0 and L1 respectively represent the order of the feedforward filter and the order of the feedback filter, and the signal entering the decision device is set as
Figure FDA0003808294700000023
The output signal of the decision device is
Figure FDA0003808294700000024
n represents the number of iterations and,lis shown aslThe order coefficient of the first-order coefficient,
the blind equalization algorithm applicable to MLT-3 specifically includes:
defining intermediate parameters e n If, if
Figure FDA0003808294700000025
Let e be n =0; if it is
Figure FDA0003808294700000026
Order to
Figure FDA0003808294700000027
The coefficients of the feedforward filter are adjusted to:
Figure FDA0003808294700000028
the coefficients of the feedback filter are adjusted as follows:
Figure FDA0003808294700000029
wherein λ is 0 Is an adjustment step size of a blind equalization algorithm applicable to MLT-3; r' ln- Is relative to r' n HysteresislSignal of one sampling interval r' n An input signal adaptively equalized for the DFE;
Figure FDA00038082947000000210
representing the second of the coefficients of the feedforward filter at the nth iterationlThe order of the coefficients,
Figure FDA00038082947000000211
representing the second of the coefficients of the feedforward filter at the (n + 1) th iterationlThe order coefficient of the first-order coefficient,
Figure FDA00038082947000000212
representing the th of coefficients of the feedback filter at the nth iterationlThe order of the coefficients,
Figure FDA00038082947000000213
representing the th of coefficients of a feedback filter at the (n + 1) th iterationlThe order coefficient of the first-order coefficient,
Figure FDA00038082947000000214
is relative to
Figure FDA00038082947000000215
Hysteresisl-1 sampling interval signal;
the variable coefficient equalization algorithm specifically includes:
the coefficients of the feedforward filter are adjusted to:
Figure FDA00038082947000000216
the coefficients of the feedback filter are adjusted as follows:
Figure FDA00038082947000000217
wherein, λ 1 is the adjusting step length of the equalization algorithm of the variable coefficient; the decision error is
Figure FDA00038082947000000218
2. The method as claimed in claim 1, wherein a third threshold of iteration times is preset in the equalization algorithm with variable coefficients, and λ is determined when the adaptive iteration times does not reach the third threshold of iteration times 1 ＝λ 11 (ii) a When the adaptive iteration number reaches a third iteration number threshold value, lambda 1 ＝λ 12 (ii) a Wherein λ is 11 First adjustment step length in equalization algorithm for variable coefficient, lambda 12 Second adjustment step size, lambda, in the coefficient-variable equalization algorithm 12 ＜λ 11 。
3. The method for processing the hundred mega ethernet digital baseband signal according to claim 1, wherein the method for the digital AGC to adopt successive approximation specifically includes:
(b1) Let the absolute amplitude of the digital AGC output signal at time t be v t (ii) a The ith gain adjustment step size is epsilon i ，ε i ∈[δ，Δ max ]Delta is epsilon i Minimum value of, Δ max Is epsilon i A maximum value that is desirable; epsilon 0 An initial value of a gain adjustment step length; delta i The adjustment value of the programmable gain amplifier of the ith iteration;
presetting AGC output signal threshold as Th 1 (ii) a Gain g for programmable gain amplifier ini Adjustment value delta 0 Make an initialization setting, Δ 0 ＝0、ε 0 ＝Δ max The iteration number i =0;
(b2) Setting the actual gain of the programmable gain amplifier to g i+1 ＝g ini +Δ i Waiting for the validation;
(b3) Calculating an average amplitude value of a signal
Figure FDA00038082947000000219
M 1 For the number of samples used to calculate the average signal amplitude value, v lt+ Represents the first (t +l) Absolute amplitude of the digital AGC output signal at the moment;
(b4) If v is avg ＜Th 1 Then a is i+1 ＝Δ i +ε i ；
If v is avg ≥Th 1 Then a is i+1 ＝Δ i -ε i ；
(b5)
Figure FDA0003808294700000031
Judging whether a circulation condition is satisfied, wherein the circulation condition is as follows: epsilon i+1 If the loop condition is satisfied, i = i +1, and the steps (b 2) to (b 5) are continuously executed in an iteration mode; if the loop condition is not satisfied, the digital AGC adjustment is finished.
4. A module for processing a digital baseband signal of a hundred mega ethernet according to any one of claims 1 to 3, comprising a sampling amplifying unit, a decision feedback equalizing unit and a CDR phase tracking unit; the input end of the sampling amplification unit inputs a channel signal, and the output end of the sampling amplification unit is connected with the input end of the decision feedback equalization unit; the output end of the decision feedback equalization unit outputs the processed signal and is connected with the input end of the CDR phase tracking unit; the output end of the CDR phase tracking unit is connected with the sampling amplification unit; the sampling amplification unit comprises a programmable gain amplifier, an ADC sampling conversion unit, an analog AGC unit and a digital AGC unit; the input end of the programmable gain amplifier is connected with a channel signal, the output end of the programmable gain amplifier is connected with the ADC sampling conversion unit, the output end of the ADC sampling conversion unit is connected with the digital AGC unit and the analog AGC unit, the output end of the analog AGC unit is connected with the programmable gain amplifier, and the output end of the digital AGC unit is connected with the decision feedback equalization unit.
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