CN114696959A - Viterbi decoder for 4D-PAM5 trellis coding modulation - Google Patents
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- 238000012546 transfer Methods 0.000 claims abstract description 5
- 238000010586 diagram Methods 0.000 claims description 19
- 230000007704 transition Effects 0.000 claims description 6
- 230000008569 process Effects 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 238000012937 correction Methods 0.000 description 3
- 230000004083 survival effect Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
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- 238000007476 Maximum Likelihood Methods 0.000 description 1
- SIHKVAXULDBIIY-OWOJBTEDSA-N [(e)-4-(2-bromoacetyl)oxybut-2-enyl] 2-bromoacetate Chemical compound BrCC(=O)OC\C=C\COC(=O)CBr SIHKVAXULDBIIY-OWOJBTEDSA-N 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
- H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0059—Convolutional codes
- H04L1/006—Trellis-coded modulation
Abstract
The invention discloses a Viterbi decoding method and a Viterbi decoding device which can be used for carrying out decoding operation on Trellis Coded Modulation (TCM). The device is divided into four functional units, and the branch metric calculation unit calculates each branch metric in the grid graph and correspondingly decodes the parallel transfer result generated by the grid coding modulation, so that the grid coding modulation can be decoded. The addition-ratio-selection unit adopts a structure that the addition operation and the ratio operation are carried out in parallel, so that the decoding speed of the decoder is improved. The survivor path selection unit is used for comparing the path metrics corresponding to each state node at the current moment, and the comparison result is used for judging a backtracking starting point when the path storage backtracking unit performs backtracking operation. The path storage backtracking unit adopts a one-input-multiple-output backtracking (Trace Back) structure, so that the decoding speed is ensured, and the system connection structure is simplified.
Description
Technical Field
The invention relates to a Viterbi (Viterbi) decoding technology, in particular to a Viterbi decoding method and a Viterbi decoding device which can be applied to a 4D-PAM5 Trellis Coded Modulation (TCM) technology in the communication field.
Background
In digital communication systems, the traditional approach of designing the coding and modulation separately cannot coordinate the balance between bandwidth and power. In order to find a way to save both power and bandwidth, trellis coded modulation techniques have been developed that combine error correction coding and modulation.
The trellis coded modulation technique combines coding and modulation together, increases the distance between codeword sequences, and does not reduce the utilization rate of frequency bands or the power utilization rate but replaces the complexity of equipment with coding gain. Nowadays, trellis coded modulation has been largely applied to communication systems with limited frequency band and power, such as satellite, microwave, coaxial, twisted pair, etc. communication, and occupies a dominant position.
The idea of trellis coded modulation is to combine the error correction coding technique and the modulation technique together for design, and to divide the point set of the signal by expanding the point set of the signal, so that the euclidean distance of the signal in each signal point set is increased.
The error correction coding technique in trellis coded modulation usually uses convolutional coding, and for convolutional coding with small constraint length, the viterbi decoding algorithm of maximum likelihood decoding is usually adopted.
There are two metrics to be considered in viterbi decoding of convolutional codes, Branch Metric (BM) and Path Metric (PM), respectively. Where the branch metrics are used to represent the "distance" between the input value and the decoded output prediction value on each branch path in the trellis. The path metric is related to the whole path formed by the branch paths in the trellis diagram, and corresponds to the distance between the most probable path from the initial state to the current state in the trellis and the received bit sequence. "most likely" refers to the one that takes the smallest distance after all possible path metrics from the initial state to the current state are computed.
The process of decoding a convolutional code using the viterbi algorithm can be mainly divided into the following two specific steps: firstly, the branch metrics between branches corresponding to the input value at the current moment are calculated, and then the path metrics corresponding to the input states of each branch metric are accumulated to obtain the path metric at the current moment. The computation of the path metric can be considered as an "add-compare" process:
(1) the branch metric is added to the path metric for the last time state.
(2) Each state compares all paths that reach that state.
(3) Each state deletes the remaining arriving paths, preserving the path with the smallest metric (called the survivor path), which corresponds to the path with the least errors.
A conventional viterbi decoder is generally composed of three parts: a Branch metric calculation Unit (BMU); an Add-Compare-Select Unit (ACSU); survivor Path Memory Unit (SPMU).
Wherein the branch metric calculation unit is used for calculating branch metrics of all branch paths;
the adding-comparing-selecting unit selects the path with the minimum measurement according to the adding-comparing-selecting process
The survival path storage unit is used for storing the path information obtained by the addition-ratio-selection unit so as to carry out decoding output.
The invention is based on the Viterbi decoding algorithm for decoding the convolutional code, improves the Viterbi decoder to enable the Viterbi decoder to decode the trellis coded modulation, optimizes the traditional ACS unit to improve the decoding speed, adopts a one-input-multiple-output backtracking structure in the SPM unit, simplifies the system connection structure and ensures the decoding speed.
Disclosure of Invention
The invention provides an improvement method for a traditional Viterbi decoding method and a decoder, which can decode trellis coded modulation by adding a decoding decision function in a branch metric calculation unit and storing a decoding decision result.
The invention provides an optimization method of an addition-comparison selection unit of a traditional Viterbi decoder, which carries out addition operation and comparison operation in parallel so as to improve the decoding speed.
The invention provides a backtracking decoding method, which adopts a one-input-multiple-output structure, can ensure that decoding output exists in each period in the backtracking process, overcomes backtracking delay caused by the traditional backtracking structure, and ensures the decoding speed.
The embodiment of the invention provides a Viterbi decoding method and a Viterbi decoding device for 4D-PAM5 trellis coded modulation, which can improve the decoding speed and simplify the structure of a backtracking part.
The embodiment of the invention provides a Viterbi decoder device, which can decode 4D-PAM5 trellis coded modulation and comprises the following four parts: the device comprises a branch metric calculating unit, an adding-comparing-selecting unit, a survival path selecting unit and a path storage backtracking unit.
The embodiment of the invention provides a branch metric calculation unit which can simultaneously decode parallel transition in a Viterbi decoder, and the branch metric calculation unit can simultaneously decode symbols in a corresponding subset.
The embodiment of the invention provides an addition and comparison menu unit for performing addition operation and comparison operation in parallel, which has the specific implementation mode that:
in the embodiment of the invention, 8 state nodes are corresponded, and each state node has 4 input branch paths. The "add" operation is to add each branch metric to the path metric of the state node that output the branch at the previous time, and the "ratio" operation is to determine the sign of [ (path metric a + branch metric a) - (path metric b + branch metric b) ] to determine the magnitude relationship between the two path metrics.
In this embodiment, a "one-input three-output" structure is used, that is, path transfer information and a decoding decision result corresponding to a group of state nodes are written in each cycle, state nodes with three depths are traced back, that is, the trace back depth in four cycles is 12, 4 decoding output results are output at the same time, it can be ensured that the trace back outputs 4 decoding depths in every four cycles when tracing back is started, and it can be ensured that there is one decoding output in each cycle when serial output is performed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below.
FIG. 1 is a diagram of trellis coded modulation technique
FIG. 2 is a diagram of a 4D-PAM5 trellis-coded modulation structure
Convolutional code state trellis diagram in FIG. 34D-PAM 5
FIG. 4 is a schematic diagram of a Viterbi decoder according to an embodiment of the invention
FIG. 5 is a block diagram of a branch metric calculation unit
FIG. 6 is a block diagram of an add-compare-select unit
FIG. 7 is a block diagram of a path memory trace unit
FIG. 8 is a diagram showing the correspondence between write addresses and read addresses
FIG. 9 is a diagram of a path and decode bit register structure
Detailed Description
In order to more clearly illustrate the objects, technical solutions and advantages of the present invention, embodiments of the present invention are described in more detail below with reference to the accompanying drawings. The invention should not be construed as being limited to the 4D-PAM5 trellis coded modulation technique used in this embodiment. Wherein the improvements to the viterbi decoder are applicable to other applications using viterbi decoding algorithms.
Referring to fig. 1, a general structure diagram of a trellis-coded modulation encoder, first, input k-bit information is divided into k1 bits and k2 bits; the k1 bits are passed through an (n, k1, m) convolutional code encoder to produce an n-bit output for selecting one of the 2n subsets of the signal constellation after diversity, and the other k2 bits are used to select signal points in each subset. This means that the constellation is divided into 2n subsets, each subset containing 2k2 signal points. When k2 is 0, all m information bits participate in the encoding.
Referring to fig. 2, a general structure diagram of a 4D-PAM5 trellis coded modulation encoder, it can be seen that 2 bits of input 8-bit data are passed through an 8-state feedback convolutional code encoder, and output 3-bit data is used for selection of subsets, and 6 bits are used for selection of symbols in each subset.
The correspondence relationship between the subsets in the 4D-PAM5 can be seen in the following table, where a denotes odd subset symbols { -1, 1} in 5-level symbols, and B denotes even subset symbols { -2, 0, 2} in 5-level symbols, and the correspondence relationship between the convolutionally encoded 3 bits and the four-dimensional subsets is shown in table 1 below.
TABLE 1
| Four-dimensional subsets | Symbol group within subset | 3bit |
| D0 | AAAA BBBB | 000 |
| D1 | AAAB BBBA | 001 |
| D2 | AABB BBAA | 010 |
| D3 | AABA BBAB | 011 |
| D4 | ABBA BAAB | 100 |
| D5 | ABBB BAAA | 101 |
| D6 | ABAB BABA | 110 |
| D7 | ABAA BABB | 111 |
Referring to fig. 3, which is a trellis diagram of the convolutional code encoder of fig. 2, it can be seen that for 8 states of the convolutional code, each state has 4 input branch paths and also has 4 output branch paths.
Referring to fig. 4, an embodiment of the present invention provides a viterbi decoder apparatus, which can decode 4D-PAM5 trellis-coded modulation, including the following four parts: the device comprises a branch metric calculation unit (401), an addition-comparison-selection unit (402), a survival path selection unit (403) and a path storage backtracking unit (404).
The structure of the branch metric calculation unit in this embodiment is shown in fig. 5, and is composed of 4 one-dimensional error calculation modules (501), 8 four-dimensional error calculation modules (502), and 8 decision decoding modules (503).
Each one-dimensional error calculation module corresponds to a pair of soft decision one-dimensional inputs, the one-dimensional errors and symbols generated by the 4 one-dimensional error calculation modules are respectively input into the four-dimensional error calculation module and the decoding decision module, and the minimum branch metrics corresponding to 8 states and corresponding decoding results are finally output through calculation and comparison. The specific implementation scheme is as follows:
the judgment of the A subset symbol and the B subset symbol which are closest to each one-dimensional symbol soft decision result and the distance error between the closest symbols are firstly realized in a one-dimensional decision device.
The symbol distances calculated in the one-dimensional decision device are combined into four-dimensional errors, the branch distance from the received symbol to each subset is calculated, and the sub-subset with the minimum four-dimensional error is judged.
The decision decoder performs decision decoding on 64 parallel transition paths existing in each state transition in the 4D-PAM5 trellis-coded modulation state diagram. The specific process is as follows:
4 groups of symbol values output by the one-dimensional decision device form 16 sub-set four-dimensional symbol groups corresponding to 8 4-dimensional sub-sets, each symbol group is decoded, and simultaneously, decoding decision output is selected according to a sub-set selection result obtained by the four-dimensional error calculation module.
The embodiment of the invention adopts a full parallel addition comparison and selection structure, namely, a single ACS unit is used corresponding to 8 state nodes. The operation sequence of the conventional add-compare-select unit is:
adding branch metrics corresponding to each state output in the trellis to the path metrics;
comparing the path metric values obtained after the addition;
and selecting one with the smallest path metric corresponding to all the branches reaching each state node as a surviving branch path corresponding to the state node.
The invention optimizes the traditional addition-ratio-selection unit, carries out the addition operation and the selection operation in parallel, does not operate in the sequence of addition, ratio and selection, and can improve the processing speed of the ACS unit.
Fig. 6 shows an ACS unit structure diagram corresponding to one state node. Each ACS unit of the embodiment of the invention is divided into 6 functional modules:
the path metric accumulator (601) implements an "add" operation that adds the path metrics prior to the branch metric corresponding to each state for subsequent comparison and selection operations.
The path metric comparator (602) and branch selector (603) together implement a "ratio" operation.
Referring to the state transition trellis diagram of FIG. 3, there are 4 input paths for each state, so the path metric comparators of the first stage are common to the ACS unit of each state node
Each path metric comparator compares the path metric by judging [ (path metric a + branch metric a) - (path metric b + branch metric b)]To determine the magnitude relation between two path metricsIs described.
Then, the judgment results of the 6 path metric comparators are input into the branch selector, and the branch selector performs sorting comparison by using the output results of the four path metric comparators, and selects a path with the minimum path metric.
The path metric selector (604) in the embodiment of the invention uses the output result of the branch selector to select and output the output results of the four path metric accumulators.
The decoding output selector (605) selects and outputs the path information corresponding to the four branches and the mapping decoding result by using the output result of the branch selector in the embodiment of the invention.
In the embodiment of the present invention, the survivor path selecting unit is configured to compare the path metrics corresponding to the 8 state nodes at the current time to select the state node corresponding to the path with the minimum path metric, and the comparison result is used for determining the backtracking start point when the path storage backtracking unit performs the backtracking operation.
The embodiment of the present invention selects the decoding depth to be 12, and at the same time, unlike the general design of outputting one set of data, the embodiment of the present invention selects four sets of data to be output during each trace back, so the required registers are 12+4 sets, and there are 16 sets of registers for each state.
For each set of registers, two parts are possible, one for holding decoded data: the other part is used for saving the state at the last moment, namely the transfer information of the path.
Referring to fig. 7, the structure diagram of the path storage backtracking unit in the embodiment of the present invention is composed of three functional modules: a store and trace control module (701), a path and decode bit register (702), and a trace and output module (703).
The store and trace control module is used for generating control signals for the register, namely, addresses of the write register and addresses of the read register. The embodiment of the invention adopts a structure that one port writes data and three ports read data, so that the addresses required to be generated comprise:
write address signals for writing to the register: write _ pointer;
three read address signals for the information in the register being read: pointer _ a; pointer _ b; pointer _ c;
the write address and read address correspondence at each time is shown in fig. 8.
For the embodiment of the present invention, the trace back output operation is performed when the write addresses are 3, 7, 11, and 15, and since a state node with 3 depths is traced back in each cycle, three read address signals trace back 3 depths in each cycle, that is, at the next time:
pointer_a＝pointer_a-3；
pointer_b＝pointer_b-3；
pointer_c＝pointer_c-3；
path and decode bit register structure diagram referring to fig. 9, it is composed of 8 sub-modules, each sub-module corresponds to a state, for each state it is composed of 16 groups of registers, each group of registers records decoded data and path transfer information.
In the embodiment of the invention, the backtracking and output module backtracks and outputs the decoding data stored in the path and decoding bit register at the output moment by using the decision signal generated by the survivor path selection unit. The specific implementation scheme is as follows:
the data output selection is performed every four clock cycles, for example, when the write address is 15, the corresponding decoded data in the 0123 th group of registers is output, when the write address is 3, the corresponding decoded data in the 4567 th group of registers is output, when the write address is 7, the corresponding decoded data in the 891011 th group of registers is output, and when the write address is 11, the corresponding decoded data in the 12131415 th group of registers is output.
Claims (7)
1. A viterbi decoder for trellis coded modulation comprising:
the branch metric calculating unit calculates each branch metric in the grid graph and correspondingly decodes the parallel transfer result generated by the grid coding modulation, so that the grid coding modulation can be decoded.
And the addition-comparison-selection unit is used for increasing the decoding speed of the decoder by a structure of carrying out addition operation and comparison operation in parallel.
And the survivor path selection unit is used for comparing the path metrics corresponding to each state node at the current moment, and the comparison result is used for judging a backtracking starting point when the path storage backtracking unit performs backtracking operation.
The path storage backtracking unit adopts a one-input-multiple-output backtracking (Trace Back) structure, so that the decoding speed is ensured, and the system connection structure is simplified.
2. The arrangement as claimed in claim 1, the branch metric calculation unit being characterized in that the branch metrics are calculated while simultaneously making decoding decisions on parallel path transitions resulting from the presence of inputs not participating in the convolutional encoding during the code modulation.
3. An addition-comparison-menu element as claimed in claim 1, wherein the comparison operation is performed simultaneously with the addition operation of the branch metrics of the output branch paths corresponding to each state and the path metrics corresponding to the state, and the result of the "comparison" operation is used to select the path metric after the "addition" operation and decode the decision result.
4. According to the scheme of claim 3, the 'ratio' operation in the addition-ratio-selection unit adopts a two-stage structure, the grid graph corresponds to each state node and has n input branch paths, and the first stage is composed of
And the second stage compares the results output by the first stage comparison module to select the branch path with the minimum path metric.
5. The method of claim 2, wherein the structure of the storage module of the path memory trace-back unit corresponds to a trellis diagram structure of trellis coded modulation, and each time corresponds to a set of state inputs, and the storage contents include path transition information and decoding results.
6. The method according to claim 1, wherein the path backtracking unit adopts a one-input-multiple-output structure, thereby reducing the time delay of backtracking decoding, ensuring the decoding speed and simplifying the complexity of system connection.
7. The invention, as recited in claim 6, wherein the memory depth of the trace-back unit is l + m, where l is 5 times or more of the constraint length of the convolutional code, and m is a period required for trace-back, and is characterized in that each period performs a write operation and trace-back n state nodes at the same time, so as to ensure that l depth can be traced-back within m periods, so that m decoding results can be output in each m period, and finally, when the trace-back operation is started, one decoding result can be output in each period.
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