CN114696937A - High-precision synchronization device and synchronization method for distributed test system - Google Patents
High-precision synchronization device and synchronization method for distributed test system Download PDFInfo
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Abstract
The invention provides a high-precision synchronization device and a synchronization method for a distributed test system, wherein the synchronization device comprises a time service unit, a spread spectrum clock signal modulation unit, a passive clock signal distribution and transmission unit, a signal amplification and clock recovery unit and a portable clock calibration unit which are sequentially connected, wherein the spread spectrum clock signal modulation unit modulates time service data and a clock signal provided by the time service unit into radio frequency signals; the passive clock signal distribution and transmission unit distributes and transmits radio frequency signals to at least one signal amplification and clock recovery unit, and each signal amplification and clock recovery unit converts, amplifies and demodulates the radio frequency signals into time service data and clock signals; each signal amplification and clock recovery unit is connected with the portable clock calibration unit to calibrate the clock signal. The invention realizes the high-precision time synchronization of the distributed multi-channel signals and improves the correlation analysis capability of the multi-channel signals.
Description
Technical Field
The invention relates to a time synchronization device, in particular to a high-precision synchronization device and a synchronization method for a distributed test system.
Background
The test system, especially the integrated test system in the final assembly stage, has a large number of systems, subsystems and devices involved in the test and a large number of signal types to be tested. Taking an airplane general assembly integrated test as an example, the integrated test relates to the test of systems such as a power supply system, a fuel system, a hydraulic system, a flight control system, an avionics system, a lighting system and the like, and the interaction relationship of tested equipment is more and more complex, so that the test system develops towards a distributed architecture. On the other hand, since correlation exists among a plurality of signals of a plurality of systems, data correlation analysis is required in subsequent processing, and therefore, the requirement of synchronous testing needs to be further satisfied under a distributed architecture.
However, a complex distributed test system architecture has a certain contradiction with the synchronous acquisition of multi-channel signals, and when the acquisition equipment is located in different cases, different cabinets and even different machine rooms, in order to realize high-precision synchronous measurement of the multi-channel signals, the time synchronization precision needs to reach microsecond level or even nanosecond level.
The existing time synchronization generally falls into two categories, one is signal-based synchronization, such as synchronization of a Pulse Per Second (PPS) signal; the other is Time-based synchronization, such as Network Time Protocol (NTP), IRIG-B code, Precision Time Protocol (PTP), and the like. NTP time service precision is dozens of milliseconds to hundreds of milliseconds; the IRIG-B time service precision is in the microsecond level; the precision of PTP time service is tens to hundreds of nanoseconds, but the price is higher.
In order to realize multi-channel signal synchronization of tens of nanoseconds on the scale of hundreds of meters of indoor space, generally, a pulse signal, such as a PPS clock signal, is adopted, and a coaxial cable is used for transmitting the PPS clock signal, and the coaxial cable is required to have equal length so as to realize synchronization among multiple devices. If the length of the coaxial cable reaches hundreds of meters, the coaxial cable seriously affects the quality of transmitted signals. Experiments have shown that after transmission through a 300m coax cable, a 1PPS signal is output with a rise time measurement of 182 ns. (Zhao Zhixiong. hectometer magnitude time-frequency signal transmission and recovery method research [ D ]. institute of graduate institute of Chinese academy of sciences (national time service center), 2015.) the multi-channel distribution of pulse signals needs active pulse signal distributors, such as time mark distributors, and has certain limitation on engineering wiring.
For the existing test system, in order to improve the distributed multi-channel acquisition capability thereof, a high-precision time synchronization device and a synchronization method for an indoor distributed test system are urgently needed.
Disclosure of Invention
The invention provides a high-precision time synchronization device and a synchronization method for an indoor distributed test system, which aim to solve the problem that the high-precision time synchronization device and the synchronization method for the indoor distributed test system are needed to improve the distributed multi-channel acquisition capacity of the existing test system in the prior art, wherein the high-precision time synchronization device for the indoor distributed test system comprises a time service unit, a spread spectrum clock signal modulation unit, a passive clock signal distribution and transmission unit, a signal amplification and clock recovery unit and a portable clock calibration unit which are sequentially connected, wherein the spread spectrum clock signal modulation unit modulates time service data and clock signals provided by the time service unit into radio frequency signals; the passive clock signal distribution and transmission unit distributes and transmits radio frequency signals to at least one signal amplification and clock recovery unit, and each signal amplification and clock recovery unit converts, amplifies and demodulates the radio frequency signals into time service data and clock signals; each signal amplification and clock recovery unit is connected with the portable clock calibration unit to calibrate the clock signal. The invention realizes the high-precision time synchronization of the distributed multi-channel signals and improves the correlation analysis capability of the multi-channel signals.
The invention specifically comprises the following contents:
the invention provides a high-precision synchronization device for a distributed test system, which comprises a time service unit, a spread spectrum clock signal modulation unit, a passive clock signal distribution and transmission unit, a signal amplification and clock recovery unit and a portable clock calibration unit, wherein the time service unit is used for providing a time service for a test system;
the time service unit, the spread spectrum clock signal modulation unit and the passive clock signal distribution and transmission unit are sequentially connected;
the passive clock distribution and transmission unit is provided with a plurality of output branches, and each output branch is connected with a signal amplification and clock recovery unit and is connected with the test equipment through the signal amplification and clock recovery unit;
the portable clock calibration unit is overlapped on the signal amplification and clock recovery unit and forms a calibration feedback loop.
In order to better realize the invention, the spread spectrum clock signal modulation unit comprises a time service data input port, a data coder, a frequency spreader, a modulator, an up-conversion and amplifier and a radio frequency signal output port;
the time service data input port is connected with the time service unit;
the radio frequency signal output port is connected with the passive clock distribution and transmission unit;
the time service data input port, the data encoder, the frequency spreader, the modulator, the up-conversion amplifier and the radio frequency signal output port are sequentially connected.
In order to better implement the invention, further, the spread spectrum clock signal modulation unit further comprises a 10MHz reference frequency input port, a PPS signal input port, a clock and timing controller, and a pseudo-random sequence generator;
the 10MHz reference frequency input port and the PPS signal input port are connected with the time service unit;
the first input end of the clock and time schedule controller is connected with the output end of the 10MHz reference frequency input port, the second input end is connected with the output end of the PPS signal input port, the first output end is connected with the data encoder, the second output end is connected with the frequency spreader, and the third output end is connected with the input end of the pseudo-random sequence generator;
and the output end of the pseudo-random sequence generator is connected with the frequency spreader.
In order to better realize the invention, the signal amplification and clock recovery unit comprises a radio frequency signal input port, a down conversion and AGC amplifier, a demodulation de-spreader, a data decoder and a time service data output port which are connected in sequence;
the radio frequency signal input port is connected with the passive clock signal distribution and transmission unit;
the time service data output port is connected with the test equipment.
In order to better implement the present invention, further, the signal amplifying and clock recovering unit further includes a pseudo random sequence generator, a timing controller, a configuration port, and a PPS signal output port;
the input end of the time schedule controller is connected with the configuration port, the first output end is connected with the demodulation despreader through the pseudo-random sequence generator, and the second output end is connected with the PPS signal output port.
In order to better implement the invention, further, the data encoder comprises a time service data encoder, an encoding data buffer and a shift register which are connected in sequence;
the frequency spreader comprises an exclusive or gate XOR;
the modulator comprises a D/A controller and a dual-channel D/A converter U5 which are connected in sequence;
the up-conversion and amplifier comprises a low-pass filter FL1, a low-pass filter FL2, an integrated quadrature debugger U6, an amplifier U7 and a low-pass filter FL3 which are connected in sequence;
the low-pass filter FL1 and the low-pass filter FL2 are arranged between the dual-channel D/A converter U5 and the integrated orthogonal debugger U6 in parallel;
the time service data input port is connected with a time service data encoder;
the low pass filter FL3 is connected to the rf signal output port.
In order to better implement the present invention, further, the spread spectrum clock signal modulating unit further includes an amplifier U1, an amplifier U2, an amplifier U3;
the amplifier U1 is arranged between the time service data input port and the time service data encoder;
the amplifier U2 is arranged between the PPS signal input port and the clock and time sequence controller;
the amplifier U3 is disposed between the 10MHz reference frequency input port and the clock and timing controller.
To better implement the present invention, further, the down-conversion and AGC amplifier includes a low pass filter FL4, an amplifier U8, an integrated quadrature demodulator U9;
the data decoder comprises a configuration data decoder and a time service data decoder;
the demodulation despreader comprises a low-pass filter FL5 and a low-pass filter FL6 which are arranged in parallel, a dual-channel A/D converter U10 and an A/D acquisition synchronization module which are sequentially connected with the output ends of the low-pass filter FL5 and the low-pass filter FL6, a first multiplier and a first integrator which are sequentially connected with the first output end of the A/D acquisition synchronization module, a second multiplier and a second integrator which are sequentially connected with the second output end of the A/D acquisition synchronization module;
the low-pass filter FL4 is connected with a radio frequency signal input port;
the integrated quadrature demodulator U9 is connected to a low pass filter FL5 and a low pass filter FL 6;
one end of the time service data decoder is connected with the first integrator and the second integrator, and the other end of the time service data decoder is connected with the time service data output port;
one end of the configuration data decoder is connected with the configuration port, and the other end of the configuration data decoder is connected with the time schedule controller.
In order to better implement the invention, further, amplifiers U12 are arranged between the configuration data decoder and the configuration port and between the time service data decoder and the time service data output port;
an amplifier U13 is arranged between the time schedule controller and the PPS signal output port.
To better implement the present invention, further, the signal amplification and clock recovery unit further comprises an integrated quadrature demodulator U9 configuration module;
the integrated quadrature demodulator U9 configuration module is arranged between the integrated quadrature demodulator U9 and the time service data decoder.
In order to better implement the present invention, further, a loop tracker is disposed between the timing controller and the pseudo random sequence generator;
the first input end of the loop tracker is connected with the first integrator, the second input end of the loop tracker is connected with the second integrator, the third input end of the loop tracker is connected with the clock controller 305, the first output end of the loop tracker is connected with the integrated quadrature demodulator U9 configuration module, and the second output end of the loop tracker is connected with the time service data decoder.
Based on the above proposed high-precision synchronization apparatus for a distributed test system, in order to better implement the present invention, further, a high-precision synchronization method for a distributed test system is proposed, which includes the following steps:
step 1: collecting time service data and clock signals by using a time service unit;
step 2: modulating the time service data and the clock signal acquired by the time service unit into a radio frequency signal by using a spread spectrum clock signal modulation unit;
and step 3: distributing and transmitting the radio frequency signal modulated by the spread spectrum clock signal modulation unit to at least one signal amplification and clock recovery unit by using a passive clock signal distribution and transmission unit;
and 4, step 4: a signal amplification and clock recovery unit is used for converting, amplifying and demodulating the radio-frequency signal into time service data and a clock signal;
and 5: and feeding the clock signal of each signal amplification and clock recovery unit back to the signal amplification and clock recovery unit by using the portable clock calibration unit for calibration.
Based on the above proposed high-precision synchronization apparatus for distributed test system, in order to better implement the present invention, further, a high-precision synchronization method for distributed test system comprises the following steps:
step S1: connecting a clock input port of the portable clock calibration unit with the time service unit to acquire a PPS clock signal;
step S2: measuring the time difference DT1 between the PPS clock signal of the time service unit and the PPS clock signal of the atomic clock time-frequency standard source which are accessed simultaneously by using a clock measurement and a display, and storing the time difference DT1 in a memory;
step S3: connecting a clock input port of the portable clock calibration unit with a PPS signal output port of the signal amplification and clock recovery unit;
step S4: measuring the time difference DT2 between the PPS clock signal output by the signal amplification and clock recovery unit and the PPS clock signal of the atomic clock time-frequency standard source by using a clock measurement and a display, and storing the time difference DT2 in a memory;
step S5: taking the difference value of the time difference DT1 of the PPS clock signal and the time difference DT2 of the PPS clock signal as a calibration value DT, and storing the calibration value DT in a memory;
step S6: a timing controller connected to the configuration port through the data output port, for injecting the calibration value Dt into the signal amplifying and clock recovering unit;
step S7: the time schedule controller adjusts the output PPS clock signal to a calibration value Dt to complete the synchronization with the PPS clock signal of the time service unit.
The invention has the following beneficial effects:
(1) according to the high-precision synchronization device for the distributed test system, the spread spectrum clock signal modulation unit is used for modulating the time service data and the clock signal into the radio frequency signal, so that the clock signal is convenient to transmit indoors and high precision is kept; through a passive clock signal distribution and transmission mode, the clock signal is convenient to transmit in a complex indoor space and is convenient for integrated wiring; recovering a high-precision clock signal at a distributed remote end through a signal amplification and clock recovery unit; calibrating the distributed clock signal by a portable clock calibration unit; the distributed multi-channel simultaneous acquisition capability of the conventional test system is improved, and the multi-channel signal correlation analysis capability is improved.
(2) The invention can eliminate phase difference by sharing reference frequency, reference clock, sampling trigger signal and sampling clock based on signal synchronization, namely, the reference frequency shared by a plurality of test devices, the reference clock, the sampling trigger signal and the sampling clock can ensure the precision of sampling data time stamp, the sharing sampling trigger signal can ensure the start of multichannel sampling synchronization, and the sampling clock can ensure the updating of data at the new rising edge of the sampling clock, thereby realizing the synchronization precision of tens of nanoseconds with lower cost.
Drawings
FIG. 1 is a schematic diagram of the module connection of a high-precision time synchronizer for an indoor distributed test system according to the present invention;
FIG. 2 is a schematic diagram of a spread spectrum clock signal modulation unit module connection;
FIG. 3 is a schematic diagram of the connection of signal amplification and clock recovery unit modules;
FIG. 4 is a schematic diagram of a portable clock calibration unit module connection;
FIG. 5 is an electrical schematic diagram of a spread spectrum clock signal modulating unit;
FIG. 6 is an electrical schematic of the signal amplification and clock recovery unit;
101, a time service unit, 102, a spread spectrum clock signal modulation unit, 103, a coaxial power divider, 104, a signal amplification and clock recovery unit, 105, a portable clock calibration unit, 106, a test device, 201, a time service data input port, 202, 10MHz reference frequency input port, 203, a PPS signal input port, 204, a clock and timing controller, 205, a pseudo random sequence generator, 206, a data encoder, 207, a spreader, 208, a modulator, 209, an up-conversion and amplifier, 210, a radio frequency signal output port, 301, a radio frequency signal input port, 302, a down-conversion and AGC amplifier, 303, a demodulation despreader, 304, a pseudo random sequence generator, 305, a timing controller, 306, a data decoder, 307, a configuration port, 308, a PPS signal output port, 309, and a time service data output port.
Detailed Description
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments, and therefore should not be considered as a limitation to the scope of protection. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example 1:
the present embodiment proposes a high-precision synchronization apparatus for a distributed test system, as shown in fig. 1, which includes a time service unit 101, a spread spectrum clock signal modulation unit 102, a passive clock signal distribution and transmission unit, a signal amplification and clock recovery unit 104, and a portable clock calibration unit 105;
the time service unit 101, the spread spectrum clock signal modulation unit 102, the passive clock signal distribution and transmission unit, the signal amplification and clock recovery unit 104, and the portable clock calibration unit 105 are connected in sequence.
The working principle is as follows: the embodiment provides a high-precision synchronization device for a distributed test system, which comprises a time service unit 101, a spread spectrum clock signal modulation unit 102, a passive clock signal distribution and transmission unit, a signal amplification and clock recovery unit 104 and a portable clock calibration unit 105, which are connected in sequence, wherein the spread spectrum clock signal modulation unit 102 modulates time service data and clock signals provided by the time service unit 101 into radio frequency signals; the passive clock signal distribution and transmission unit distributes and transmits the radio frequency signal to at least one signal amplification and clock recovery unit 104, and each signal amplification and clock recovery unit 104 converts, amplifies and demodulates the transmitted and attenuated radio frequency signal into time service data and a clock signal; each signal amplifying and clock recovering unit 104 is connected to a portable clock calibrating unit 105 for calibrating the clock signal; the signal amplification and clock recovery unit 104 is coupled to the test equipment 106 to provide a calibrated clock signal and timing data.
Example 2:
in this embodiment, on the basis of embodiment 1, as shown in fig. 2, the spread spectrum clock signal modulation unit 102 includes a timing data input port 201, a 10MHz reference frequency input port 202, a PPS signal input port 203, a clock and timing controller 204, a pseudo random sequence generator 205, a data encoder 206, a spreader 207, a modulator 208, an up-converter and amplifier 209, and a radio frequency signal output port 210;
the time service data input port 201, the 10MHz reference frequency input port 202 and the PPS signal input port 203 are connected with the time service unit 101;
the radio frequency signal output port 210 is connected with a passive clock signal distribution and transmission unit;
the output end of the time service data input port 201 is connected with the first input end of the data encoder 206; a first output end of the 10MHz reference frequency input port 202 is connected to a first input end of the clock and timing controller 204, and a second output end is connected to a first input end of the modulator 208;
the output end of the PPS signal input port 203 is connected with a second input end of the clock and timing controller 204;
a first output end of the clock and timing controller 204 is connected with a second input end of the data encoder 206, a second output end is connected with an input end of the pseudo-random sequence generator 205, and a third output end is connected with a first input end of the frequency spreader 207;
an output terminal of the pseudo random sequence generator 205 is connected to a second input terminal of the spreader 207;
an output terminal of the data encoder 206 is connected to a third input terminal of the spreader 207;
the output of the spreader is connected to a second input of the modulator 208;
the up-conversion and amplifier 209 has an input connected to the output of the modulator 208 and an output connected to the input of the radio frequency signal output port 210.
The working principle is as follows: referring to fig. 2, in the high-precision time synchronizer for an indoor distributed test system according to the embodiment of the present invention, a spread spectrum clock signal modulation unit 102 includes a timing data input port 201, a 10MHz reference frequency input port 202, a PPS signal input port 203, a clock and timing controller 204, a pseudo random sequence generator 205, a data encoder 206, a spreader 207, a modulator 208, an up-converter and amplifier 209, and a radio frequency signal output port 210.
The time service data input port 201 receives time service data from the time service unit 101, wherein the time service data comprises time, minutes and seconds; the time service data input port 201 can be, but is not limited to, an RS-232 interface, an RS-422 interface, and an Ethernet interface. The 10MHz reference frequency input port 202 receives a 10MHz reference frequency radio frequency signal from the time service unit 101; the PPS signal input port 203 receives a PPS clock signal from the time service unit 101, wherein the PPS clock signal is a clock pulse signal, and the rising edge of the clock pulse signal is aligned with the second; the time service unit 101 is universal, the PPS clock signal output precision of the time service unit 101 determines the time precision of the system, the resolution is nanosecond, and the error is within tens of nanoseconds.
The time service data input port 201 is connected with the data encoder 206, the frequency spreader 207, the modulator 208, the up-conversion and amplifier 209 and the radio frequency signal output port 210 in sequence; the data encoder 206, the spreader 207, and the modulator 208 encode, spread, and modulate the timing data into an intermediate frequency signal, the up-converter and amplifier 209 converts the intermediate frequency signal into a radio frequency signal and amplifies the radio frequency signal, and the radio frequency signal output port 210 outputs the radio frequency signal to the coaxial cable via the coaxial power divider 103.
Specifically, the 10MHz reference frequency input port 202 is connected to the clock and timing controller 204 and the modulator 208, and provides the clock and timing controller 204 and the modulator 208 with a 10MHz reference frequency;
the PPS signal input port 203 is connected to a clock and timing controller 204, and the clock and timing controller 204 is connected to a data encoder 206, a spreader 207, and a pseudo random sequence transmitter 205; the pseudo-random sequence transmitter 205 is connected to a spreader 207;
the clock and timing controller 204 performs frequency division and timing control, and the clock and timing controller 204 supplies a clock signal and a control signal to the data encoder 206 and the pseudo random sequence transmitter 205; the clock and timing controller 204 is a logic circuit, and can perform frequency division and timing control by using an FPGA, the clock and timing controller 204 controls the alignment of the first bit of data after being encoded by the data encoder 206 with the rising edge of the PPS clock signal, the clock and timing controller 204 provides the data encoder 206 with a clock signal with a 250Hz data rate, and the clock signal with the 250Hz data rate is obtained by the clock and timing controller 204 by frequency division from a 10MHz reference frequency.
The pseudo-random sequence generator 205 outputs a pseudo-random sequence to the spreader 207, and the clock and timing controller 204 provides a clock signal and controls the alignment of the revelation position of the epoch of the pseudo-random sequence, i.e., the 1 st bit, with the rising edge of the PPS clock signal; the pseudo-random sequence is clocked from a 10MHz reference frequency.
The spreader 207 performs an exclusive or operation on the data output by the data encoder 206 based on the pseudo-random sequence to generate a direct sequence spread spectrum baseband signal; the modulator 208 modulates the baseband signal, which may be BPSK modulation; the up-conversion and amplifier 209 up-converts the modulated signal to a radio frequency signal of a carrier frequency, performs power amplification, and outputs the radio frequency signal to the radio frequency signal output port 210.
Other parts of this embodiment are the same as those of embodiment 1, and thus are not described again.
Example 3:
in this embodiment, on the basis of any of the above embodiments 1-2, as shown in fig. 3, the signal amplifying and clock recovering unit 104 includes a radio frequency signal input port 301, a down-conversion and AGC amplifier 302, a demodulation despreader 303, a data decoder 306, a pseudo random sequence generator 304, a timing controller 305, a configuration port 307, a PPS signal output port 308, and a timing data output port 309;
the radio frequency signal input port 301 is connected with a passive clock signal distribution and transmission unit;
the configuration port 307, the PPS signal output port 308 and the time service data output port 309 are connected with the portable clock calibration unit 105;
a first input end of the demodulation despreader 303 is connected with a radio frequency signal input port 301, a down-conversion and AGC amplifier 302 which are sequentially connected, a second input end of the demodulation despreader 303 is connected with a configuration port 307, a time schedule controller 305 and a pseudorandom sequence generator 304 which are sequentially connected, and an output end of the demodulation despreader 303 is connected with a data decoder 306 and a time service data output port 309 which are sequentially connected;
the PPS signal output port 308 is connected to an output terminal of the timing controller 305.
The working principle is as follows: in the high-precision time synchronization device for an indoor distributed test system according to the embodiment of the present invention, the signal amplification and clock recovery unit 104 includes a radio frequency signal input port 301, a down-conversion and AGC amplifier 302, a demodulation despreader 303, a data decoder 306, a pseudorandom sequence generator 304, a timing controller 305, a configuration port 307, a PPS signal output port 308, and a timing data output port 309; the demodulation despreader 303 is an electronic component that can demodulate and despread.
The radio frequency signal input port 301 is connected with a down-conversion and AGC amplifier 302, a demodulation despreader 303, a data decoder 306 and a time service data output port 309 in sequence; the radio frequency signal input port 301 is connected to the passive clock signal distribution and transmission unit to input the attenuated radio frequency signal; the down-conversion and AGC amplifier 302 converts the radio frequency signal to an intermediate frequency signal and amplifies it; the demodulation despreader 303, the data decoder 306, and the pseudo-random sequence generator 304 demodulate, despread, and decode the intermediate frequency signal to recover the PPS clock signal and the time-service data.
Specifically, the demodulation despreader 303 despreads and decodes the intermediate frequency signal; the data decoder 306 receives the despread and decoded data and restores the despread and decoded data into time service data, and outputs the time service data through a time service data output port 309;
the timing controller 305 is connected to the demodulation despreader 303 through a pseudo-random sequence generator 304, the pseudo-random sequence generator 304 generating a pseudo-random sequence in conformity with the spread spectrum clock signal modulation unit 102; the timing controller 305 controls the digitally controlled oscillator, and recovers the PPS clock signal by using the correlation peak despread by the demodulation despreader 303 as the rising edge of the PPS clock signal, and outputs the PPS clock signal through the PPS signal output port 308.
The timing controller 305 is connected to a configuration port 307, and the timing controller 305 is connected to the portable clock calibration unit 105 through the configuration port 307 to calibrate and adjust the phase of the PPS clock signal, and to adjust the lead and lag of the PPS clock signal output from the signal amplification and clock recovery unit 104.
Other parts of this embodiment are the same as any of embodiments 1-2 described above, and thus are not described again.
Example 4:
this embodiment is based on any of embodiments 1 to 3, and as shown in fig. 1, the passive clock signal distribution and transmission unit includes a coaxial power divider 103 and a coaxial cable;
the input end of the coaxial power divider 103 is connected with the spread spectrum clock signal modulation unit, and the output end is connected with the signal amplification and clock recovery unit through a coaxial cable.
The working principle is as follows: the passive clock signal distribution and transmission unit includes a plurality of coaxial power dividers 103 and coaxial cables, where the plurality of coaxial power dividers 103 distribute the radio frequency signals into multiple paths and transmit the multiple paths to the signal amplification and clock recovery units 104 arranged in each part of the distributed test system through the coaxial cables. The radio frequency signal is transmitted through a radio frequency coaxial cable, and is subjected to signal shunting through the coaxial power divider 103, so that one path is divided into multiple paths, and the requirement of clock synchronization of various distributed devices is met. The coaxial power divider 103 is a passive device, and the integrated wiring is convenient.
In one embodiment, the total length of transmission of the most distal coaxial cable is 300m and passes through 3 1/4 coaxial power splitters 103. The coaxial cable adopts a solid polyethylene insulated radio frequency cable, the attenuation of 1.15GHz per 100 m is 16.8dB, and the attenuation of 300m is 50.4 dB. The loss of the 1-to-4 coaxial power divider 103 is 12dB, and the total loss of 3 coaxial power dividers is 36 dB.
Other parts of this embodiment are the same as any of embodiments 1 to 3, and thus are not described again.
Example 5:
this embodiment is based on any of the above embodiments 1 to 4, and as shown in fig. 4, the portable clock calibration unit 105 includes a clock input port 401, an atomic clock time-frequency standard source 402, a clock measurement and display 403, a memory 404, and a data output port 405;
the clock input port 401 is connected with the PPS signal output port 308;
the data output port 405 is connected with a configuration port 307;
a first input of the clock measurement and display 403 is connected to an output of the clock input port 401, a second input is connected to an output of the atomic clock time-frequency standard source 402, a first output is connected to an input of the memory 404, and a second output is connected to an input of the data output port 405.
The working principle is as follows: in the high-precision time synchronization device for an indoor distributed test system of the embodiment of the present invention, the portable clock calibration unit 105 includes a clock input port 401, an atomic clock time-frequency standard source 402, a clock measurement and display 403, a memory 404 and a data output port 405, and the atomic clock time-frequency standard source 402 outputs a standard PPS signal; the clock input port 401 and the atomic clock time-frequency standard source 402 are both connected to a clock measurement and display 403; the clock measurement and display 403 measures the time difference between the clock input port 401 and two paths of PPS clock signals accessed by the atomic clock time-frequency standard source 402; a memory 404 is connected to the clock measurement and display 403. The clock measurement and display 403 is connected to a data output port 405, and is connected to a configuration port 307 of the signal amplification and clock recovery unit 104 through the data output port 405, so as to calibrate the PPS clock signal output by the signal amplification and clock recovery unit 104, and adjust the PPS clock signal output by the signal amplification and clock recovery unit 104 to be consistent with the time service unit 101. The atomic clock time-frequency standard source 402 outputs a high stability PPS clock signal that needs to be preheated.
Other parts of this embodiment are the same as any of embodiments 1 to 4, and thus are not described again.
Example 6:
in this embodiment, on the basis of any one of the foregoing embodiments 1 to 5, as shown in fig. 5, the data encoder 206 includes a time service data encoder, an encoded data buffer, and a shift register, which are connected in sequence;
the spreader 207 comprises an exclusive or gate XOR;
the modulator 208 comprises a D/A controller and a dual-channel D/A converter U5 which are connected in sequence;
the up-conversion and amplifier 209 comprises a low-pass filter FL1, a low-pass filter FL2, an integrated quadrature debugger U6, an amplifier U7 and a low-pass filter FL3 which are connected in sequence;
the low-pass filter FL1 and the low-pass filter FL2 are arranged between the dual-channel D/A converter U5 and the integrated orthogonal debugger U6 in parallel;
the time service data input port 201 is connected with a time service data encoder;
the low pass filter FL3 is connected to the rf signal output port 210.
The spread spectrum clock signal modulating unit 102 further comprises an amplifier U1, an amplifier U2, an amplifier U3;
the amplifier U1 is arranged between the time service data input port 201 and the time service data encoder;
the amplifier U2 is disposed between the PPS signal input port 203 and the clock and timing controller 204;
the amplifier U3 is disposed between the 10MHz reference frequency input port 202 and the clock and timing controller 204.
The working principle is as follows: the time service unit 101 outputs a 1PPS clock signal, a 10MHz reference frequency and GNSS time service data by adopting GNSS time service and a tamed rubidium atomic clock, wherein the PPS clock signal is synchronous with UTC standard time. The signal is input from the XS1 connector. GNSS time service data are RS-232 levels, and are transmitted to a U4 FPGA for processing after being converted into TTL levels through U1 RS-232 level conversion signals; the PPS clock signal is sent to U4 for processing after passing through a U2 TTL driver; the 10MHz reference frequency is shaped by a U3 buffer and then sent to U4 for processing. Data synchronization, spread spectrum coding is implemented in U4. The time service data encoder encodes GNSS time service data, stores a data encoding buffer, outputs an encoding data rate of 500bps by the shift register under the control of the initial pulse and the shift clock, and sends the encoding data to the XOR circuit. The pseudo-random sequence generator generates a PN sequence with a rate of 10.23 Mbps, a sequence length of 4092, 2500 cycles of one epoch, 10,230,000 bits, and a time length of 1000 ms. And the PN sequence is sent to an exclusive OR circuit. The exclusive-or circuit outputs a direct sequence spread spectrum baseband signal, the direct sequence spread spectrum baseband signal is sent to a D/A controller and a U5 dual-channel D/A converter, and 1/Q two paths of intermediate frequency modulation signals are output, wherein the modulation mode is BPSK. The intermediate frequency modulation signal passes through FL1, FL2 low pass filter, and U6 integrated quadrature debugger, U6 built-in frequency synthesizer and quadrature mixer, outputs radio frequency signal, and sends to XS2 connector. The center frequency of the radio frequency signal is 1.15GHz, and the output signal power is 1 mW, namely 0 dBm; the maximum output power can be adjusted to 10mW, i.e. 10 dBm. Other L-band center frequencies and signal powers may also be used.
Other parts of this embodiment are the same as any of embodiments 1 to 5, and thus are not described again.
Example 7:
this embodiment is based on any of the above embodiments 1-6, and as shown in fig. 6, the down-conversion and AGC amplifier 302 includes a low pass filter FL4, an amplifier U8, and an integrated quadrature demodulator U9 connected in series;
the data decoder 306 comprises a configuration data decoder and a time service data decoder;
the demodulation despreader 303 comprises a low-pass filter FL5 and a low-pass filter FL6 which are arranged in parallel, a dual-channel A/D converter U10 and an A/D acquisition synchronization module which are sequentially connected with the output ends of the low-pass filter FL5 and the low-pass filter FL6, a first multiplier and a first integrator which are sequentially connected with the first output end of the A/D acquisition synchronization module, a second multiplier and a second integrator which are sequentially connected with the second output end of the A/D acquisition synchronization module;
the low-pass filter FL4 is connected to the rf signal input port 301;
the integrated quadrature demodulator U9 is connected to a low pass filter FL5 and a low pass filter FL 6;
one end of the time service data decoder is connected with the first integrator and the second integrator, and the other end of the time service data decoder is connected with the time service data output port 309;
the configuration data decoder is connected to a configuration port 307 at one end and to a timing controller 305 at the other end.
In order to better implement the present invention, further, amplifiers U12 are disposed between the configuration data decoder and the configuration port 307, and between the time service data decoder and the time service data output port;
an amplifier U13 is arranged between the timing controller 305 and the PPS signal output port.
To better implement the present invention, further, the signal amplification and clock recovery unit 104 further includes an integrated quadrature demodulator U9 configuration module;
the integrated quadrature demodulator U9 configuration module is arranged between the integrated quadrature demodulator U9 and the time service data decoder.
Further, a loop tracker is disposed between the timing controller 305 and the pseudo random sequence generator 304;
the first input end of the loop tracker is connected with the first integrator, the second input end of the loop tracker is connected with the second integrator, the third input end of the loop tracker is connected with the clock controller 305, the first output end of the loop tracker is connected with the integrated quadrature demodulator U9 configuration module, and the second output end of the loop tracker is connected with the time service data decoder.
The working principle is as follows: the XS2 connector is connected with a radio frequency signal, the radio frequency signal is filtered by FL1, the U2j integrated quadrature demodulator realizes functions of I/Q two-path down-conversion and AGC amplifier, two paths of I/Q zero intermediate frequency signals converted by the radio frequency signal are filtered by FL2 and FL2, and the signals are sampled by a U3 two-path A/D converter. The U2 configuration module of the U4 FPGA controls the AGC and carrier frequency of the U2. So that the level needs to meet the sampling requirement of the A/D converter and the peak-to-peak value is 1V. The U4 FPGA synchronizes A/D acquisition, and de-spreads and decodes I/Q signals through a multiplier, an integrator, a pseudorandom sequence generator, a loop tracker and the like, wherein the de-spread adopts a universal advance (E), prompt (P) and lag (L) capturing mode, and a universal carrier tracking loop and a code tracking loop are sampled, so that the precise tracking of a pseudorandom sequence is realized. Because the signal-to-noise ratio is higher, after the carrier loop smoothing processing is adopted, the measurement error of a tracking loop of the pseudo-random sequence code is 0.01 chip; the pseudo-random sequence generator uses a pseudo-random sequence consistent with the spread spectrum clock signal modulation unit 102, the code rate is 10.23 Mbps, and the length of the sequence is 4092.
The recovered PPS clock signal accuracy depends on the measurement error of the pseudorandom sequence code tracking loop. In this embodiment, the farthest transmission loss is 86.4dB and the signal strength is-86.4 dBm.
The noise at the receiving end is: n = -174 + 10log (BW) + NF
Wherein-174 is the product of the ambient temperature and the boltzmann constant when the ambient temperature is 290K of the standard room temperature; BW is the bandwidth with unit of Hz, and the signal bandwidth is 20 MHz; NF is the noise coefficient of the receiving end, which is 2 dB.
Therefore, the noise is-99 dBm, and the far-end pre-despreading signal-to-noise ratio (S/N) is 12.6.
Consider a spreading gain of 10log (4092) = 36.1 dB
Considering again the processing loss, the signal-to-noise ratio after despreading is about 48.
Due to higher signal-to-noise ratio and no interference signal, after the carrier loop smoothing processing is adopted, the measurement error of the pseudo-random sequence code tracking loop is 0.01 chip, namely: 1/10M 0.01 = 1ns
The PPS signal output by the signal amplification and clock recovery unit, i.e., the clock/timing generator of U4, may meet system accuracy requirements. After the signal is sent to a U6 TTL driver, the output of an XS1 connector is connected.
The decoded data is sent to a U4 time service data decoding module, coded into UART serial data, then sent to a U5 RS-232 level conversion chip, and finally connected with an XS1 connector for output.
Due to cable transmission and signal processing, the output PPS clock signal has a certain time delay compared with the time service unit 101, and the time delay is a fixed value. Therefore, the portable clock calibration unit 105 needs to be connected for calibration through the configuration port 307. Configuration data is accessed from XS1, sent to a U5 RS-232 level conversion chip, converted to TTL level and then sent to a configuration data decoder of U4, and the decoded data is directly sent to a clock/timing generator of U4 to control PPS time delay.
Other parts of this embodiment are the same as any of embodiments 1 to 6, and thus are not described again.
Example 8:
this embodiment proposes a synchronization method for a high-precision synchronization apparatus of a distributed test system, as shown in fig. 1, fig. 2, fig. 3, fig. 4, fig. 5, and fig. 6, based on any of embodiments 1 to 7.
The working principle is as follows: the portable clock calibration unit 105 calibrates the PPS clock signal output from the signal amplification and clock recovery unit 104 through the data output port 405, and the calibration process is as follows:
s1: connecting a clock input port 401 of the portable clock calibration unit 105 with the time service unit 101 to obtain a PPS clock signal;
s2: the clock measurement and display 403 measures the time difference between the PPS clock signal of the time service unit 101 and the PPS clock signal of the atomic clock time-frequency standard source 402, which are accessed simultaneously, and records the time difference as DT1 and stores the time difference in the memory 404;
s3: connecting the clock input port 401 of the portable clock calibration unit 105 with the PPS signal output port 308 of the signal amplification and clock recovery unit 104;
s4: the clock measurement and display 403 measures the time difference between the PPS clock signal output by the simultaneously accessed signal amplification and clock recovery unit 104 and the PPS clock signal of the atomic clock time-frequency standard source 402, records the time difference as DT2, and stores the time difference in the memory 404;
s5: calculating a calibration value Dt = Dt1-Dt2, and storing the calibration value Dt = Dt1-Dt2 in the memory 404;
s6: a timing controller 305 connected to the configuration port 307 through a data output port 405, injecting Dt into the signal amplification and clock recovery unit 104;
s7: the timing controller 305 adjusts Dt of the output PPS clock signal to complete synchronization with the PPS clock signal of the timing unit 101.
And repeating the steps, and respectively calibrating the time difference of each signal amplification and clock recovery unit 104, so that the PPS clock signal output by the signal amplification and clock recovery unit 104 is synchronous with the PPS clock signal of the timing unit 101.
In summary, in the high-precision time synchronization apparatus for an indoor distributed test system according to the embodiment of the present invention, the spread spectrum clock signal modulation unit 102 modulates the time service data and the clock signal into the radio frequency signal, so that the clock signal is convenient to transmit indoors and maintains high precision; through a passive clock signal distribution and transmission mode, the clock signal is convenient to transmit in a complex indoor space and is convenient for integrated wiring; recovering a high-precision clock signal at a distributed remote end through a signal amplification and clock recovery unit 104; calibrating the distributed clock signal by the portable clock calibration unit 105; the distributed multi-channel simultaneous acquisition capability of the conventional test system is improved, and the multi-channel signal correlation analysis capability is improved.
Other parts of this embodiment are the same as any of embodiments 1 to 7, and thus are not described again.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, and all simple modifications and equivalent variations of the above embodiments according to the technical spirit of the present invention are included in the scope of the present invention.
Claims (16)
1. A high-precision synchronization device for a distributed test system is characterized by comprising a time service unit (101), a spread spectrum clock signal modulation unit (102), a passive clock signal distribution and transmission unit, a signal amplification and clock recovery unit (104) and a portable clock calibration unit (105);
the time service unit (101), the spread spectrum clock signal modulation unit (102) and the passive clock signal distribution and transmission unit are sequentially connected;
the passive clock distribution and transmission unit is provided with a plurality of output branches, each output branch is connected with a signal amplification and clock recovery unit (104) and is connected with the test equipment (106) through the signal amplification and clock recovery unit (104);
the portable clock calibration unit (105) is connected to the signal amplification and clock recovery unit (104) and forms a calibration feedback loop.
2. The high-precision synchronization device for the distributed test system according to claim 1, wherein the spread spectrum clock signal modulation unit (102) comprises a time service data input port (201), a data encoder (206), a frequency spreader (207), a modulator (208), an up conversion and amplifier (209), a radio frequency signal output port (210);
the time service data input port (201) is connected with a time service unit (101);
the radio frequency signal output port (210) is connected with a passive clock distribution and transmission unit;
the time service data input port (201), the data encoder (206), the frequency spreader (207), the modulator (208), the up-conversion and amplifier (209) and the radio frequency signal output port (210) are connected in sequence.
3. A high accuracy synchronizing device for a distributed test system according to claim 2, wherein said spread spectrum clock signal modulating unit (102) further comprises a 10MHz reference frequency input port (202), a PPS signal input port (203), a clock and timing controller (204), a pseudo random sequence generator (205);
the 10MHz reference frequency input port (202) and the PPS signal input port (203) are connected with a time service unit (101);
a first input end of the clock and time schedule controller (204) is connected with an output end of the 10MHz reference frequency input port (202), a second input end of the clock and time schedule controller is connected with an output end of the PPS signal input port (203), a first output end of the clock and time schedule controller is connected with the data encoder (206), a second output end of the clock and time schedule controller is connected with the frequency spreader (207), and a third output end of the clock and time schedule controller is connected with an input end of the pseudo-random sequence generator (205);
the output of the pseudo-random sequence generator (205) is connected to a spreader (207).
4. A high precision synchronization apparatus for distributed test system according to claim 1, wherein the signal amplifying and clock recovering unit (104) comprises a radio frequency signal input port (301), a down-conversion and AGC amplifier (302), a demodulation despreader (303), a data decoder (306), a time service data output port (309) connected in sequence;
the radio frequency signal input port (301) is connected with a passive clock signal distribution and transmission unit;
the time service data output port (309) is connected to the test equipment (106).
5. A high precision synchronization apparatus for distributed test system according to claim 4, wherein said signal amplification and clock recovery unit (104) further comprises a pseudo random sequence generator (304), a timing controller (305), a configuration port (307), a PPS signal output port (308);
the input end of the time sequence controller (305) is connected with a configuration port (307), the first output end is connected with the demodulation despreader (303) through a pseudo-random sequence generator (304), and the second output end is connected with a PPS signal output port (308).
6. A high precision synchronization apparatus for distributed test system according to claim 1, comprising a time service unit (101), a spread spectrum clock signal modulation unit (102), a passive clock signal distribution and transmission unit, a signal amplification and clock recovery unit (104), a portable clock calibration unit (105);
the time service unit (101), the spread spectrum clock signal modulation unit (102) and the passive clock signal distribution and transmission unit are sequentially connected;
the passive clock distribution and transmission unit is provided with a plurality of output branches, each output branch is connected with a signal amplification and clock recovery unit (104) and is connected with the test equipment (106) through the signal amplification and clock recovery unit (104);
the portable clock calibration unit (105) is lapped on the signal amplification and clock recovery unit (104) and forms a calibration feedback loop;
the spread spectrum clock signal modulation unit (102) comprises a time service data input port (201), a data encoder (206), a frequency spreader (207), a modulator (208), an up-conversion and amplifier (209) and a radio frequency signal output port (210);
the time service data input port (201) is connected with a time service unit (101);
the radio frequency signal output port (210) is connected with a passive clock distribution and transmission unit;
the time service data input port (201), the data encoder (206), the frequency spreader (207), the modulator (208), the up-conversion and amplifier (209) and the radio frequency signal output port (210) are connected in sequence;
the spread spectrum clock signal modulation unit (102) further comprises a 10MHz reference frequency input port (202), a PPS signal input port (203), a clock and timing controller (204) and a pseudo-random sequence generator (205);
the 10MHz reference frequency input port (202) and the PPS signal input port (203) are connected with a time service unit (101);
a first input end of the clock and time schedule controller (204) is connected with an output end of the 10MHz reference frequency input port (202), a second input end of the clock and time schedule controller is connected with an output end of the PPS signal input port (203), a first output end of the clock and time schedule controller is connected with the data encoder (206), a second output end of the clock and time schedule controller is connected with the frequency spreader (207), and a third output end of the clock and time schedule controller is connected with an input end of the pseudo-random sequence generator (205);
the output end of the pseudo-random sequence generator (205) is connected with a frequency spreader (207);
the signal amplification and clock recovery unit (104) comprises a radio frequency signal input port (301), a down-conversion and AGC amplifier (302), a demodulation despreader (303), a data decoder (306) and a time service data output port (309) which are connected in sequence;
the radio frequency signal input port (301) is connected with a passive clock signal distribution and transmission unit;
the time service data output port (309) is connected with the test equipment (106);
the signal amplification and clock recovery unit (104) further comprises a pseudo-random sequence generator (304), a timing controller (305), a configuration port (307) and a PPS signal output port (308);
the input end of the time sequence controller (305) is connected with a configuration port (307), the first output end is connected with the demodulation despreader (303) through a pseudo-random sequence generator (304), and the second output end is connected with a PPS signal output port (308).
7. A high accuracy synchronization apparatus for a distributed test system as defined in claim 1, wherein said passive clock signal distribution and transmission unit comprises a plurality of coaxial power splitters (103) and a plurality of coaxial cables;
the input end of the coaxial power divider (103) is connected with the spread spectrum clock signal modulation unit (102), and the output end of the coaxial power divider is respectively connected with a plurality of coaxial cables to form an output branch which is connected with the signal amplification and clock recovery unit (104).
8. A high precision synchronization apparatus for distributed test systems according to claim 5, characterized in that the portable clock calibration unit (105) comprises a clock input port (401), an atomic clock time-frequency standard source (402), a clock measurement and display (403), a memory (404), a data output port (405);
the clock input port (401) is connected with the PPS signal output port (308);
the data output port (405) is connected with a configuration port (307);
the first input end of the clock measuring and displaying device (403) is connected with the output end of the clock input port (401), the second input end of the clock measuring and displaying device is connected with the output end of the atomic clock time-frequency standard source (402), the first output end of the clock measuring and displaying device is connected with the input end of the memory (404), and the second output end of the clock measuring and displaying device is connected with the input end of the data output port (405).
9. The high-precision synchronizer for the distributed test system according to claim 2, wherein the data encoder (206) comprises a time service data encoder, an encoded data buffer and a shift register which are connected in sequence;
-said spreader (207) comprises an exclusive or gate XOR;
the modulator (208) comprises a D/A controller and a two-channel D/A converter U5 which are connected in sequence;
the up-conversion and amplifier (209) comprises a low-pass filter FL1, a low-pass filter FL2, an integrated quadrature debugger U6, an amplifier U7 and a low-pass filter FL3 which are connected in sequence;
the low-pass filter FL1 and the low-pass filter FL2 are arranged between the dual-channel D/A converter U5 and the integrated orthogonal debugger U6 in parallel;
the time service data input port (201) is connected with a time service data encoder;
the low pass filter FL3 is connected to the radio frequency signal output port (210).
10. A high accuracy synchronizing device for a distributed test system according to claim 9, wherein said spread spectrum clock signal modulating unit (102) further comprises an amplifier U1, an amplifier U2, an amplifier U3;
the amplifier U1 is arranged between a time service data input port (201) and a time service data encoder;
the amplifier U2 is arranged between the PPS signal input port (203) and the clock and time sequence controller (204);
the amplifier U3 is disposed between a 10MHz reference frequency input port (202) and a clock and timing controller (204).
11. A high accuracy synchronization apparatus for distributed test systems according to claim 4, wherein said down conversion and AGC amplifier (302) comprises a low pass filter FL4, an amplifier U8, an integrated quadrature demodulator U9;
the data decoder (306) comprises a configuration data decoder and a time service data decoder;
the demodulation despreader (303) comprises a low-pass filter FL5 and a low-pass filter FL6 which are arranged in parallel, a dual-channel A/D converter U10 which is sequentially connected to the output ends of the low-pass filter FL5 and the low-pass filter FL6, an A/D acquisition synchronization module, a first multiplier and a first integrator which are sequentially connected to the first output end of the A/D acquisition synchronization module, a second multiplier and a second integrator which are sequentially connected to the second output end of the A/D acquisition synchronization module;
the low-pass filter FL4 is connected with a radio frequency signal input port (301);
the integrated quadrature demodulator U9 is connected to a low pass filter FL5 and a low pass filter FL 6;
one end of the time service data decoder is connected with the first integrator and the second integrator, and the other end of the time service data decoder is connected with a time service data output port (309);
the configuration data decoder is connected with a configuration port (307) at one end and is connected with a time schedule controller (305) at the other end.
12. A high accuracy synchronizer for a distributed test system according to claim 11 wherein an amplifier U12 is provided between said configuration data decoder and configuration port (307) and between said timing data decoder and said timing data output port;
an amplifier U13 is arranged between the timing controller (305) and the PPS signal output port (308).
13. A high accuracy synchronization apparatus for a distributed test system as defined in claim 11 wherein said signal amplification and clock recovery unit (104) further comprises an integrated quadrature demodulator U9 configuration module;
the integrated quadrature demodulator U9 configuration module is arranged between the integrated quadrature demodulator U9 and the time service data decoder.
14. A high precision synchronization apparatus for a distributed test system according to claim 13, wherein a loop tracker is provided between the timing controller (305) and the pseudo random sequence generator (304);
the first input end of the loop tracker is connected with the first integrator, the second input end of the loop tracker is connected with the second integrator, the third input end of the loop tracker is connected with the clock controller (305), the first output end of the loop tracker is connected with the integrated quadrature demodulator U9 configuration module, and the second output end of the loop tracker is connected with the time service data decoder.
15. A high-precision synchronization method for a distributed test system, based on the high-precision synchronization apparatus for a distributed test system claimed in any one of claims 1 to 14, comprising the steps of:
step 1: collecting time service data and clock signals by using a time service unit (101);
step 2: the spread spectrum clock signal modulation unit (102) is used for modulating the time service data and the clock signal collected by the time service unit (101) into a radio frequency signal;
and step 3: distributing and delivering the radio frequency signal modulated by the spread spectrum clock signal modulation unit (102) to at least one signal amplification and clock recovery unit (104) with a passive clock signal distribution and transmission unit;
and 4, step 4: a signal amplification and clock recovery unit (104) is used for converting, amplifying and demodulating the radio frequency signal into time service data and a clock signal;
and 5: and feeding the clock signal of each signal amplification and clock recovery unit (104) back to the signal amplification and clock recovery unit (104) by using a portable clock calibration unit (105) for calibration.
16. A high-precision synchronization method for a distributed test system, based on the high-precision synchronization device for a distributed test system of claim 6, characterized by comprising the following steps:
step S1: connecting a clock input port (401) of a portable clock calibration unit (105) with a time service unit (101) to acquire a PPS clock signal;
step S2: measuring the time difference DT1 between the PPS clock signal of the time service unit (101) and the PPS clock signal of the atomic clock time-frequency standard source which are accessed simultaneously by using a clock measuring and displaying device (403), and storing the time difference DT1 in a memory (404);
step S3: connecting a clock input port (401) of the portable clock calibration unit (105) with a PPS signal output port (308) of the signal amplification and clock recovery unit (104);
step S4: measuring the time difference DT2 between the PPS clock signal output by the simultaneously accessed signal amplification and clock recovery unit (104) and the PPS clock signal of the atomic clock time-frequency standard source (402) by using a clock measurement and display (403), and storing the time difference DT2 to a memory (404);
step S5: the difference value of the time difference DT1 of the PPS clock signal and the time difference DT2 of the PPS clock signal is used as a calibration value DT and is stored in a memory (404);
step S6: a timing controller (305) connected to the configuration port (307) through a data output port (405) for injecting the calibration value Dt into the signal amplification and clock recovery unit (104);
step S7: the timing controller (305) adjusts the output PPS clock signal by a calibration value Dt, and completes the synchronization with the PPS clock signal of the timing unit (101).
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