CN114696610A - Charge pump circuit - Google Patents
Charge pump circuit Download PDFInfo
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- CN114696610A CN114696610A CN202011575701.XA CN202011575701A CN114696610A CN 114696610 A CN114696610 A CN 114696610A CN 202011575701 A CN202011575701 A CN 202011575701A CN 114696610 A CN114696610 A CN 114696610A
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- 239000003990 capacitor Substances 0.000 claims abstract description 97
- 238000007599 discharging Methods 0.000 claims abstract description 18
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- 238000001514 detection method Methods 0.000 claims description 10
- 230000000295 complement effect Effects 0.000 claims description 8
- 230000000630 rising effect Effects 0.000 claims description 6
- 230000008878 coupling Effects 0.000 claims description 5
- 238000010168 coupling process Methods 0.000 claims description 5
- 238000005859 coupling reaction Methods 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 230000001976 improved effect Effects 0.000 abstract description 3
- 230000001276 controlling effect Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 abstract 1
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 13
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- 230000009286 beneficial effect Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/34—Snubber circuits
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The present disclosure relates to the field of power converter technology, and provides a charge pump circuit, which utilizes a high-side driver to respectively control a first transistor and a second transistor to be alternately switched on and off in each clock cycle, and provides an output current at a voltage output end of the charge pump circuit; and respectively controlling the third transistor and the fourth transistor to be alternately switched on and off in each clock period during the soft start period of the charge pump circuit through the low-side driver so as to match the charging of the second transistor to the flying capacitor or match the discharging of the flying capacitor to the voltage output end through the first transistor, and regulating the voltage difference between two ends of the first transistor by clamping the magnitude of the flying capacitor discharging current during discharging, wherein the output current is a pulse signal output by a duty ratio. Therefore, the problem that the transistor is damaged because current with too high peak flows through the body diode of the transistor when the charge pump circuit is in soft start in the prior art can be solved, and the reliability of the circuit is improved.
Description
Technical Field
The present disclosure relates to power converters, and more particularly, to a charge pump circuit.
Background
A charge pump (charge pump), also known as a switched load capacitive voltage converter, is a converter that stores energy using a so-called "fast" or "pumped" load capacitor. The charge pump may be configured to generate an output voltage that is a multiple (e.g., 2, 3.... N times) of the input voltage, or it may set an output voltage that is a fraction thereof (e.g., 1/2, 1/3.. 1/N times the input voltage). In some implementations, this circuit may also generate a negative output voltage from a positive input voltage. Since the charge pump circuit does not require an inductor for voltage conversion, it is sometimes called an inductor-less DC/DC converter, and is widely used in power supplies, memories, and radio frequency chips.
Compared with the traditional inductance type switching power supply, the DC/DC converter (charge pump) with the switched capacitor structure has extremely high conversion efficiency and power density (without introducing an inductance element). However, since the charge pump has no inductive current limitation, the output voltage is difficult to perform soft start as the conventional inductive switching power supply.
In some power supplies, the bias voltage is gradually generated at the time of start-up by using a transformer. However, the use of transformers is expensive. In other power supplies, a voltage is developed at start-up by using a bootstrap technique, in which the energy of the switching node within the power supply circuit is used to charge a capacitor that provides the local power supply for the switching transistor.
Fig. 1 shows a schematic structure of a boost charge pump circuit in the prior art. As shown in fig. 1, the charge pump circuit 100 includes a voltage input terminal Vin, a voltage output terminal Vout, a bootstrap terminal BSTP, transistors Q1-Q4 sequentially connected between the voltage output terminal Vout and ground, a flying capacitor Cfly connected in parallel between a first terminal of the transistor Q2 and a second terminal of the transistor Q3, an output capacitor Co and drivers 101 to 104, and a bootstrap diode Dbs and a bootstrap capacitor Cbs connected in series between the voltage output terminal Vout and the flying capacitor Cfly. The flying capacitor Cfly has a first terminal C1P connected to a connection node between the transistor Q1 and the transistor Q2, a second terminal C1N connected to a connection node between the transistor Q3 and the transistor Q4, an output capacitor Co connected between the voltage output terminal Vout and ground, and a connection node between the transistor Q2 and the transistor Q3 connected to the voltage input terminal Vin. An output terminal of the driver 101 is connected to a control terminal of the transistor Q1 for providing a gate voltage V1 for controlling the transistor Q1 to be turned on and off according to the first clock signal drv1, an output terminal of the driver 102 is connected to a control terminal of the transistor Q2 for providing a gate voltage V2 for controlling the transistor Q2 to be turned on and off according to the second clock signal drv2, an output terminal of the driver 103 is connected to a control terminal of the transistor Q3 for providing a gate voltage V3 for controlling the transistor Q3 to be turned on and off according to the third clock signal drv3, and an output terminal of the driver 104 is connected to a control terminal of the transistor Q4 for providing a gate voltage V4 for controlling the transistor Q4 to be turned on and off according to the fourth clock signal drv4, so as to obtain the output voltage Vout.
Both transistors Q1 and Q2 are unable to conduct due to the low Vout voltage at initial soft start. The charging of both capacitors Cfly and Co is done by means of the body diodes of transistors Q1 and Q2. In the conventional solution, the transistor Q3 is turned on each time for a very short time (10-20ns), during which the first terminal C1P of the capacitor Cfly is bootstrapped to a high voltage, charging the output capacitor Co via the body diode of the transistor Q1. Because the charging time is extremely short, the average output current Iout is very small, so that Vout is slowly increased, and soft start is realized. However, during this time, the voltage difference between the positive terminal C1P of the capacitor Cfly and Vout is large, so the current spike is high, and the body diode of the transistor Q1 is easily damaged.
The prior art can make the transistor Q1 bear larger current by increasing its body diode, but this method not only increases the area of the transistor and increases the circuit cost, but also the current flowing in the body diode of the transistor will flow into the substrate of the transistor through parasitic effect, causing various secondary effects, and the reliability is poor.
Disclosure of Invention
In order to solve the technical problem, the present disclosure provides a charge pump circuit, which can improve the problem that a transistor is damaged due to a current with an excessively high peak flowing through a body diode of the transistor when the charge pump circuit is in a soft start, and improve the reliability of the circuit.
The present disclosure provides a charge pump circuit, comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, a flying capacitor coupling the second transistor and the third transistor, and an output capacitor coupling the voltage output terminal, which are connected in sequence between a voltage output terminal and ground, wherein the voltage input terminal of the charge pump circuit is connected with the connection node of the second transistor and the third transistor;
a high side driver coupled to the first and second transistors, the high side driver for controlling the first and second transistors to be turned on and off in a complementary manner according to a first clock signal and a second clock signal, respectively, during each clock cycle to provide an output current at the voltage output terminal;
a low side driver coupling the aforementioned third and fourth transistors, the low side driver configured to:
in each clock cycle during the soft start of the charge pump circuit, the third transistor and the fourth transistor are respectively controlled to be switched on and off in a complementary manner according to a third clock signal and a fourth clock signal, so as to match the charging of the flying capacitor by the second transistor or the discharging of the flying capacitor to the voltage output end through the first transistor, and
the voltage difference between the two ends of the first transistor is adjusted by clamping the discharge current of the flying capacitor during discharge,
in the continuous clock period during the soft start of the charge pump circuit, the output current is a pulse signal output by a duty ratio.
Preferably, the first clock signal and the third clock signal have the same frequency and the same period, and the second clock signal and the fourth clock signal have the same frequency, the same phase and the same period, and
the rising edge of the first clock signal is obtained by delaying the falling edge of the second clock signal, the rising edge of the second clock signal is obtained by delaying the falling edge of the first clock signal, and the two sections of delay intervals are equal.
Preferably, the charge pump circuit further comprises:
and the bootstrap diode and the bootstrap capacitor are connected between the voltage output end and the first end of the flying capacitor in series, and a connection node of the bootstrap diode and the bootstrap capacitor is used as a bootstrap end of the charge pump circuit.
Preferably, the aforementioned high-side driver comprises:
the input end of the first driving unit is connected with the first clock signal, the output end of the first driving unit is connected with the control end of the first transistor and used for providing a first control voltage, the positive power supply end is connected with the bootstrap end, and the negative power supply end is connected with the first end of the flying capacitor;
and the input end of the second driving unit is connected with the second clock signal, the output end of the second driving unit is connected with the control end of the second transistor and used for providing a second control voltage, the positive power supply end is connected with the voltage output end, and the negative power supply end is connected with the voltage input end.
Preferably, the aforementioned low-side driver comprises:
a third driving unit, connected to the first end of the flying capacitor as a power supply end, for providing a third control voltage according to the third clock signal, where the third control voltage is used to control a conducting current of the third transistor during each clock cycle during the soft start of the charge pump circuit, so as to discharge the voltage output end through the first transistor in cooperation with the flying capacitor, and to control the third transistor to be turned off according to the third clock signal, so as to charge the flying capacitor in cooperation with the second transistor;
a fourth driving unit, configured to provide a fourth control voltage according to the third clock signal, where the fourth control voltage is used to control on/off of the third transistor in each clock cycle during normal operation of the charge pump circuit, so as to cooperate with the high-side driver to provide an output voltage to the voltage output terminal;
and a first selection switch having a first selection terminal connected to the output terminal of the third driving unit, a second selection terminal connected to the output terminal of the fourth driving unit, and a first control terminal connected to the control terminal of the third transistor, wherein the first selection switch selectively provides the third control voltage or the fourth control voltage to the third transistor in response to a first switch control signal.
Preferably, the aforementioned low-side driver further comprises:
a fifth driving unit, configured to provide a fifth control voltage according to a clock signal and an input signal accessed by the voltage input terminal, where the fifth control voltage is used to control a conducting current of a fourth transistor during conducting in each clock cycle during soft start of the charge pump circuit, so as to cooperate with the second transistor to pre-charge the flying capacitor;
a sixth driving unit, configured to provide a sixth control voltage according to the fourth clock signal and the input signal accessed by the voltage input terminal, where the sixth control voltage is used to control the fourth transistor to be turned on for a period of time in each clock cycle during the soft start operation of the charge pump circuit, and cooperate with the second transistor to charge the flying capacitor, and control the fourth transistor to be turned off according to the fourth clock signal, so as to cooperate with the flying capacitor to discharge the voltage output terminal through the first transistor;
and a second selection switch having a third selection terminal connected to the output terminal of the fifth driving unit, a fourth selection terminal connected to the output terminal of the sixth driving unit, and a second control terminal connected to the control terminal of the fourth transistor, wherein the second selection switch is responsive to a second switch control signal to selectively provide the fifth control voltage or the sixth control voltage to the fourth transistor.
Preferably, the aforementioned third driving unit includes:
and the first current source and the fifth transistor are connected between the first end of the flying capacitor and the ground in series, the first current source is controlled by the third clock signal, the first end of the fifth transistor is connected with the control end of the fifth transistor, the second end of the fifth transistor is grounded, and the control end of the fifth transistor is connected with the first selection terminal.
Preferably, an input terminal of the fourth driving unit is connected to the third clock signal, an output terminal of the fourth driving unit is connected to the second selection terminal for providing the fourth control voltage, a positive power supply terminal is connected to the first terminal of the flying capacitor, and a negative power supply terminal is connected to the second terminal of the flying capacitor.
Preferably, the aforementioned fifth driving unit includes:
and a second current source and a sixth transistor connected in series between the voltage input terminal and ground, wherein a first terminal of the sixth transistor is connected to its own control terminal, a second terminal thereof is grounded, and the control terminal is connected to the third selection terminal.
Preferably, an input end of the sixth driving unit is connected to the fourth clock signal, an output end of the sixth driving unit is connected to the fourth selection terminal to provide a sixth control voltage, a positive power end of the sixth driving unit is connected to the voltage input end, and a negative power end of the sixth driving unit is grounded.
Preferably, the first switch control signal is in a low level state, the first control terminal of the first selection switch and the first selection terminal are in a communication state, and the third driving unit provides a third control voltage to the third transistor;
the first switch control signal is in a high level state, the first control terminal of the first selection switch and the second selection terminal are in a connected state, and the fourth driving unit provides a fourth control voltage to the third transistor.
Preferably, the second switch control signal is in a high state, the second control terminal of the second selection switch is in a connection state with the third selection terminal, and the fifth driving unit provides a fifth control voltage to the fourth transistor;
the second switch control signal is in a low level state, the second control terminal of the second selection switch is in a communication state with the fourth selection terminal, and the sixth driving unit provides a sixth control voltage to the fourth transistor.
Preferably, the charge pump circuit further comprises:
and the input end of the control unit is respectively connected with the output voltage and the fourth clock signal, and the output end of the control unit is respectively connected with the first selection switch and the second selection switch and is used for correspondingly providing the first switch control signal to the first selection switch and providing the second switch control signal to the second selection switch.
Preferably, the aforementioned control unit comprises:
the first detection module is connected with a preset reference voltage and the output voltage, and responds to the fact that the output voltage is greater than or equal to the reference voltage, and the generated first switch control signal is in a high level state; in response to the output voltage being less than the reference voltage, the generated first switch control signal is in a low level state;
a second detection module, configured to generate the second switch control signal in a high state in response to an active pulse of the fourth clock signal in each clock cycle during the soft start of the charge pump circuit; the second switch control signal is generated to be in a low state in response to the inactive pulse of the fourth clock signal.
Preferably, any one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor is an N-type metal oxide semiconductor field effect transistor.
The beneficial effects of this disclosure are: the present disclosure provides a charge pump circuit, which utilizes a high-side driver coupled with a first transistor and a second transistor, and controls the first transistor and the second transistor to be alternately switched on and off according to a first clock signal and a second clock signal in each clock period so as to provide an output current at a voltage output end of the charge pump circuit; and through coupling the low side driver of the third transistor and the fourth transistor, in each clock cycle during the soft start of the charge pump circuit, the third transistor and the fourth transistor are controlled to be alternately switched on and off according to a third clock signal and a fourth clock signal, so as to match the charging of the flying capacitor by the second transistor or the discharging of the flying capacitor to the voltage output end through the first transistor, and regulate the voltage difference between two ends of the first transistor by clamping and controlling the magnitude of the flying capacitor discharging current during the discharging, wherein in the continuous clock cycles during the soft start of the charge pump circuit, the output current is a pulse signal output by duty ratio. The charge pump circuit uses a first switch control signal generated by the detection result of the output voltage and the preset reference voltage to gate a driving unit (a third driving unit or a fourth driving unit) connected with the control end of the third transistor in the low-side driver, and a second switch control signal generated by the fourth clock signal is used for gating a driving unit (a fifth driving unit or a sixth driving unit) connected with the control end of the fourth transistor in the low-side driver, the voltage value at two ends of the flying capacitor in each clock cycle is controlled by controlling the discharge current of the flying capacitor, and the voltage difference between the first end of the flying capacitor and the voltage output end is controlled, so that larger peak current is avoided, the problem that the transistor is damaged because the current with overhigh peak flows through the body diode of the transistor when the charge pump circuit is in soft start in the prior art is solved, and the reliability of the circuit is improved.
In addition, the first transistor and the second transistor in the charge pump circuit provided by the disclosure do not have large current in the circuit before being turned on, so that the first transistor and the second transistor in the charge pump circuit can adopt transistors with lower breakdown voltage, which is beneficial to reducing the area of the transistors and reducing the circuit cost compared with the traditional charge pump circuit.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a charge pump circuit of the prior art;
fig. 2 shows a block diagram illustrating a structure of a charge pump circuit provided by an embodiment of the present disclosure;
FIG. 3 shows a circuit schematic of the charge pump circuit of FIG. 2;
FIG. 4 is a schematic diagram of a control unit in the charge pump circuit of FIG. 2;
fig. 5 shows an operation timing chart of respective signals when the charge pump circuit shown in fig. 3 operates.
Detailed Description
To facilitate an understanding of the present disclosure, the present disclosure will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present disclosure are set forth in the accompanying drawings. However, the present disclosure may be embodied in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It should be understood that in the following description, "circuitry" may comprise singly or in combination hardware circuitry, programmable circuitry, state machine circuitry, and/or elements capable of storing instructions executed by programmable circuitry. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
The present disclosure is described in detail below with reference to the accompanying drawings.
Fig. 2 shows a block diagram illustrating a structure of a charge pump circuit provided by an embodiment of the present disclosure, and fig. 3 shows a circuit schematic diagram of the charge pump circuit shown in fig. 2.
Referring to fig. 2 and 3, an embodiment of the present disclosure provides a boost-type charge pump circuit 200, which includes: the high-side driver 210 and the low-side driver 220 are connected in parallel, and the bootstrap diode Dbs and the bootstrap capacitor Cbs are connected in series between the voltage output end and the first end CIP of the flying capacitor Cfly.
A first end C1P of the flying capacitor Cfly is connected to a connection node between the transistor Q1 and the transistor Q2, a second end CIN is connected to a connection node between the transistor Q3 and the transistor Q4, the output capacitor Co is connected between the voltage output end and the ground, a connection node between the transistor Q2 and the transistor Q3 is connected to the voltage input end, and a bootstrap end BSTP is connected to a connection node between a negative end of the bootstrap diode Dbs and a first end of the bootstrap capacitor Cbs;
the high-side driver 210 is coupled with a transistor Q1 and a transistor Q2, for controlling the transistor Q1 and the transistor Q2 to be turned on and off in a complementary manner according to the first clock signal drv1 and the second clock signal drv2 in each clock cycle, respectively, so as to provide an output current Iout at the aforementioned voltage output terminal;
the low side driver 220 couples the transistor Q3 and the transistor Q4, configured to:
in each clock cycle during the soft start of the charge pump circuit 200, the transistor Q3 and the transistor Q4 are controlled to be turned on and off in a complementary manner according to the third clock signal drv3 and the fourth clock signal drv4, respectively, so as to adjust the voltage difference across the transistor Q1 in accordance with the charging of the flying capacitor Cfly by the transistor Q2 or the discharging of the flying capacitor Cfly to the voltage output terminal through the transistor Q1, and by controlling the magnitude of the flying capacitor Cfly discharging current Iss during discharging through clamping,
wherein, in the continuous clock cycles during the soft start period of the charge pump circuit 200, the output current Iout is a pulse signal with duty ratio output.
Further, referring to fig. 5, in this embodiment, the first clock signal drv1 and the third clock signal drv3 have the same frequency, the same phase and the same period, the second clock signal drv2 has the same frequency, the same phase and the same period as the fourth clock signal drv4, the first clock signal drv1 and the second clock signal drv2 are non-overlapping clocks, a rising edge of the first clock signal drv1 is obtained by delaying a falling edge of the second clock signal drv2, a rising edge of the second clock signal drv2 is obtained by delaying a falling edge of the first clock signal drv1, and two delay intervals are equal, and the delay interval is the first delay td.
Further, the aforementioned high-side driver 210 at least includes: a first driving unit 201 and a second driving unit 202,
the input end of the first driving unit 201 is connected to the first clock signal drv1, the output end is connected to the control end of the transistor Q1 to provide a first control voltage V1, the positive power end is connected to the bootstrap end BSTP, and the negative power end is connected to the first end CIP of the flying capacitor Cfly;
the input terminal of the second driving unit 202 is connected to the second clock signal drv2, the output terminal is connected to the control terminal of the transistor Q2 for providing a second control voltage V2, the positive power terminal is connected to the voltage output terminal, and the negative power terminal is connected to the voltage input terminal.
Further, the aforementioned low-side driver 220 at least includes: a third driving unit 221, a fourth driving unit 203 and a first selection switch S1,
the third driving unit 221 is connected to the first end CIP of the flying capacitor Cfly as a power supply end, and is configured to provide a third control voltage V3_1 according to the third clock signal drv3, the third control voltage V3_1 is configured to control a conducting current of the transistor Q3 in each clock cycle during the soft start of the charge pump circuit 200, so as to cooperate with the flying capacitor Cfly to discharge the voltage output end through the transistor Q1, and to control the transistor Q3 to turn off according to the third clock signal drv3, so as to cooperate with the transistor Q2 to charge the flying capacitor Cfly;
the fourth driving unit 203 is configured to provide a fourth control voltage V3_2 according to the third clock signal drv3, and the fourth control voltage V3_2 is configured to control the transistor Q3 to be turned on or off in each clock cycle of the normal operation period of the charge pump circuit 200, so as to cooperate with the high-side driver 210 to provide the output voltage Vout to the voltage output terminal;
the first selection switch S1 has a first selection terminal a connected to the output terminal of the third driving unit 221, a second selection terminal b connected to the output terminal of the fourth driving unit 203, and a first control terminal c connected to the control terminal of the transistor Q3, and the first selection switch S1 selectively provides the third control voltage V3_1 or the fourth control voltage V3_2 to the transistor Q3 in response to the first switch control signal Sc 1.
Further, the aforementioned low-side driver 220 further includes: a fifth driving unit 222, a sixth driving unit 204 and a second selection switch S2,
the fifth driving unit 222 is configured to provide a fifth control voltage V4_1 according to a clock signal Sc3 and an input signal Vin inputted from the voltage input terminal, wherein the fifth control voltage V4_1 is used to control a conducting current of the transistor Q4 conducting in each clock cycle during the soft start of the charge pump circuit 200, so as to cooperate with the transistor Q2 to precharge the flying capacitor Cfly;
the sixth driving unit 204 is configured to provide a sixth control voltage V4_2 according to the fourth clock signal drv4 and the input signal Vin connected to the voltage input terminal, the sixth control voltage V4_2 is configured to control the transistor Q4 to be turned on for a period of time in each clock cycle of the soft-start operation period of the charge pump circuit 200, so as to cooperate with the transistor Q2 to charge the flying capacitor Cfly, and control the transistor Q4 to be turned off according to the fourth clock signal drv4 to cooperate with the flying capacitor Cfly to discharge the voltage output terminal through the transistor Q1;
the second selection switch S2 has a third selection terminal d connected to the output terminal of the fifth driving unit 222, a fourth selection terminal e connected to the output terminal of the sixth driving unit 204, and a second control terminal f connected to the control terminal of the transistor Q4, and the second selection switch S2 selectively provides the fifth control voltage V4_1 or the sixth control voltage V4_2 to the transistor Q4 in response to the second switch control signal Sc 2.
Further, the aforementioned third driving unit 221 includes: a first current source Iref1 and a transistor Q5 connected in series between the first terminal CIP of the flying capacitor Cfly and ground, wherein the first current source Iref1 is controlled by the third clock signal drv3, and the transistor Q5 has a first terminal connected to its own control terminal, a second terminal connected to ground, and a control terminal connected to the first selection terminal a for providing the third control voltage V3_ 1.
Further, an input terminal of the fourth driving unit 203 is connected to the third clock signal drv4, an output terminal is connected to the second selection terminal b to provide the fourth control voltage V3_2 to the transistor Q3, a positive power terminal is connected to the first terminal CIP of the flying capacitor Cfly, and a negative power terminal is connected to the second terminal CIN of the flying capacitor Cfly.
Further, the aforementioned fifth driving unit 222 includes: a second current source Iref2 and a transistor Q6 connected in series between the voltage input terminal and ground, wherein the second current source Iref2 is controlled by a clock signal Sc3, a first terminal of the transistor Q6 is connected to its own control terminal, a second terminal is connected to ground, and the control terminal is connected to the third selection terminal e to provide the fifth control voltage V4_ 1.
Further, an input terminal of the sixth driving unit 204 is connected to the fourth clock signal drv4, an output terminal thereof is connected to the fourth selection terminal d for providing a sixth control voltage V4_2, a positive power terminal thereof is connected to the voltage input terminal, and a negative power terminal thereof is grounded.
Further, the first switch control signal Sc1 is in a low state, the first control terminal c of the first selection switch S1 is in a connection state with the first selection terminal a, and the third driving unit 221 provides the third control voltage V3_1 to the transistor Q3;
the first switch control signal Sc1 is at a high level, the first control terminal c of the first selection switch S1 is connected to the second selection terminal b, and the fourth driving unit 203 provides the fourth control voltage V3_2 to the transistor Q3.
Further, the second switch control signal Sc2 is in a high state, the second control terminal f of the second selection switch S2 is in a connection state with the third selection terminal d, and the fifth driving unit 222 provides the fifth control voltage V4_1 to the transistor Q4;
the second switch control signal Sc2 is at a low level, the second control terminal f of the second selection switch S2 is connected to the fourth selection terminal e, and the sixth driving unit 204 provides the sixth control voltage V4_2 to the transistor Q4.
Further, referring to fig. 4, in this embodiment, the charge pump circuit 200 may further include:
a control unit 230, wherein the input end of the control unit 230 is respectively connected to the output voltage Vout and the fourth clock signal drv4, and the output end is respectively connected to the first selection switch S1 and the second selection switch S2, so as to correspondingly provide the first switch control signal Sc1 to the first selection switch S1 and provide the second switch control signal Sc2 to the second selection switch S2.
Further, the aforementioned control unit 230 at least comprises: a first detection module 231 and a second detection module 232,
the first detecting module 231 accesses a preset reference voltage Vref and the output voltage Vout, and generates the first switch control signal Sc1 in a high level state in response to the output voltage Vout being greater than or equal to the reference voltage Vref; in response to the output voltage Vout being smaller than the reference voltage Vref, the first switch control signal Sc1 is generated to be in a low level state, and more specifically, in the present embodiment, the first detection module 231 includes, for example, a comparator (not shown), a non-inverting input terminal of the comparator is connected to the output voltage Vout provided by the voltage output terminal of the charge pump circuit 200, an inverting input terminal of the comparator is connected to the preset reference voltage Vref, and an output terminal of the comparator provides the switch control signal Sc;
the second detecting module 232 is configured to generate the second switch control signal Sc2 to be in a high state in response to an active pulse of the fourth clock signal drv4 in each clock cycle of the soft start period of the charge pump circuit 200; the second switch control signal Sc2 is generated to be in a low state in response to an inactive pulse of the fourth clock signal drv 4.
Further, the magnitude of the reference voltage Vref can be set according to the voltage requirement of the practical application, and in a preferred embodiment, the voltage value of the reference voltage Vref is, for example, twice the voltage value of the input voltage Vin.
Further, any one of the Transistor Q1, the Transistor Q2, the Transistor Q3, the Transistor Q4, the Transistor Q5, and the Transistor Q6 is an N-type Metal oxide Semiconductor Field Effect Transistor (NMOS Transistor).
The charge pump circuit 100 disclosed in the prior art is a boost-type converter with a switched capacitor structure, which cannot directly provide the voltage required by the subsequent circuit in the initial stage, and the output voltage of the circuit is difficult to perform soft start as the conventional switching power supply because the circuit does not have inductive current limitation. As shown in fig. 1, the flying capacitor Cfly first terminal C1P is bootstrapped to a high voltage to charge the output capacitor Co through the body diode of the transistor Q1 during a very short time (10-20ns) each time the transistor Q3 is turned on. Because the charging time is extremely short, the average output current Iout is very small, so that Vout is slowly increased, and soft start is realized. However, during this time, the voltage difference between the positive terminal C1P of the capacitor Cfly and Vout is large, so the current spike is high, and the body diode of the transistor Q1 is easily damaged.
The charge pump circuit 200 according to the embodiment of the disclosure can gate the driving unit (the third driving unit 221 or the fourth driving unit 203) connected to the control terminal of the transistor Q3 in the low-side driver 220 by using the first switching control signal Sc1 outputted according to the detection result of the output voltage Vout and the preset reference voltage Vref, gate the driving unit (the fifth driving unit 222 or the sixth driving unit 204) connected to the control terminal of the transistor Q4 in the low-side driver 220 by using the second switching control signal Sc2 generated by the fourth clock signal drv4, and control the flying capacitor Cfly discharging current Iss during discharging through clampingThe magnitude of the voltage across the flying capacitor Cfly is controlled to control the voltage value V in each clock cycleCflyAnd further controlling the voltage difference between the first end CIP of the flying capacitor Cfly and the voltage output end, so that in the continuous clock period during the soft start of the charge pump circuit 200, the output current Iout is a pulse signal output by a duty ratio, and the high level value of the pulse signal is equal to the value of the discharge current Iss, thereby avoiding a large spike current, and improving the problem that the transistor is damaged because the current with an excessively high spike flows through the body diode of the transistor when the charge pump circuit is in the soft start in the prior art.
Fig. 5 shows an operation timing chart of respective signals when the charge pump circuit shown in fig. 3 operates. As used herein, the term "clock cycle" refers to the time period between two adjacent pulses of a clock signal, and one clock cycle consists of two phases: a first phase of high level in a clock cycle and a second phase of low level in a cycle following the first phase, or a first phase of low level in a clock cycle and a second phase of high level in a cycle following the first phase.
Specifically, referring to fig. 3 to 5, the operation principle of the charge pump circuit 200 is as follows:
in the soft start phase of the charge pump circuit 200, two phases can be divided:
in the first stage, the control terminal c of the first selection switch S1 is connected to the first selection terminal a, the control terminal f of the second selection switch S2 is connected to the first selection terminal d, the voltage of the initial output voltage Vout is low, neither the transistor Q1 nor the transistor Q2 is turned on, the first switch control signal Sc1 is in a low state, and the control terminal c of the first selection switch S1 is connected to the first selection terminal a (assuming that the duty ratios of the first clock signal drv1 to the fourth clock signal drv4 are all 50%, and the drv1 to drv4 may be respectively obtained by means of in-phase, inversion, delay, and the like of the clock signal with the duty ratio of 50%, which is not unique here).
When the fourth clock signal drv4 is at a low level and the third clock signal drv3 is at a high level, the transistor Q4 is controlled to be turned off by the generated fourth control voltage V4_2, and the transistor Q3 is controlled to be turned on by the third control voltage V3, so that the input signal Vin connected to the voltage input terminal is precharged to the flying capacitor Cfly through the body diode of the transistor Q2, and the precharge current is Ipre. The third clock signal drv3 is used to control the first current source Iref1 to turn off, and the clock signal Sc3 is used to control the second current source Iref2 to turn on, at this time, the transistor Q6 and the transistor Q4 form a current mirror structure. When the transistor Q4 is turned on, the precharge current flowing through the transistor Q4 is:
Ipre＝Iref2*(W/L)Q4/(W/L)Q6 (1)
in the formula (1), W and L are the width and length of the NMOS tube, respectively, (W/L) Q4For the width-to-length ratio of transistor Q4, (W/L) Q6Is the width to length ratio of transistor Q6. Voltage difference V on flying capacitor CflyCflyWhen the following formula (2) is satisfied, the precharge is completed and the first stage is ended.
VCfly＝Vin-Vdiode (2)
Wherein, VdiodeIs the conduction voltage drop of the body diode of the transistor Q2.
In the second stage, the control terminal f of the second selection switch S2 is turned to be connected to the first selection terminal e, and the second current source Iref2 is selectively turned off, the second stage is divided into two processes, and the two processes control the first clock signal drv1 to the fourth clock signal drv4 to alternately perform:
a) when the fourth clock signal drv4 is at low level and the third clock signal drv3 is at high level, the transistor Q4 is controlled to be turned off by the generated fourth control voltage V4_2, the first current source Iref1 is turned on, and the transistor Q3 is controlled to be turned on by the third control voltage V3, so that the voltage V at the first end of the flying capacitor Cfly is enabledC1PIs bootstrapped to a high voltage, the output capacitor Co is charged through the body diode of the transistor Q1, the output voltage Vout is generated, and the magnitude of the discharge current is Iss, wherein the third driving unit 221 controls the switching state of the first current source Iref1 by using the third clock signal drv 3. The current mirror structure formed by the transistor Q5 and the transistor Q3 clamps and controls the current flowing through the transistor Q3 when the transistor Q3 is conducted：
Iss＝Iref1*(W/L)Q3/(W/L)Q5 (3)
In the formula (4), W and L are the width and length of the NMOS tube, respectively, (W/L) Q3For the width-to-length ratio of transistor Q3, (W/L) Q5Is the width to length ratio of transistor Q5.
b) The first current source Iref1 is turned off, the fourth clock signal drv4 is at a high level state, the third clock signal drv3 is at a low level state, the transistor Q4 is controlled to be turned on by the generated fourth control voltage V4_1, and the transistor Q3 is controlled to be turned off by the third control voltage V3, so that the flying capacitor Cfly and the bootstrap capacitor Cbs are charged by the input voltage Vin through the body diode of the transistor Q2.
The two processes are continuously alternated, so that the output voltage Vout slowly rises, and the voltage difference V on the flying capacitor Cfly can be controlled by controlling the magnitude of the discharge current IssCflyBecause a large spike current is avoided by controlling the magnitude of the discharge current Iss when the flying capacitor Cfly discharges to the voltage output in the first process a).
When the output voltage Vout rises to a certain voltage value (preset reference voltage Vref, for example, Vref is approximately 2 × Vin), the transistors Q1 and Q2 may be normally turned on, so as to charge the output voltage Vout to 2 × Vin. When the output voltage Vout is close to Vref, i.e., the soft start is completed, the first switch control signal Sc1 is in a high state, the control terminal c of the first selection switch S1 is connected to the second selection terminal b, the fourth driving unit 203 supplies the fourth control voltage V3_2 to the transistor Q3, and then the charge pump circuit 200 enters a normal operation state.
In summary, the present disclosure provides a charge pump circuit 200, which can utilize a high-side driver 210 coupled to a transistor Q1 and a transistor Q2 to control a transistor Q1 and a transistor Q2 to be turned on and off in a complementary manner according to a first clock signal drv1 and a second clock signal drv2 in each clock cycle, respectively, so as to provide an output current Iout at a voltage output terminal of the charge pump circuit 200; and a low side driver 220 coupled between transistor Q3 and transistor Q4 for each clock cycle during soft start of the charge pump circuit 200In the method, the transistor Q3 and the transistor Q4 are controlled to be alternately turned on and off according to the third clock signal drv3 and the fourth clock signal drv4, so as to adjust the voltage difference between the two ends of the transistor Q1 in accordance with the charging of the flying capacitor Cfly by the transistor Q2 or the discharging of the flying capacitor Cfly to the voltage output end through the transistor Q1, and by controlling the magnitude of the discharging current Iss of the flying capacitor Cfly during the discharging through clamping, wherein the output current Iout is a pulse signal output by a duty ratio in a continuous clock cycle during the soft start of the charge pump circuit 200. The charge pump circuit 200 thus gates the driving unit (the third driving unit 221 or the fourth driving unit 203) connected to the control terminal of the transistor Q3 in the low-side driver 220 by using the first switching control signal Sc1 generated by the detection result of the output voltage Vout and the preset reference voltage Vref, gates the driving unit (the fifth driving unit 222 or the sixth driving unit 204) connected to the control terminal of the transistor Q4 in the low-side driver 220 by using the second switching control signal Sc2 generated by the fourth clock signal drv4, and controls the voltage value V across the flying capacitor Cfly in each clock cycle by controlling the magnitude of the discharge current Iss of the flying capacitor Cfly at the time of dischargeCflyFurther controlling the voltage V of the first end CIP of the flying capacitor CflyC1PThe voltage difference between the output end of the charge pump circuit and the voltage output end, so that larger peak current is avoided, the problem that the transistor is damaged because current with too high peak flows through a body diode of the transistor when the charge pump circuit is in soft start in the prior art is solved, and the reliability of the charge pump circuit is improved.
In addition, because there is no large current in the circuit before the transistor Q1 and the transistor Q2 are turned on, compared with a conventional charge pump circuit, the transistor Q1 and the transistor Q2 in the charge pump circuit of the embodiment of the present disclosure may adopt transistors with lower breakdown voltage, which is beneficial to reducing the area of the transistors and reducing the circuit cost.
It should be noted that although the device is described herein as being an N-channel or P-channel device, or an N-type or P-type doped region, one of ordinary skill in the art will appreciate that complementary devices may be implemented in accordance with the present invention. It will be understood by those skilled in the art that conductivity type refers to the mechanism by which conduction occurs, for example by conduction through holes or electrons, and thus does not relate to the doping concentration but to the doping type, for example P-type or N-type. It will be understood by those of ordinary skill in the art that the words "during", "when" and "when … …" as used herein in relation to the operation of a circuit are not strict terms referring to actions occurring immediately upon initiation of a startup action, but rather there may be some small but reasonable delay or delays, such as various transmission delays, between them and the reaction action (action) initiated by the startup action. The words "about" or "substantially" are used herein to mean that the value of an element (element) has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there is always a slight deviation that makes it difficult for the value or position to be exactly the stated value. It has been well established in the art that a deviation of at least ten percent (10%) for a semiconductor doping concentration of at least twenty percent (20%) is a reasonable deviation from the exact ideal target described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.
Moreover, it should be further noted that the relational terms such as first and second, and the like, herein are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present disclosure, and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention as herein taught are within the scope of the present disclosure.
Claims (15)
1. A charge pump circuit, comprising:
the flying capacitor is coupled with the second transistor and the third transistor, the output capacitor is coupled with the voltage output end, and the voltage input end of the charge pump circuit is connected with the connection node of the second transistor and the third transistor;
a high side driver coupled to the first and second transistors, the high side driver for controlling the first and second transistors to turn on and off in a complementary manner in accordance with first and second clock signals, respectively, during each clock cycle to provide an output current at the voltage output;
a low side driver coupling the third transistor and the fourth transistor, the low side driver configured to:
in each clock cycle during soft start of the charge pump circuit, the third transistor and the fourth transistor are controlled to be turned on and off in a complementary manner according to a third clock signal and a fourth clock signal, respectively, in coordination with charging of the flying capacitor by the second transistor or discharging of the flying capacitor to the voltage output terminal via the first transistor, and
the magnitude of the flying capacitor discharging current during discharging is controlled through clamping to adjust the voltage difference between two ends of the first transistor,
wherein, in the continuous clock period during the soft start of the charge pump circuit, the output current is a pulse signal output by a duty ratio.
2. The charge pump circuit of claim 1, wherein the first clock signal and the third clock signal have the same frequency and the same period, the second clock signal and the fourth clock signal have the same frequency and the same phase and the same period, an
The rising edge of the first clock signal is obtained by delaying the falling edge of the second clock signal, the rising edge of the second clock signal is obtained by delaying the falling edge of the first clock signal, and the two sections of delay intervals are equal.
3. The charge pump circuit of claim 2, further comprising:
and the bootstrap diode and the bootstrap capacitor are connected between the voltage output end and the first end of the flying capacitor in series, and a connection node of the bootstrap diode and the bootstrap capacitor is used as a bootstrap end of the charge pump circuit.
4. The charge pump circuit of claim 3, wherein the high-side driver comprises:
the input end of the first driving unit is connected to the first clock signal, the output end of the first driving unit is connected to the control end of the first transistor and used for providing a first control voltage, the positive power supply end is connected to the bootstrap end, and the negative power supply end is connected to the first end of the flying capacitor;
and the input end of the second driving unit is connected to the second clock signal, the output end of the second driving unit is connected with the control end of the second transistor and used for providing a second control voltage, the positive power supply end is connected with the voltage output end, and the negative power supply end is connected with the voltage input end.
5. The charge pump circuit of claim 4 wherein the low side driver comprises:
a third driving unit, connected to the first end of the flying capacitor as a power supply end, for providing a third control voltage according to the third clock signal, where the third control voltage is used to control a conducting current of the third transistor when conducting in each clock cycle during the soft start of the charge pump circuit, so as to cooperate with the flying capacitor to discharge the voltage output end through the first transistor, and to control the third transistor to turn off according to the third clock signal, so as to cooperate with the second transistor to charge the flying capacitor;
a fourth driving unit, configured to provide a fourth control voltage according to the third clock signal, where the fourth control voltage is used to control the third transistor to turn on or off in each clock cycle during normal operation of the charge pump circuit, so as to cooperate with the high-side driver to provide an output voltage for the voltage output terminal;
the first selection switch is provided with a first selection terminal communicated with the output end of the third driving unit, a second selection terminal communicated with the output end of the fourth driving unit and a first control terminal communicated with the control end of the third transistor, and the first selection switch responds to a first switch control signal and selects to provide the third control voltage or the fourth control voltage to the third transistor.
6. The charge pump circuit of claim 5 wherein the low side driver further comprises:
a fifth driving unit, configured to provide a fifth control voltage according to a clock signal and an input signal accessed by the voltage input terminal, where the fifth control voltage is used to control a conduction current of the fourth transistor when the fourth transistor is turned on in each clock cycle during a soft start period of the charge pump circuit, so as to cooperate with the second transistor to precharge the flying capacitor;
a sixth driving unit, configured to provide a sixth control voltage according to the fourth clock signal and an input signal accessed by the voltage input terminal, where the sixth control voltage is used to control the fourth transistor to be turned on for a period of time in each clock cycle during a soft start operation period of the charge pump circuit, and cooperate with the second transistor to charge the flying capacitor, and control the fourth transistor to be turned off according to the fourth clock signal, so as to cooperate with the flying capacitor to discharge the voltage output terminal through the first transistor;
and a second selection switch having a third selection terminal connected to the output terminal of the fifth driving unit, a fourth selection terminal connected to the output terminal of the sixth driving unit, and a second control terminal connected to the control terminal of the fourth transistor, the second selection switch selectively providing the fifth control voltage or the sixth control voltage to the fourth transistor in response to a second switch control signal.
7. The charge pump circuit of claim 6, wherein the third drive unit comprises:
the first current source and the fifth transistor are connected between the first end of the flying capacitor and the ground in series, the first current source is controlled by the third clock signal, the first end of the fifth transistor is connected with the control end of the fifth transistor, the second end of the fifth transistor is grounded, and the control end of the fifth transistor is connected with the first selection terminal.
8. The charge pump circuit of claim 7, wherein an input terminal of the fourth driver unit is coupled to the third clock signal, an output terminal is coupled to the second select terminal for providing the fourth control voltage, a positive power supply terminal is coupled to the first terminal of the flying capacitor, and a negative power supply terminal is coupled to the second terminal of the flying capacitor.
9. The charge pump circuit according to claim 8, wherein the fifth driving unit comprises:
and the first end of the sixth transistor is connected with the control end of the sixth transistor, the second end of the sixth transistor is grounded, and the control end of the sixth transistor is connected with the third selection terminal.
10. The charge pump circuit of claim 9, wherein the sixth driving unit has an input terminal coupled to the fourth clock signal, an output terminal coupled to the fourth selection terminal for providing the sixth control voltage, a positive power terminal coupled to the voltage input terminal, and a negative power terminal coupled to ground.
11. The charge pump circuit according to claim 5, wherein the first switch control signal is in a low state, the first control terminal of the first selection switch and the first selection terminal are in a connected state, and the third driving unit supplies the third control voltage to the third transistor;
the first switch control signal is in a high level state, the first control terminal of the first selection switch and the second selection terminal are in a connected state, and the fourth driving unit provides the fourth control voltage to the third transistor.
12. The charge pump circuit according to claim 6, wherein the second switch control signal is in a high state, the second control terminal of the second selection switch is in a connected state with the third selection terminal, and the fifth driving unit supplies the fifth control voltage to the fourth transistor;
the second switch control signal is in a low level state, the second control terminal of the second selection switch and the fourth selection terminal are in a connected state, and the sixth driving unit provides the sixth control voltage to the fourth transistor.
13. The charge pump circuit of claim 10, further comprising:
and the input end of the control unit is respectively connected with the output voltage and the fourth clock signal, and the output end of the control unit is respectively connected with the first selection switch and the second selection switch and is used for correspondingly providing the first switch control signal to the first selection switch and providing the second switch control signal to the second selection switch.
14. The charge pump circuit of claim 13, wherein the control unit comprises:
the first detection module is connected with a preset reference voltage and the output voltage, and responds that the output voltage is greater than or equal to the reference voltage, and the generated first switch control signal is in a high level state; in response to the output voltage being less than the reference voltage, the generated first switch control signal is in a low level state;
a second detection module, configured to generate the second switch control signal to be in a high level state in response to an active pulse of the fourth clock signal in each clock cycle during the soft start of the charge pump circuit; the second switch control signal is generated to be in a low state in response to an inactive pulse of the fourth clock signal.
15. The charge pump circuit according to claim 9, wherein any one of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor is an N-type metal oxide semiconductor field effect transistor.
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| US20090121781A1 (en) * | 2007-11-13 | 2009-05-14 | Rohm Co., Ltd. | Control circuit and control method for charge pump circuit |
| CN110635680A (en) * | 2018-06-21 | 2019-12-31 | 凌力尔特科技有限责任公司 | Reverse capacitor voltage balancing for high current high voltage charge pump circuits |
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