CN114695361A - Anti-fuse memory cell, writing method and reading method thereof, and electronic device - Google Patents

Abstract

The disclosure provides an antifuse memory cell, a writing method and a reading method thereof, and an electronic device. The anti-fuse memory unit comprises a semiconductor substrate, a gate oxide layer, a word line, a bit line and the like. The transistor is formed on the semiconductor substrate, and the anti-fuse memory unit only comprises one transistor. The transistor includes a gate, a source, and a drain. The gate oxide layer is arranged between the semiconductor substrate and the grid electrode, and the thickness of the gate oxide layer is a fixed value, namely the thickness of the whole gate oxide layer does not change along with the change of the position. The word line is connected to the gate and the bit line is connected to the source and drain. The anti-fuse minimum memory cell of the present disclosure only needs one transistor and occupies a smaller space. Therefore, the technical scheme provided by the disclosure is beneficial to the integration and small-size requirements of the semiconductor device, improves the data storage density and has a very wide market prospect. The method can obviously reduce the processing difficulty and cost and improve the product yield.

Description

Anti-fuse memory cell, writing method and reading method thereof, and electronic device

Technical Field

The present disclosure relates to the field of semiconductor memory technologies, and more particularly, to an antifuse memory cell, a writing method and a reading method thereof, and an electronic device.

Background

An Anti-fuse (Anti-fuse) memory is a commonly used One Time Programmable (OTP) memory, and is generally used as an auxiliary circuit of a main functional circuit. The anti-fuse memory has the advantages of programmability, low power consumption, high safety and the like.

The smallest unit of an antifuse memory is generally composed of one programming transistor and one select transistor. The selection transistor has a switching function for turning on or off according to an applied voltage to control whether or not data storage is performed. The programming transistor has a data storage function, storing either a "1" or a "0". It can be seen that the conventional anti-fuse memory cell requires two transistors, occupying a relatively large space in the semiconductor device. However, as the integration of semiconductor devices is higher and higher, the device size is required to be smaller and smaller, and the conventional antifuse memory cell having a dual transistor structure has not been able to meet the practical requirement.

Disclosure of Invention

In order to solve the problems that the conventional anti-fuse memory cell is large in size and cannot meet the requirement of high integration degree of a semiconductor device, the disclosure provides an anti-fuse memory cell, a writing method and a reading method of the anti-fuse memory cell, and electronic equipment, so that the size of the anti-fuse memory cell is reduced, and the integration degree and reliability of the semiconductor device are improved.

To achieve the above technical object, the present disclosure provides an antifuse memory cell. The antifuse memory cell includes, but is not limited to, a semiconductor substrate, a gate oxide layer, a word line, a bit line, and the like. The transistor is formed on the semiconductor substrate, and the anti-fuse memory cell disclosed by the invention can only comprise one transistor. The transistor includes a gate, a source, and a drain. The gate oxide layer is arranged between the semiconductor substrate and the grid electrode, and the thickness of the gate oxide layer is a fixed value, namely the thickness of the whole gate oxide layer does not change along with the change of the position. The word lines are connected to the gates and the bit lines are connected to the sources and/or drains. The transistor is preferably a depletion transistor.

To achieve the above technical object, the present disclosure also provides an electronic device, which may include the antifuse memory cell in any embodiment of the present disclosure.

To achieve the above technical object, the present disclosure can also provide a writing method of an antifuse memory cell, which may include, but is not limited to, the following steps:

a first preset voltage is applied to a word line of an antifuse memory cell of the present disclosure, and a second preset voltage is applied to the bit line. And the difference value of the first preset voltage and the second preset voltage is greater than a first threshold value so as to break down the gate oxide layer and write '1' into the anti-fuse memory unit. Or applying a third preset voltage to a word line and a fourth preset voltage to the bit line of the antifuse memory cell of the present disclosure. And the difference value of the third preset voltage and the fourth preset voltage is smaller than a second threshold value so as to prevent the gate oxide layer from being broken down and write '0' into the anti-fuse memory unit.

To achieve the above technical object, the present disclosure may also provide a reading method of an antifuse memory cell, which may include, but is not limited to, the following steps:

a supply voltage is applied to the bit line of the antifuse memory cell of the present disclosure, and a ground voltage is applied to the word line. The current logic voltage on the bit line is obtained. When the current logic voltage is "1", the data stored on the antifuse memory cell is "0". Alternatively, when the current logic voltage is "0", the data stored in the antifuse memory cell is "1".

To achieve the above technical object, the present disclosure may also provide a reading method of an antifuse memory cell, which may include, but is not limited to, the following steps:

a supply voltage is applied to the bit line of the antifuse memory cell of the present disclosure, and a ground voltage is applied to the word line. The amount of charge on the bit line is acquired. The data stored on the antifuse memory cell is "0" when the amount of charge on the bit line is unchanged. Alternatively, when the amount of charge on the bit line is reduced, the data stored on the antifuse memory cell is "1".

The beneficial effect of this disclosure does:

the anti-fuse minimum memory cell provided by the disclosure only needs one transistor and occupies a smaller space. Therefore, the technical scheme provided by the disclosure is beneficial to the integration and small-size requirements of semiconductor devices, greatly improves the data storage density of the memory, and has a very wide market prospect.

The thickness of the gate oxide layer of the anti-fuse memory unit provided by the disclosure does not change along with the change of the position, namely the gate oxide layer has a single thickness. Due to the fact that the gate oxide layer with the single thickness is adopted, the processing difficulty of the anti-fuse storage unit is reduced, the product yield can be improved in the aspect of processing technology, and the processing cost is reduced.

Based on the depletion transistor adopted by some embodiments of the present disclosure, the gate oxide layer provided by the present disclosure does not need to separately design a breakdown position during processing, thereby greatly improving the success rate of data writing and reading.

Drawings

FIG. 1 illustrates a device cross-sectional structure of an antifuse memory cell in some embodiments of the present disclosure.

FIG. 2 illustrates a device plan view of a plurality of antifuse memory cells in some embodiments of the present disclosure.

FIG. 3 illustrates a schematic diagram of the structure of a 5 × 5 antifuse memory array in some embodiments of the present disclosure.

In the figure, the position of the first and second end faces,

100. a semiconductor substrate.

200. And a gate.

201. And a source electrode.

202. And a drain electrode.

300. And (4) a gate oxide layer.

400. Word lines.

500. A bit line.

600. A contact portion.

700. An active region.

800. Shallow trench isolation.

900. And a sense amplifier.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that these descriptions are illustrative only and are not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

As shown in fig. 1 and 2, one or more embodiments of the present disclosure can provide an antifuse memory cell using only one transistor. The antifuse memory cell may include, but is not limited to, a semiconductor substrate 100, a gate oxide layer 300, a word line 400, a bit line 500, a contact 600, and the like. The semiconductor base 100 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a silicon germanium substrate, a III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by performing Selective Epitaxial Growth (SEG), or the like.

As shown in fig. 1, the present disclosure forms a transistor and Shallow Trench Isolation (STI) layer on a semiconductor substrate 100. In this embodiment, specifically, an active region 700 is formed on a semiconductor substrate 100, and transistors are formed on the active region 700, and the shallow trench isolation 800 may be used for isolation and insulation between two adjacent transistors. It is understood that the transistors provided in the present disclosure may be either PMOS (P-type Metal Oxide Semiconductor) transistors or NMOS (N-type Metal Oxide Semiconductor) transistors, or CMOS (Complementary Metal Oxide Semiconductor) transistors. Taking a PMOS transistor as an example, the semiconductor substrate 100 is an N-type substrate, the active region 700 is a P-well (P + doped region), the source 201 and the drain 202 are N-wells (N + doped regions), the doping principles of the NMOS transistor and the CMOS transistor are similar, and the description of this embodiment is omitted.

The transistor includes a gate 200, a source 201, and a drain 202. The gate 200 may be fabricated from a conductive material, which may include, but is not limited to, doped polysilicon, metals (e.g., tungsten, tantalum, etc.), silicides, etc. (e.g., alloys of metals and polysilicon).

The transistor is preferably a depletion mode transistor (depletion mode transistor), so that some embodiments of the present disclosure do not need to determine the breakdown position of the gate oxide layer separately. In particular, based on the depletion mode transistor at the gate-source voltage (U)_GS) When the voltage is zero, the channel is formed, and after the gate is pressurized, carriers in the channel rapidly flow, so that the gate oxide layer at the position of the channel is broken down (the stored data can be '1'). Therefore, the method can also effectively solve the problems that the breakdown position of the gate oxide layer is inaccurate or the gate oxide layer is difficult to break down in the conventional technology; channel position at increased voltage for depletion mode transistors of the present disclosureIt has been previously determined that the gate oxide at the channel location is more carrier-rich and susceptible to breakdown, so the present disclosure improves the reliability of operation of the antifuse memory device and the overall yield of the semiconductor device.

The gate oxide layer 300 is disposed between the semiconductor substrate 100 and the gate electrode 200. The thickness of the gate oxide layer 300 is a fixed value, i.e., the gate oxide layer 300 employed in the present disclosure has a single thickness. The gate oxide layer 300 having a constant thickness helps to reduce the processing difficulty and processing cost of the semiconductor device. The gate oxide layer 300 may be formed, for example, by an oxide of silicon, which may include, but is not limited to, silicon dioxide. For a depletion transistor, the gate oxide layer 300 is doped with metal ions having conductivity opposite to that of the transistor. For NMOS, for example, the gate oxide layer 300 may be doped with positively charged metal ions, so that the channel under the gate oxide layer 300 induces electrons when the gate voltage is 0, and vice versa.

The word line 400 is used to connect with the gate 200. The word line 400 may be made of a conductive material, which may include, but is not limited to, doped polysilicon, metals (e.g., tungsten, tantalum, etc.), silicides, etc. (e.g., alloys of metals and polysilicon).

The bit line 500 is used to connect to the source 201 and/or the drain 202, and the bit line 500 of the antifuse memory cell in the present embodiment is connected to both the source 201 and the drain 202. The bit line 500 may be fabricated using at least one of a doped semiconductor material (e.g., doped silicon or doped germanium), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), a metal (e.g., tungsten, titanium, or tantalum), and/or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide).

The Contact 600 may be formed on the source 201 and the drain 202, and the Contact 600 in the present disclosure is a bit line Contact (Bitline Contact). Specifically, bit line 500 is connected to contact 600, and contact 600 may be fabricated from the same material as bit line 500. The contact portion 600 of the present embodiment is used to connect the bit line 500 to the source 201 and the drain 202, respectively, and the source 201 and the drain 202 of one transistor share the same bit line.

As shown in FIG. 3, the antifuse memory cell may further include a Sense Amplifier (SA) 900. The sense amplifier 900 is used to convert the resistance value of the gate oxide layer into a logic output (e.g., "1" or "0") to determine whether the gate oxide layer is broken down, and the sense amplifier 900 of the present disclosure is connected to the bit line 500.

Other embodiments of the present disclosure may provide an electronic device that may include an antifuse memory cell of any of the embodiments of the present disclosure. A semiconductor device on an electronic device may include one or more antifuse memory arrays formed of antifuse memory cells of the present disclosure. The electronic device may include, but is not limited to, a smart phone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source, and the like.

A method of writing an antifuse memory cell in some embodiments of the present disclosure may include, but is not limited to, one or more of the following.

The antifuse memory cells in any embodiment of the present disclosure are provided, and the embodiment takes the antifuse memory cells in the third row and the third column in fig. 3 (the target memory cell in the dashed box, where the third word line WL3 crosses the third bit line BL 3) as an example.

A first preset voltage is applied to the word line WL3 of the target memory cell and a second preset voltage is applied to the bit line BL3 of the target memory cell. The difference value between the first preset voltage and the second preset voltage is larger than a first threshold value so as to break down the gate oxide layer and reduce the resistance value of the gate oxide layer, and writing '1' into the anti-fuse memory unit is realized.

In specific implementation, the first preset voltage used in the present disclosure is higher than the power supply voltage, the second preset voltage is zero voltage or negative voltage, and the first threshold is the power supply voltage. The present embodiment applies a power supply Voltage (VDD) to all the word lines 400 and the bit lines 500 before applying a first preset voltage to the word lines of the target memory cell.

Or applying a third preset voltage to the word line of the target memory cell and applying a fourth preset voltage to the bit line of the target memory cell. And the difference value of the third preset voltage and the fourth preset voltage is smaller than the second threshold value so as to prevent the gate oxide layer from being broken down and the resistance value of the gate oxide layer from being unchanged, and write '0' into the anti-fuse memory unit. In other words, the antifuse memory cells of the present disclosure store a "0" by default.

In specific implementation, the third preset voltage used in the present disclosure is a power supply voltage or a zero voltage, the fourth preset voltage is a zero voltage (the fourth preset voltage may be a negative voltage when the third preset voltage is a zero voltage), and the second threshold is a power supply voltage. The present embodiment applies a power supply Voltage (VDD) to all the word lines 400 and the bit lines 500 before applying a first preset voltage to the word lines of the target memory cell.

A method of reading an antifuse memory cell in some embodiments of the present disclosure may include, but is not limited to, one or more of the following steps.

The antifuse memory cells in any embodiment of the present disclosure are provided, and the embodiment takes the antifuse memory cells in the third row and the third column (the target memory cells in the dashed box) in fig. 3 as an example.

A power supply Voltage (VDD) is applied to the bit lines, and a ground Voltage (VSS) is applied to the word lines.

The current logic voltage on the bit line is obtained. The present embodiment may output a current logic voltage "0" or "1" by detecting and amplifying a voltage through a sense amplifier 900 connected to a bit line.

When the current logic voltage is "1", the data stored on the antifuse memory cell is "0". Alternatively, when the current logic voltage is "0", the data stored on the antifuse memory cell is "1".

Other embodiments of the present disclosure provide a method for reading an antifuse memory cell, which may include, but is not limited to, one or more of the following.

The antifuse memory cells in any embodiment of the present disclosure are provided, and the embodiment takes the antifuse memory cells in the third row and the third column (the target memory cells in the dashed box) in fig. 3 as an example.

A power supply Voltage (VDD) is applied to the bit lines, and a ground Voltage (VSS) is applied to the word lines.

The amount of charge on the bit line is acquired. The present embodiment can determine whether the amount of charge on the bit line has changed by detecting and amplifying the current through the sense amplifier 900 connected to the bit line. It should be understood that the present disclosure may also determine whether the data stored on the antifuse memory cell is "0" or "1" by current.

When the amount of charge on the bit line is unchanged, the data stored on the antifuse memory cell is "0"; alternatively, when the amount of charge on the bit line decreases, the data stored on the antifuse memory cell is "1".

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (10)

1. An antifuse memory cell, comprising:

the transistor comprises a semiconductor substrate, a first electrode, a second electrode and a third electrode, wherein a transistor is formed on the semiconductor substrate and comprises a grid electrode, a source electrode and a drain electrode;

the gate oxide layer is arranged between the semiconductor substrate and the grid electrode, and the thickness of the gate oxide layer is a fixed value;

a word line connected to the gate;

a bit line connected with the source and/or the drain.

2. The antifuse memory cell of claim 1,

the transistor is a depletion transistor.

3. The antifuse memory cell of claim 1, further comprising:

and a contact portion formed on the source electrode and the drain electrode, the bit line being connected to the contact portion.

4. The antifuse memory cell of claim 1, further comprising:

and the sensitive amplifier is connected with the bit line.

5. An electronic device comprising the antifuse memory cell of any one of claims 1 to 4.

6. The electronic device of claim 5, comprising a smartphone, a computer, a tablet, a wearable smart device, an artificial smart device, a mobile power source.

7. A method of writing to an antifuse memory cell, comprising:

providing an antifuse memory cell as claimed in any one of claims 1 to 4;

applying a first preset voltage to a word line and applying a second preset voltage to the bit line; the difference value between the first preset voltage and the second preset voltage is larger than a first threshold value so as to break down the gate oxide layer and write '1' into the anti-fuse memory unit; alternatively, the first and second electrodes may be,

applying a third preset voltage to the word line and a fourth preset voltage to the bit line; and the difference value of the third preset voltage and the fourth preset voltage is smaller than a second threshold value so as to prevent the gate oxide layer from being broken down and write '0' into the anti-fuse memory unit.

8. The method of writing to an antifuse memory cell according to claim 7,

the first preset voltage is higher than the power supply voltage;

the second preset voltage is zero voltage or negative voltage;

the first threshold is a power supply voltage;

the third preset voltage is power supply voltage or zero voltage;

the fourth preset voltage is zero voltage;

the second threshold is a supply voltage.

9. A method of reading an antifuse memory cell, comprising:

providing an antifuse memory cell of any of claims 1 to 4;

applying a power supply voltage to the bit line and applying a ground voltage to the word line;

acquiring a current logic voltage on a bit line;

when the current logic voltage is '1', the data stored on the antifuse memory cell is '0'; alternatively, the first and second electrodes may be,

when the current logic voltage is "0", the data stored on the antifuse memory cell is "1".

10. A method of reading an antifuse memory cell, comprising:

providing an antifuse memory cell as claimed in any one of claims 1 to 4;

applying a power supply voltage to the bit line and applying a ground voltage to the word line;

acquiring the charge quantity on the bit line;

when the amount of charge on the bit line is unchanged, the data stored on the antifuse memory cell is "0"; alternatively, the first and second electrodes may be,

as the amount of charge on the bit line decreases, the data stored on the antifuse memory cell is a "1".

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