CN114695346A

CN114695346A - Bootstrap diode and semiconductor device

Info

Publication number: CN114695346A
Application number: CN202110654057.3A
Authority: CN
Inventors: 陈柏安
Original assignee: Nuvoton Technology Corp
Current assignee: Nuvoton Technology Corp
Priority date: 2020-12-30
Filing date: 2021-06-11
Publication date: 2022-07-01
Also published as: TW202226603A; TWI763220B

Abstract

A bootstrap diode including a bootstrap cathode terminal and a bootstrap anode terminal includes a junction field effect transistor, a P-type transistor and a diode. The junction field effect transistor comprises a first gate terminal coupled to a ground terminal, a first source/drain terminal and a second source/drain terminal coupled to the bootstrap cathode terminal. The P-type transistor includes a second gate terminal coupled to the ground terminal, a third source/drain terminal coupled to the ground terminal, and a fourth source/drain terminal coupled to the bootstrap anode terminal. The diode includes a cathode terminal coupled to the first source/drain terminal of the junction field effect transistor and an anode terminal coupled to the bootstrap anode terminal. The circuit helps to reduce the complexity and the circuit area of the circuit, can provide considerable forward conduction current, resists higher reverse bias, and remarkably reduces the current from electric leakage to the substrate.

Description

Bootstrap diode and semiconductor device

Technical Field

The present invention relates to a bootstrap diode, and more particularly to a bootstrap diode composed of a Junction Field-Effect Transistor (JFET), a P-type Transistor and a diode.

Background

Increasing energy efficiency is becoming more and more important, and among them, off-line power converters that can reduce power consumption are becoming more and more important. In response to market changes, high-voltage integrated circuit (HVIC) chips with higher performance and economic benefits have been gradually adopted, so that designers have flexible solutions when implementing high-performance power converters.

The High-voltage integrated circuit chip functions as a gate driver, for example, for driving a power Metal Oxide Semiconductor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT), wherein a bootstrap diode (bootstrap diode), a capacitor, a resistor, and the like are generally used to form a bootstrap circuit, and a voltage level of the High-voltage integrated circuit is provided with reference to a floating level of a source voltage of the power metal oxide semiconductor of the upper bridge circuit (High-Side circuit).

However, the bootstrap diode has a disadvantage of leaking current to the semiconductor substrate when conducting in the forward direction. Moreover, the general bootstrap diode cannot bear high voltage, and when the reverse bias voltage of the bootstrap diode is too high, the bootstrap diode is broken down and conducted, and the purpose of unidirectional conduction of the bootstrap diode cannot be achieved. Therefore, it is necessary to optimize the leakage and breakdown voltage levels of the bootstrap diode and to increase the on-current in forward conduction.

Disclosure of Invention

The present invention herein proposes a semiconductor device as a bootstrap diode. The semiconductor device provided by the invention does not need additional circuit control, thereby being beneficial to reducing the complexity of the circuit and the area of the circuit. Moreover, the semiconductor device provided by the invention can provide considerable forward conduction current, resist higher reverse bias voltage and obviously reduce the current leaked to the substrate.

In view of the above, the present invention provides a bootstrap diode, which includes a bootstrap cathode terminal and a bootstrap anode terminal. The bootstrap diode includes a junction field effect transistor, a P-type transistor and a diode. The jfet includes a first gate terminal coupled to a ground terminal, a first source/drain terminal, and a second source/drain terminal coupled to the bootstrap cathode terminal. The P-type transistor includes a second gate terminal coupled to the ground terminal, a third source/drain terminal coupled to the ground terminal, and a fourth source/drain terminal coupled to the bootstrap anode terminal. The diode includes a cathode terminal coupled to the first source/drain terminal and an anode terminal coupled to the bootstrap anode terminal.

According to an embodiment of the present invention, the bootstrap diode further includes a substrate, a first N-well, a first buried N-layer, a second buried N-layer, and a second N-well. The first N-type well is formed in the substrate. The first N-type buried layer is formed over the first N-type well. The second N-type buried layer is formed over the first N-type well, wherein a gap is formed between the first N-type buried layer and the second N-type buried layer. The second N-well is formed over the first N-buried layer and the second N-buried layer, wherein the jfet, the P-transistor, and the diode are formed in the second N-well.

According to an embodiment of the present invention, the bootstrap diode further includes a first P-well, a second P-well, a first P-doped region, a third N-well and a first N-doped region. The first P-well is formed in the second N-well and above the gap. The second P-well is formed in the first P-well. The first P-type doped region is formed in the second P-type well, wherein the first P-type doped region forms the first gate terminal. The third N-well is formed in the second N-well and is located at one side of the first P-well. The first N-type doped region is formed in the third N-type well, wherein the first N-type doped region forms the second source/drain terminal, and wherein the second N-type well forms the first source/drain terminal.

According to an embodiment of the present invention, the bootstrap diode further includes a third P-well, a second P-doped region, a first P-drift region, a second P-drift region and a gate structure. The third P-well is formed in the second N-well, wherein the third P-well and the third N-well are respectively located on two different sides of the first P-well. The second P-type doped region is formed in the third P-type well, wherein the second P-type doped region forms the fourth source/drain terminal. The first P-type drift region is formed in the second N-type well and located between the first P-type doped region and the second P-type doped region, wherein the first P-type drift region is connected to the second P-type doped region. The second P-type drift region is formed between the first P-type doped region and the first N-type doped region. The gate structure is formed over the first P-type drift region and adjacent to the first P-type doped region, wherein the gate structure forms the second gate terminal, wherein the first P-type doped region also forms the third source/drain terminal.

According to an embodiment of the invention, the second P-type doped region forms an anode terminal of the diode, and the second N-type well forms a cathode terminal of the diode.

According to another embodiment of the present invention, the bootstrap diode further comprises a P-type buried layer. The P-type buried layer is formed in the gap between the first N-type buried layer and the second N-type buried layer.

According to another embodiment of the present invention, the bootstrap diode further comprises a fourth P-well. The fourth P-well is formed in the first N-well and below the gap.

The present invention further provides a semiconductor device, which includes a substrate, a first N-well, a first N-buried layer, a second N-well, a first P-doped region, a first N-doped region, a second P-doped region, and a gate structure. The first N-type well is formed in the substrate. The first N-type buried layer is formed over the first N-type well. The second N-type buried layer is formed over the first N-type well, wherein a gap is formed between the first N-type buried layer and the second N-type buried layer. The second N-well is formed over the first and second buried N-type layers, wherein the second N-well forms a first source/drain terminal of a junction field effect transistor therein. The first P-type doped region is formed in the second N-well and above the gap, wherein the first P-type doped region forms a first gate terminal of the jfet and a third source/drain terminal of a P-type transistor, wherein the first P-type doped region is coupled to a ground terminal. The first N-type doped region is formed in the second N-type well, wherein the first N-type doped region forms a second source/drain terminal of the JFET. The second P-type doped region is formed in the second N-well, wherein the first N-type doped region and the second P-type doped region are respectively located at two different sides of the first P-type doped region, and wherein the second P-type doped region forms a fourth source/drain terminal of the P-type transistor. The gate structure is formed on the second N-well, between the first P-type doped region and the second P-type doped region and adjacent to the first P-type doped region, wherein the gate structure forms a second gate terminal of the P-type transistor and is coupled to the ground terminal.

According to an embodiment of the present invention, the second P-type doped region forms an anode terminal of a diode, and the second N-type well forms a cathode terminal of the diode.

According to an embodiment of the present invention, the second P-type doped region is coupled to a first node, and the first N-type doped region is coupled to a second node, wherein the semiconductor device provides the voltage of the first node to the second node when the voltage of the first node exceeds the voltage of the second node.

According to another embodiment of the present invention, when the voltage of the second node exceeds the voltage of the first node, the semiconductor device electrically isolates the first node from the second node.

According to an embodiment of the present invention, the semiconductor device further includes a first P-well, a second P-well, a third N-well, a third P-well, a first P-drift region and a second P-drift region. The first P-well is formed in the second N-well. The second P-well is formed in the first P-well, wherein the first P-doped region is formed in the second P-well. The third N-well is formed in the second N-well, wherein the first N-doped region is formed in the third N-well. The third P-well is formed in the second N-well, wherein the second P-doped region is formed in the third P-well. The first P-type drift region is formed in the second N-type well and under the gate structure, wherein the first P-type drift region is connected to the second P-type doped region. The second P-type drift region is formed between the first P-type doped region and the first N-type doped region.

According to another embodiment of the present invention, the semiconductor device further comprises a P-type buried layer. The P-type buried layer is formed in the gap between the first N-type buried layer and the second N-type buried layer.

According to another embodiment of the present invention, the semiconductor device further comprises a fourth P-well. The fourth P-well is formed in the first N-well and below the gap.

Drawings

Fig. 1 shows a circuit diagram of a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a block diagram of a power driving circuit according to an embodiment of the invention;

fig. 3 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention;

fig. 4 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention; and

fig. 5 is a cross-sectional view of a semiconductor device according to another embodiment of the invention.

[ notation ] to show

100,300,400,500 semiconductor device

110 junction field effect transistor

120P-type transistor

130: diode

N1 first node

N2 second node

NA anode terminal

NC is cathode terminal

G1 first gate terminal

G2 second Gate terminal

S1/D1 first Source/Drain terminal

S2/D2 second source/drain terminal

S3/D3 third Source/Drain terminal

S4/D4 fourth Source/Drain terminal

200 power driving circuit

210 lower bridge driver

220 upper bridge driver

MHS upper bridge transistor

Lower bridge transistor of MLS

SO output signal

SLD drive signal

CBT bootstrap capacitor

VBT bootstrap voltage

VDD supply voltage

VH upper bridge voltage

HV external voltage

Substrate of PSUB

NW1 first N-type well

NBL1 first N type buried layer

NBL2 second N-type buried layer

NW2 second N-type well

NW3 third N-type well

S is the distance between

PW1 first P-type well

PW2 second P-type well

PW3 third P-type well

311 first P-type doped region

312 first N-type doped region

313 second P-type doped region

321 first P-type drift region

322 second P-type drift region

331: gate structure

341 first isolation Structure

342 a second isolation structure

343 third isolation Structure

344 fourth isolation Structure

PBL P-type buried layer

PW4 fourth P-type well

Detailed Description

The following describes an element substrate, a semiconductor device, and a method for manufacturing a semiconductor device according to some embodiments of the present application in detail. It is to be understood that the following description provides many different embodiments, or examples, for implementing different aspects of embodiments of the application. The specific elements and arrangements described below are merely illustrative of some embodiments of the disclosure for simplicity and clarity. These are, of course, merely examples and are not intended to be limiting of the application. Moreover, repeated reference numerals or designations may be used in various embodiments. These iterations are merely provided for simplicity and clarity in describing some embodiments of the present application and are not intended to represent any interrelationships between the various embodiments and/or structures discussed. Furthermore, when a first material layer is located on or above a second material layer, the first material layer and the second material layer are in direct contact. Alternatively, one or more further layers of material may be provided, in which case there may not be direct contact between the first and second layers of material.

Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used in embodiments to describe one element's relative relationship to another element of the drawings. It will be understood that if the device in the figures is turned over, elements described as being on the "lower" side would then be elements on the "upper" side if the device were turned over.

As used herein, the term "about", "about" or "substantially" generally means within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The amounts given herein are approximate, that is, the meanings of "about", "about" and "about" may be implied without specifically stating "about", "about" or "about".

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms, and these terms are only used to distinguish one element, component, region, layer and/or section from another element, component, region, layer and/or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of some embodiments of the present application.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present application and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Some embodiments of the present application can be understood together with the drawings, which are considered a part of the description of the embodiments of the present application. It is to be understood that the drawings of the embodiments of the present application are not necessarily drawn to scale of actual devices or elements. The shape and thickness of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present application. In addition, the structures and devices in the drawings are shown schematically in order to clearly illustrate the features of the embodiments of the present application.

In some embodiments of the present application, relative terms such as "lower," "upper," "horizontal," "vertical," "lower," "above," "top," "bottom," and the like are to be understood as referring to the segment and the orientation depicted in the associated drawings. These relative terms are for convenience of description only and do not imply that the described apparatus should be constructed or operated in a particular orientation. Terms concerning bonding, connecting, such as "connected," "interconnected," and the like, may refer to two structures as being in direct contact, or may refer to two structures as being not in direct contact, unless otherwise specified, with another structure being interposed between the two structures. And the terms coupled and connected should also be construed to include both structures being movable or both structures being fixed.

Embodiments of the present invention are disclosed in the context of semiconductor devices, and may be embodied in Integrated Circuits (ICs) such as microprocessors, memory devices, and/or other devices. The integrated circuit may also include various passive and active microelectronic components such as thin-film resistors (MIMCAPs), inductors, diodes, Metal-Oxide-Semiconductor field-effect transistors (MOSFETs), complementary MOS transistors, Bipolar Junction Transistors (BJTs), laterally diffused MOS transistors, high-power MOS transistors, or other types of transistors. One of ordinary skill in the art will appreciate that semiconductor devices may also be used to include other types of semiconductor devices in integrated circuits.

Fig. 1 shows a circuit diagram of a semiconductor device according to an embodiment of the invention. As shown in fig. 1, the semiconductor device 100 includes a junction field effect transistor 110, a P-type transistor 120, and a diode 130. According to an embodiment of the present invention, the semiconductor device 100 is configured as a bootstrap diode, and has the characteristics of low substrate leakage and high reverse voltage (i.e., when the voltage at the second node N2 is much larger than the voltage at the first node N1), and also has a high forward conduction current, which will be described in detail below.

As shown in fig. 1, the semiconductor device 100 further includes a first node N1 and a second node N2. According to an embodiment of the present invention, when the voltage of the first node N1 exceeds the voltage of the second node N2, the semiconductor device 100 supplies the voltage of the first node N1 to the second node N2. According to another embodiment of the present invention, the semiconductor device 100 is configured to electrically isolate the first node N1 and the second node N2 when the voltage of the second node N2 exceeds the voltage of the first node N1. According to an embodiment of the invention, when the semiconductor device 100 is used as a bootstrap diode, the first node N1 is an anode terminal of the bootstrap diode, and the second node N2 is a cathode terminal of the bootstrap diode.

The junction field effect transistor 110 includes a first source/drain terminal S1/D1, a second source/drain terminal S2/D2, and a first gate terminal G1, wherein the first gate terminal G1 is coupled to ground, and the second source/drain terminal S2/D2 is coupled to a second node N2. According to an embodiment of the invention, as shown in FIG. 1, the JFET 110 is an N-type JFET.

The P-type transistor 120 includes a third source/drain terminal S3/D3, a fourth source/drain terminal S4/D4 and a second gate terminal G2, wherein the third source/drain terminal S3/D3 and the second gate terminal G2 are both coupled to ground, and the fourth source/drain terminal S4/D4 is coupled to the first node N1. The diode 130 includes an anode terminal NA coupled to the first node N1 and the fourth source/drain terminal S4/D4, and a cathode terminal NC coupled to the first source/drain terminal S1/D1.

According to an embodiment of the present invention, when the semiconductor device 100 is a bootstrap diode and the voltage of the first node N1 exceeds the voltage of the second node N2, the jfet 110 and the P-type transistor 120 are both turned on, so that the current flows from the first node N1 to the second node N2 through the channels of the P-type transistor 120 and the jfet 110. According to another embodiment of the present invention, when the voltage at the second node N2 exceeds the voltage at the first node N1, the jfet 110 and the P-type transistor 120 are both off, and the second source/drain terminals S2/D2 are configured to withstand the high reverse voltage received by the second node N2.

Fig. 2 is a block diagram of a power driving circuit according to an embodiment of the invention. As shown in fig. 2, the power driving circuit 200 is configured to alternately turn on the upper bridge transistor MHS and the lower bridge transistor MLS to generate the output signal SO, wherein the supply voltage VDD is smaller than the external voltage HV. Power driver circuit 200 includes a lower bridge driver 210, semiconductor device 100, bootstrap capacitor CBT, and an upper bridge driver 220.

According to an embodiment of the present invention, the lower bridge driver 210 outputs the lower bridge driving signal SLD, such that the lower bridge transistor MLS is turned on and the upper bridge transistor MHS is turned off according to the signal SLD of the lower bridge driver, and pulls the output signal SO to ground. Meanwhile, the supply voltage VDD charges the bootstrap capacitor CBT through the semiconductor device 100, so that the bootstrap capacitor CBT generates a bootstrap voltage VBT, wherein the bootstrap voltage VBT does not exceed the supply voltage VDD.

According to another embodiment of the present invention, when the lower bridge transistor MLS is turned off and the upper bridge transistor MHS is turned on according to the lower bridge driving signal SLD of the lower bridge driver 210, the output signal SO is pulled up to the external voltage HV, and the bootstrap capacitor CBT boosts the upper bridge voltage VH to the sum of the bootstrap voltage VBT and the external voltage HV, SO that the upper bridge driver 220 can completely turn on the upper bridge transistor MHS. In addition, the semiconductor device 100 is turned off to electrically isolate the upper bridge voltage VH from the supply voltage VDD.

Therefore, the semiconductor device 100 can operate by itself without control of a control circuit, which is advantageous for reducing the complexity of the circuit and reducing the circuit area, and the voltage endurance of the second source/drain terminals S2/D2 of the jfet 110 is much higher than that of a general diode, so that the semiconductor device 100 can withstand a higher reverse bias voltage than the general diode.

Fig. 3 is a cross-sectional view of a semiconductor device according to an embodiment of the invention. As shown in fig. 3, the semiconductor device 300 includes a substrate PSUB, a first N-type well NW1, a first N-type buried layer NBL1, a second N-type buried layer NBL2, and a second N-type well NW 2.

The substrate PSUB is P-type, the first N-type well NW1 is formed in the substrate PSUB, the first N-type buried layer NBL1 and the second N-type buried layer NBL2 are formed on the first N-type well NW1, wherein a space S is formed between the first N-type buried layer NBL1 and the second N-type buried layer NBL 2. The present invention does not limit the formation method of the first and second N-type buried layers NBL1 and NBL 2. According to an embodiment of the invention, the first and second N-type buried layers NBL1 and NBL2 may be formed by an ion implantation step. For example, phosphorus ions or arsenic ions may be implanted into a region where the first and second N-type buried layers NBL1 and NBL2 are to be formed to form the first and second N-type buried layers NBL1 and NBL2 of N-type.

The second N-well NW2 is formed over the first N-type buried layer NBL1 and the second N-type buried layer NBL2, wherein the junction field effect transistor 110, the P-type transistor 120, and the diode 130 of fig. 1 are formed in the second N-well NW 2. According to an embodiment of the present invention, the impurity concentrations of the first and second N-type buried layers NBL1 and NBL2 are higher than the impurity concentration of the first and second N-type wells NW1 and NW 2. According to an embodiment of the invention, the first N-well NW1 is a Pre-drift region doping (Pre-HVNW). According to an embodiment of the invention, the second N-well NW2 is a high-pressure well or epitaxial layer.

As shown in fig. 3, the semiconductor device 300 further includes a first P-well PW1, a second P-well PW2, a first P-doped region 311, a third N-well NW3, a first N-doped region 312, a third P-well PW3, a second P-doped region 313, a first P-drift region 321, a second P-drift region 322, and a gate structure 331.

The first P-well PW1 is formed in the second N-well NW2 and located above the distance S, the second P-well PW2 is formed in the first P-well PW1, and the first P-doped region 311 is formed in the second P-well PW 2. According to one embodiment of the present invention, the first P-well PW1 is a high-pressure well. According to an embodiment of the invention, the doping concentration of the second P-type well PW2 is higher than that of the first P-type well PW 1. According to an embodiment of the invention, the first P-type doped region 311 forms the first gate terminal G1 of the junction field effect transistor 110 of fig. 1 and the third source/drain terminal S3/D3 of the P-type transistor 120.

The third N-well NW3 is formed in the second N-well NW2 and is located at one side of the first P-well PW 1. The first N-type doped region 312 is formed in the third N-type well NW 3. According to an embodiment of the invention, the first N-type doped region 312 is used to form the second source/drain terminals S2/D2 of the junction field effect transistor 110 of FIG. 1, and the second N-type well NW2 forms the first source/drain terminals S1/D1 of the junction field effect transistor 110 of FIG. 1.

The third P-well PW3 is formed in the second N-well NW2, wherein the third P-well PW3 and the third N-well NW3 are respectively located at two different sides of the first P-well PW 1. A second P-type doped region 313 is formed in the third P-type well PW 3. According to an embodiment of the present invention, the second P-type doped region 313 forms the fourth source/drain terminal S4/D4 of the P-type transistor 120 of FIG. 1.

According to an embodiment of the present invention, the second P-type doped region 313 forms the anode terminal NA of the diode 130 of fig. 1, and the second N-type well NW2 forms the cathode terminal NC of the diode 130 of fig. 1. In other words, the junctions of the third P-well PW3 and the second N-well NW2 form the diode 130 of fig. 1.

The first P-type drift region 321 is formed in the second N-well NW2 and located between the first P-type doped region 311 and the second P-type doped region 313. According to an embodiment of the present invention, the first P type drift region 321 and the second P type doped region 313 are connected to each other. According to another embodiment of the present invention, the first P-type drift region 321 may also be interconnected with a third P-type well PW 3.

The second P-type drift region 322 is formed between the first P-type doped region 311 and the first N-type doped region 312. According to an embodiment of the present invention, the second P type drift region 322 is connected to the first N type doped region 312. According to another embodiment of the present invention, the second P type drift region 322 is connected to a third N type well NW 3. According to another embodiment of the present invention, the second P type drift region 322 is separated from the first N type doped region 312 or the third N type well NW 3.

The gate structure 331 is formed on the first P-type drift region 321 and adjacent to the first P-type doped region 311. According to an embodiment of the invention, the gate structure 331 forms the second gate terminal G2 of the P-type transistor 120 of FIG. 1.

The semiconductor device 300 further includes a first isolation structure 341, a second isolation structure 342, a third isolation structure 343, and a fourth isolation structure 344. The first isolation structure 341 is adjacent to the second P-type doped region 313 for isolating the second P-type doped region 313 from other devices. As shown in fig. 3, the first isolation structure 341 directly contacts the second P-type doped region 313, but is not limited to the invention. According to other embodiments of the present invention, the first isolation structure 341 does not contact the second P-type doped region 313.

The second isolation structure 342 is located on the first P-type doped region 311 and the second P-type doped region 313 and above the first P-type drift region 321. According to an embodiment of the present invention, the gate structure 331 covers the second isolation structure 342. As shown in fig. 3, the second isolation structure 342 directly contacts the second P-type doped region 313 and is far away from the first P-type doped region 311, but the invention is not limited thereto. According to other embodiments of the present invention, the second isolation structure 342 does not contact the second P-type doped region 313.

The third isolation structure 343 is located between the first P-type doped region 311 and the first N-type doped region 312 and above the second P-type drift region 322. As shown in fig. 3, the third isolation structure 343 directly contacts the first P-type doped region 311 and the first N-type doped region 312, but is not limited thereto. According to other embodiments of the present invention, the third isolation structure 343 does not contact the first P-type doped region 311 and/or the first N-type doped region 312.

As shown in fig. 3, the first P-type doped region 311 and the gate structure 331 are electrically connected to the ground terminal through an interconnect structure (not shown in fig. 3), the first N-type doped region 312 is electrically connected to the second node N2 through an interconnect structure (not shown in fig. 3), and the second P-type doped region 313 is electrically connected to the first node N1 of fig. 1 through an interconnect structure (not shown in fig. 3). According to an embodiment of the present invention, the semiconductor device 300 corresponds to the semiconductor device 100 of fig. 1.

In other words, the second N-well NW2, the first P-type doped region 311, and the first N-type doped region 312 form the junction field effect transistor 110 of fig. 1, the first P-type doped region 311, the gate structure 331, and the second P-type doped region 313 form the P-type transistor 120 of fig. 1, and the second P-type doped region 313 and the second N-well NW2 form the diode 130 of fig. 1. According to an embodiment of the invention, the space S between the first N-type buried layer NBL1 and the second N-type buried layer NBL2 helps to pinch off the channel of the jfet 110 of fig. 1, so as to improve the performance of the semiconductor device 300 in reverse bias.

According to an embodiment of the present invention, when the first P-type doped region 313 leaks to the substrate PSUB, the first P-type doped region 313, the N-type well (including the first N-type well NW1, the second N-type well NW2 and the parasitic PNP transistor of the substrate PSUB) must be turned on, and the current gain of the parasitic PNP transistor is reduced due to the deeper depth of the N-type well formed by the first N-type well NW1, the first N-type buried layer NBL1, the second N-type buried layer NBL2 and the second N-type well NW2, which is helpful for reducing the magnitude of the leakage current of the second P-type doped region 313 to the substrate PSUB.

According to an embodiment of the present invention, when the voltage of the first node N1 exceeds the voltage of the second node N2, a current flows from the first node N1 through the second P-type doped region 313 and the first P-type drift region 321, turning on the P-type transistor, and flows through the first P-well PW1, the second P-type drift region 322, and the second N-type doped region 312 to the second node N2, so that a considerable forward conduction current can be obtained.

According to another embodiment of the present invention, when the voltage of the second node N2 exceeds the voltage of the first node N1, the depletion regions generated by the first P-well PW1 and the second N-well NW2, the first N-type buried layer NBL1 and the second N-type buried layer NBL2 sandwich the channel, so that the current cannot flow from the second node N2 to the first node N1.

Fig. 4 is a cross-sectional view of a semiconductor device according to another embodiment of the invention. Comparing the semiconductor apparatus 300 of fig. 3 with the semiconductor apparatus 400 of fig. 4, the semiconductor apparatus 400 further includes a P-type buried layer PBL. As shown in fig. 4, the P-type buried layer PBL is located between the first N-type buried layer NBL1 and the second N-type buried layer NBL2, that is, the P-type buried layer PBL fills the space of the space S.

According to an embodiment of the invention, the P-type buried layer PBL helps to adjust the clamp voltage of the junction field effect transistor 110 of fig. 1. According to another embodiment of the present invention, when the semiconductor device 400 is forward biased, that is, when the voltage of the first node N1 exceeds the voltage of the second node N2, the second P-type doped region 313, the second N-type well NW2, the P-type buried layer PBL, the first N-type well NW1 and the substrate PSUB form a PNPNP structure, which helps to further reduce the magnitude of leakage current from the second P-type doped region 313 to the substrate PSUB.

Fig. 5 is a cross-sectional view of a semiconductor device according to another embodiment of the invention. In comparison with the semiconductor device 500 in fig. 5, in the semiconductor device 300 in fig. 3, the semiconductor device 500 further includes a fourth P-well PW 4. As shown in fig. 5, the fourth P-well PW4 is located below the first N-type buried layer NBL1 and the second N-type buried layer NBL2, and is used to fill the gap S.

According to an embodiment of the invention, the fourth P-well PW4 is helpful for adjusting the clamp voltage of the jfet 110 of fig. 1. According to another embodiment of the present invention, when the semiconductor device 500 is forward biased, that is, when the voltage of the first node N1 exceeds the voltage of the second node N2, the second P-type doped region 313, the second N-type well NW2, the fourth P-type well PW4, the first N-type well NW1 and the substrate PSUB form a PNPNP structure, which helps to further reduce the magnitude of leakage current from the second P-type doped region 313 to the substrate PSUB.

Although the embodiments of the present application and their advantages have been disclosed, it should be understood that various changes, substitutions and alterations can be made herein by those skilled in the art without departing from the spirit and scope of the application. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but rather, the process, machine, manufacture, composition of matter, means, methods and steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein. Accordingly, the scope of the present application includes the processes, machines, manufacture, compositions of matter, means, methods, and steps described above. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present application also includes combinations of the respective claims and embodiments.

Claims

1. A bootstrap diode, comprising a bootstrap cathode terminal and a bootstrap anode terminal, wherein the bootstrap diode comprises:

a junction field effect transistor including a first gate terminal coupled to a ground terminal, a first source/drain terminal, and a second source/drain terminal coupled to the bootstrap cathode terminal;

a P-type transistor including a second gate terminal coupled to the ground terminal, a third source/drain terminal coupled to the ground terminal, and a fourth source/drain terminal coupled to the bootstrap anode terminal; and

a diode including a cathode terminal coupled to the first source/drain terminal and an anode terminal coupled to the bootstrap anode terminal.

2. The bootstrap diode of claim 1, further comprising:

a substrate;

a first N-well formed in the substrate;

a first N-type buried layer formed over the first N-type well;

a second N-type buried layer formed over the first N-type well, wherein a gap is provided between the first N-type buried layer and the second N-type buried layer; and

a second N-well formed over the first and second buried N-layers, wherein the JFET, the P-type transistor, and the diode are formed in the second N-well.

3. The bootstrap diode of claim 2, further comprising:

a first P-well formed in the second N-well and above the gap;

a second P-well formed in the first P-well;

a first P-type doped region formed in the second P-type well, wherein the first P-type doped region forms the first gate terminal;

a third N-well formed in the second N-well and located at one side of the first P-well; and

a first N-type doped region formed in the third N-type well, wherein the first N-type doped region forms the second source/drain terminal, wherein the second N-type well forms the first source/drain terminal.

4. The bootstrap diode of claim 3, further comprising:

a third P-well formed in the second N-well, wherein the third P-well and the third N-well are respectively located on two different sides of the first P-well;

a second P-type doped region formed in the third P-type well, wherein the second P-type doped region forms the fourth source/drain terminal;

a first P-type drift region formed in the second N-type well and located between the first P-type doped region and the second P-type doped region, wherein the first P-type drift region is connected with the second P-type doped region;

a second P-type drift region formed between the first P-type doped region and the first N-type doped region; and

a gate structure formed over the first P-type drift region and adjacent to the first P-type doped region, wherein the gate structure forms the second gate terminal, wherein the first P-type doped region also forms the third source/drain terminal.

5. The bootstrapped diode of claim 4, wherein the second P-type doped region forms an anode terminal of the diode, and the second N-type well forms a cathode terminal of the diode.

6. The bootstrap diode of claim 4, further comprising:

a P-type buried layer formed in the gap between the first N-type buried layer and the second N-type buried layer.

7. The bootstrap diode of claim 4, further comprising:

a fourth P-well formed in the first N-well and below the gap.

8. A semiconductor device, comprising:

a substrate;

a first N-well formed in the substrate;

a first N-type buried layer formed over the first N-type well;

a second N-type buried layer formed over the first N-type well, wherein a gap is provided between the first N-type buried layer and the second N-type buried layer;

a second N-well formed over the first and second buried N-type layers, wherein the second N-well has a first source/drain terminal of a junction field effect transistor formed therein;

a first P-type doped region formed in the second N-well and above the gap, wherein the first P-type doped region forms a first gate terminal of the jfet and a third source/drain terminal of a P-type transistor, wherein the first P-type doped region is coupled to a ground terminal;

a first N-type doped region formed in the second N-type well, wherein the first N-type doped region forms a second source/drain terminal of the junction field effect transistor;

a second P-type doped region formed in the second N-well, wherein the first N-type doped region and the second P-type doped region are respectively located at two different sides of the first P-type doped region, and wherein the second P-type doped region forms a fourth source/drain terminal of the P-type transistor; and

a gate structure formed over the second N-well between and adjacent to the first P-doped region and the second P-doped region, wherein the gate structure forms a second gate terminal of the P-transistor and is coupled to the ground terminal.

9. The semiconductor device of claim 8, wherein the second P-type doped region forms an anode terminal of a diode and the second N-type well forms a cathode terminal of the diode.

10. The semiconductor device of claim 9, wherein the second P-type doped region is coupled to a first node and the first N-type doped region is coupled to a second node, wherein the semiconductor device provides the voltage of the first node to the second node when the voltage of the first node exceeds the voltage of the second node.

11. The semiconductor device according to claim 10, wherein when the voltage of the second node exceeds the voltage of the first node, the semiconductor device electrically isolates the first node from the second node.

12. The semiconductor device according to claim 8, further comprising:

a first P-well formed in the second N-well;

a second P-well formed in the first P-well, wherein the first P-doped region is formed in the second P-well;

a third N-well formed in the second N-well, wherein the first N-doped region is formed in the third N-well;

a third P-well formed in the second N-well, wherein the second P-doped region is formed in the third P-well;

a first P-type drift region formed in the second N-type well and located under the gate structure, wherein the first P-type drift region is connected to the second P-type doped region; and

and the second P-type drift region is formed between the first P-type doped region and the first N-type doped region.

13. The semiconductor device according to claim 12, further comprising:

14. The semiconductor device according to claim 12, further comprising:

a fourth P-well formed in the first N-well and below the gap.