CN114694709A

CN114694709A - Anti-power-consumption-attack storage unit based on digital mechanism

Info

Publication number: CN114694709A
Application number: CN202210344123.1A
Authority: CN
Inventors: 余水月; 叶俊; 邢根
Original assignee: Anhui University
Current assignee: Anhui University
Priority date: 2022-03-31
Filing date: 2022-03-31
Publication date: 2022-07-01

Abstract

The invention discloses a digital mechanism-based power attack resistant storage unit, which consists of a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first phase inverter, a second phase inverter, a third phase inverter, a first transmission gate and a second transmission gate. The power consumption attack resistant storage unit based on the digital mechanism can improve the side channel attack resistant capability of a unit circuit, can greatly improve the stability of the unit under the condition of sacrificing smaller unit area, and reduces the power consumption of the unit.

Description

Anti-power-consumption-attack storage unit based on digital mechanism

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a power-attack-resistant storage unit based on a digital mechanism.

Background

Today, Side Channel Attack (SCA) has become a serious threat to security systems because it can extract confidential data by analyzing the current consumed by the system power plane. Static Random Access Memory (SRAM), a key component of these security systems, is the primary subject of attacks. As shown in fig. 1, a conventional SRAM cell (referred to as a 6T cell for short) composed of 6 transistors has proven to be vulnerable to side channel attacks. When writing to a conventional 6T cell, the power consumption resulting from the write operation varies depending on the data stored inside the cell. The attacker obtains the original data information stored inside the unit by analyzing the correlation between the write power consumption and the internally stored data.

As different side channel attack patterns emerge endlessly, a series of side channel attack resistant techniques also appear in succession. The prior art mainly comprises the following schemes:

fig. 2 shows a 7T architecture proposed by Robert Giterman in 2019 to resist power consumption attacks. It adds a "balance tube" (PMOS transistor P3 in FIG. 2) between two storage nodes Q and QN based on the conventional 6T structure. The write operation of the 7T structure is divided into two phases: a balance phase and a write phase. The balance stage enables a balance pipe to pull the levels of the two storage nodes to the same level, so that the correlation between original storage data and write power consumption is eliminated, and the aim of resisting side channel attack is fulfilled. However, the 7T structure has problems of large write power consumption, significant delay of write operation, and low write speed.

Shown in fig. 3 as V.

An 8T structure against side channel attack was proposed in 2012. Two NMOS transistors (NMOS transistors N5 and N6 in FIG. 3) are added between the two coupled inverters of the structure for cutting off feedback. The write operation of the structure is also divided into two stages, in the balance stage, the CUT signal is pulled down, the positive feedback between the two storage nodes Q and QN is broken, at the moment, the level of the two storage nodes is pulled down to '0' at the same time because the bit line BL/BLB is at a low level, so that the influence of original data is eliminated, the correlation between write power consumption and internal original data is reduced, and the purpose of resisting side channel attack is achieved.

The existing side channel attack resisting technology still has the problems of large power consumption, low writing speed, interference caused by half-selection problem and low noise tolerance.

Disclosure of Invention

In view of the above disadvantages of the prior art, the present invention provides a digital mechanism-based storage unit for resisting power attack, which is used to solve the problems of large power consumption, low writing speed, interference from half-select problem and low noise margin of the static random access memory unit in the prior art.

To achieve the above and other related objects, the present invention provides a digital mechanism-based storage unit for resisting power attack, including:

the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, the second NMOS transistor, the first inverter, the second inverter, the third inverter, the first transmission gate and the second transmission gate;

the source electrode of the first PMOS transistor is connected with a power supply, the drain electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor, and the grid electrode of the first PMOS transistor is connected with the output end of the first phase inverter, the input end of the third phase inverter, the grid electrode of the second NMOS transistor and the input end of the second phase inverter; the grid electrode of the second PMOS transistor is connected with a first write word line, and the drain electrode of the second PMOS transistor is respectively connected with the drain electrode of the first NMOS transistor, the input end of the first phase inverter and the output end of the second phase inverter; the grid electrode of the first NMOS transistor is connected with a second write word line, the drain electrode of the second NMOS transistor is connected with the source electrode of the first NMOS transistor, and the source electrode of the second NMOS transistor is grounded; the output end of the third inverter is connected with a first bit line through the first transmission gate; the input end of the second inverter is connected with a second bit line through a second transmission gate;

a first control end of the first transmission gate is connected with a first read word line, and a second control end of the first transmission gate is connected with a second read word line; and a first control end of the second transmission gate is connected with the first writing bit line, and a second control end of the second transmission gate is connected with the second writing bit line.

In an alternative embodiment, the first write word line and the second write word line are used to provide a pair of opposite control signals.

In an alternative embodiment, the first read wordline and the second read wordline are used to provide a pair of opposing control signals.

In an alternative embodiment, the first write bit line and the second write bit line are used to provide a pair of opposing control signals.

In an alternative embodiment, the first transmission gate is a CMOS transmission gate.

In an alternative embodiment, the second transmission gate is a CMOS transmission gate.

In an optional embodiment, the first inverter, the second inverter, and the third inverter are CMOS inverters.

In an alternative embodiment, in the hold phase, the first bit line and the second bit line are both precharged to a high level, the first write bit line is at a low level, the second write bit line is at a high level, the first read word line is at a low level, the second read word line is at a high level, the first write word line is at a low level, and the second write word line is at a high level.

In an alternative embodiment, in the read data phase, the first bit line is precharged to a high level, the first read word line is at a high level, the second read word line is at a low level, the first write word line is at a low level, and the second write word line is at a high level.

In an optional embodiment, in the data writing phase, the first write bit line is at a high level, the second write bit line is at a low level, the first write word line is at a high level, the second write word line is at a low level, and the second bit line is at a high level or a low level.

The digital mechanism-based power consumption attack resisting storage unit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first phase inverter, a second phase inverter, a third phase inverter, a first transmission gate and a second transmission gate, can improve the stability of the storage unit and the side channel attack resisting capacity of the unit, can greatly improve the writing speed of the unit under the condition of sacrificing small unit area, and reduces the power consumption of the unit.

Drawings

Fig. 1 is a schematic structural diagram of a 6T circuit in the prior art.

Fig. 2 is a schematic structural diagram of a 7T circuit in the prior art.

Fig. 3 is a schematic structural diagram of an 8T circuit in the prior art.

Fig. 4 is a schematic structural diagram of a digital mechanism-based storage unit for resisting power consumption attack according to an embodiment of the present invention;

fig. 5 is a timing waveform diagram of a digital mechanism-based memory cell circuit with resistance to power consumption attack according to an embodiment of the present invention.

Wherein: 0.5ns-1.5ns is a write "0" operation, 1.5ns-2.5ns is a read "0" operation, 2.5sn-3.5ns is a write "1" operation, 3.5ns-4.5ns is a read "1" operation, and 4.5ns-5.5ns is hold (simulation conditions: Corner: TT; Temperature: 27 ℃; VDD: 0.9V).

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1-5. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

As shown in fig. 4, the present embodiment provides a digital mechanism-based power Attack resistant storage unit, which is a unit circuit structure that can be applied to an ultra-low voltage system and that improves the resistance of the unit to Side Channel Attack (SCA). The digital mechanism-based power attack resistant storage unit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first phase inverter 10, a second phase inverter 20, a third phase inverter 30, a first transmission gate 40 and a second transmission gate 50. The source electrode of the first PMOS transistor is connected with a power supply, the drain electrode of the first PMOS transistor is connected with the source electrode of the second PMOS transistor, and the gate electrode of the first PMOS transistor is connected with the output end of the first inverter 10, the input end of the third inverter 30, the gate electrode of the second NMOS transistor and the input end of the second inverter 20; the gate of the second PMOS transistor is connected to the first write word line, and the drain of the second PMOS transistor is connected to the drain of the first NMOS transistor, the input terminal of the first inverter 10, and the output terminal of the second inverter 20, respectively; the grid electrode of the first NMOS transistor is connected with a second write word line, the drain electrode of the second NMOS transistor is connected with the source electrode of the first NMOS transistor, and the source electrode of the second NMOS transistor is grounded; the output terminal of the third inverter 30 is connected to a first bit line through the first transmission gate 40; the input terminal of the second inverter 20 is connected to a second bit line through a second transmission gate 50; a first control terminal of the first transmission gate 40 is connected to a first read word line, and a second control terminal of the first transmission gate 40 is connected to a second read word line; a first control terminal of the second transmission gate 50 is connected to a first write bit line, and a second control terminal of the second transmission gate 50 is connected to a second write bit line.

As shown in fig. 4, the first inverter 10, the second inverter 20, and the third inverter 30 are all CMOS inverters formed by a PMOS transistor and an NMOS transistor, and the first transmission gate 40 and the second transmission gate 50 are CMOS transmission gates formed by a PMOS transistor and an NMOS transistor connected in parallel. It is understood that, in other embodiments, the first inverter 10, the second inverter 20, and the third inverter 30 may also be replaced by an NMOS inverter, a PMOS inverter, a TTL inverter, or other inverters, and the first transmission gate 40 and the second transmission gate 50 may also be transmission gates formed by a pair of triodes with opposite polarities.

Specifically, the digital mechanism-based power attack resistant memory cell shown in fig. 4 is a 14T digital structure SRAM memory cell, which is hereinafter referred to as a DIGIT-14T. The DIGIT-14T includes: seven NMOS transistors and seven PMOS transistors; the seven NMOS transistors are sequentially marked as N1-N7, and the seven PMOS transistors are sequentially marked as P1-P7; the drain of the PMOS transistor P1 (as a first PMOS transistor) is connected to the source of the PMOS transistor P2 (as a second PMOS transistor), and the PMOS transistors P1 and P2 are pull-up transistors, the source of the NMOS transistor N1 (as a first NMOS transistor) 0 is connected to the drain of the NMOS transistor N2 (as a second NMOS transistor), and the NMOS transistors N1 and N2 are pull-down transistors; the NMOS transistor N3 and the PMOS transistor P3 constitute one CMOS inverter (as the first inverter 10), the NMOS transistor N4 and the PMOS transistor P4 constitute another CMOS inverter (as the second inverter 20), and the two inverters are cross-coupled; the NMOS transistor N6 and the PMOS transistor P6 form a CMOS transfer gate (as the second transfer gate 50), and the main storage node Q is connected to the bit line BLB (as the second bit line) through the second transfer gate 50; the NMOS transistor N5 and the PMOS transistor P5 constitute yet another CMOS inverter (as the third inverter 30), the NMOS transistor N7 and the PMOS transistor P7 constitute another CMOS transmission gate (as the first transmission gate 40), and the main storage node QN is connected to the read bit line RBL (as the first read bit line) through the third inverter 30 and the first transmission gate 40; wherein: PMOS transistor P2 and NMOS transistor N1 are controlled by write word line WWLB (as second write word line) and WWL (as first write word line), respectively, PMOS transistor P6 and NMOS transistor N6 are controlled by write bit line WBLB (as second write bit line) and WBL (as first write bit line), respectively, and NMOS transistor N7 and PMOS transistor P7 are controlled by word line RWL (as first read word line) and RWLB (as second read word line), respectively.

The bit line BLB is electrically connected with the drains of the NMOS transistor N6 and the PMOS transistor P6, respectively; a write bit line WBL electrically connected to the gate of NMOS transistor N6, and a write bit line WBLB electrically connected to the gate of PMOS transistor N6; the bit line RBL is electrically connected with the sources of the NMOS transistor N7 and the PMOS transistor P7 respectively; the read word line RWL is electrically connected to the gate of the NMOS transistor N7; the read word line RWLB is electrically connected to the gate of the PMOS transistor P7; the power supply VDD is electrically connected with the source electrode of the PMOS transistor P1, the source electrode of the PMOS transistor P3, the source electrode of the PMOS transistor P4 and the source electrode of the PMOS transistor P5; the source of NMOS transistor N2, the source of NMOS transistor N3, the source of NMOS transistor N4, and the source of NMOS transistor N5 are grounded.

The drain of PMOS transistor P1 is electrically connected to the source of PMOS transistor P2, and the gate of PMOS transistor P1 is electrically connected to the gate of NMOS transistor N2, the drain of PMOS transistor P3, the drain of NMOS transistor N3, the gate of PMOS transistor P4, the gate of NMOS transistor N4, the gate of PMOS transistor P5, the gate of NMOS transistor N5, the gate of NMOS transistor N2, the source of NMOS transistor N6, and the source of PMOS transistor P6; the drain electrode of the PMOS transistor P2 is electrically connected with the drain electrode of the NMOS transistor N1, the gate electrode of the PMOS transistor P3, the gate electrode of the NMOS transistor N3, the drain electrode of the PMOS transistor P4 and the drain electrode of the NMOS transistor N4, and the gate electrode of the PMOS transistor P2 is electrically connected with a write word line WWLB; the source of the NMOS transistor N1 is electrically connected to the drain of the NMOS transistor N2, and the gate of the NMOS transistor N1 is electrically connected to the write word line WWL.

The working principle of the DIGIT-14T memory cell provided by the embodiment of the invention is as follows: write bit lines WBL, WBLB always form a pair of opposite control signals, read word lines RWL, RWLB always form a pair of opposite control signals, and write word lines WWL, WWLB always form a pair of opposite control signals.

In the holding stage, bit lines RBL and BLB are precharged to high level, write bit lines WBL and WBLB are precharged to low level and high level, read word lines RWL and RWLB are precharged to low level and high level, write word lines WWL and WWLB are precharged to low level and high level, respectively, the internal state of the circuit is maintained, and the circuit does not work.

When the bit line RBL is precharged to a high level in a data reading stage, the read word lines RWL, RWLB are respectively at a high level and a low level, the write word lines WWL, WWLB are respectively at a low level and a high level, the write bit lines WBL, WBLB are respectively at a low level and a high level, and the NMOS transistor N7 and the PMOS transistor P7 constituting the first transfer gate 40 are turned on; if the unit circuit stores data of '0', Q is 0, QN is 1; then RBL passes through the discharge path: the first transfer gate 40 formed by the NMOS transistor N7 and the PMOS transistor P7, the NMOS transistor N5, discharges to ground, causing the bit line RBL voltage to decrease; if the unit circuit stores data of ' 1 ', Q is 1 and QN is 0 ', the power supply VDD passes through a charging path: the second transmission gate 50 of the PMOS transistor P5, the PMOS transistor P7, and the NMOS transistor N7 charges the bit line RBL, so that the bit line RBL voltage rises.

In the data writing phase, the write bit lines WBL, WBLB are high and low respectively, the write word lines WWL, WWLB are high and low respectively, and if the bit line BLB is high, '1' is written to the storage node QN through the second transmission gate 50 composed of the NMOS transistor N6 and the PMOS transistor P6; if the bit line BLB is low, '0' is written to the storage node QN through the second transmission gate 50 consisting of the NMOS transistor N6 and the PMOS transistor P6. In the writing process, the PMOS transistor P1, the PMOS transistor P2, the NMOS transistor N1, and the NMOS transistor N2 form an inverter between the two storage nodes Q and QN, so that the data of the storage nodes is more easily inverted, and the writing capability of the memory cell is greatly improved.

The storage unit adopts a digital structure on a reading path and a writing path, and the reading and writing operations are carried out in a digital mode, so that the anti-interference capability of the storage unit is greatly improved, and the storage unit can stably run under extremely low voltage. Although the number of single unit transistors is increased by 1.3 times compared with the number of traditional 6T transistors, the digitalized operation mode enables the analog part in the traditional SRAM circuit to be eliminated in consideration of the whole system, and the area consumption caused by the increase of the number of single unit transistors is compensated to a certain extent.

The principle of the DIGIT-14T memory cell provided by this embodiment against side channel attack is as follows: the original 6T structure shown in FIG. 1 is composed of a positive feedback loop composed of only two inverters, and such a structure enables the 6T SRAM to have good holding capability, i.e. high holding noise tolerance. The DIGIT-14T of this embodiment also has such a structure, and is a cross-coupled structure of the first inverter 10 formed by the PMOS transistor P3 and the NMOS transistor N3 and the first inverter 10 formed by the PMOS transistor P4 and the NMOS transistor N4 in fig. 4. However, for 6T, a good feedback loop makes overwriting the data difficult. As shown in fig. 1, when the storage node Q stores data of "0", if "0" is still written next time, i.e., BL is 0 and BLB is 1, data in the feedback loop is not changed, the operation is easy and the power consumption is very small; if "1" is written to the storage node Q next time, that is, BL is 1 and BLB is 0, the data in the feedback loop needs to be changed, and at this time, there is a voltage difference between BL and the storage node Q, and a current is generated through N1, so that BL will raise the voltage of the storage node Q. However, the level of the storage node QN is still not "0" although it is decreased, so that P1 is still turned off and N2 is still turned on, thereby generating a feedback effect, and N2 pulls down the level of the storage node Q to keep the original storage data in the feedback loop unchanged. Although the data of the storage node Q can be finally rewritten due to the strong pull action of the BL and BLB, in this process, the operation is difficult due to the influence of the feedback loop, and the power consumption of the operation mode of the analog circuit is relatively large, so that the power consumption for rewriting the data to be "1" is much higher than the power consumption for writing "0". In the DIGIT-14T of the present embodiment, the storage node Q is directly rewritten by adding the PMOS transistor P1, the PMOS transistor P2, the NMOS transistor N1, and the NMOS transistor N2, and although the storage nodes Q and QN are still restricted by the feedback loop, the PMOS transistor P1, the PMOS transistor P2, the NMOS transistor N1, and the NMOS transistor N2 are a digital writing method, and the writing effect is not reduced by the influence of the storage node QN, so that the DIGIT-14T is less influenced by the original data and the power consumption is also less when data is rewritten.

At present, the SRAM cell structure that is the best against power consumption attack is the 7T structure in fig. 2, and it achieves the effect that the power consumption is close to that of writing "1" or "0" by cutting off the feedback loop in the first stage to perform data balance and rewriting data in the second stage. In fact, this is to amplify the power consumption, and a large write power consumption is generated regardless of whether data is rewritten. Meanwhile, since the write operation is divided into two stages, the write operation of the 7T structure has a significant delay, so that the write speed is low. Although 7T has the advantage of a small number of transistors, the gate width of P3 transistor is ten times that of the transistor in DIGIT-14T in the same process, for example, 28nm process, for balancing effect.

The DIGIT-14T of the embodiment has high security, which is not only reflected in the resistance to power consumption attack, but also reflected in that the DIGIT-14T is not interfered by half-select problem and has extremely high noise tolerance. As shown in FIG. 4, first, compared to the method that only the word line switch is needed to turn on the selection during the write operation of other memory cells, the write word lines WWL and WWLB and the write bit lines WBL and WBLB need to be turned on simultaneously during the write operation of the present cell. Only when the row and the column are valid signals at the same time, the data can be effectively written, so that the row half-selection problem in the traditional 6T writing operation is avoided. Meanwhile, in the read operation, the second transmission gate 50 (formed by the NMOS transistor N6 and the PMOS transistor P6) connected to the bit line BLB is connected to the third inverter 30 (formed by the NMOS transistor N5 and the PMOS transistor P5), and the storage node cannot be affected by the fluctuation on the bit line in the column half-select due to the unidirectional transfer level of the third inverter 30, and secondly, the read noise tolerance of the DIGIT-14T is increased to the static noise tolerance of the feedback loop by the use of the third inverter 30 (see the simulation comparison table in table 1). Therefore, the DIGIT-14T of the present embodiment has various advantages of small power consumption, fast speed, simple timing and small area.

During simulation, because the DIGIT-14T circuit structure of the embodiment does not need to use MOS transistors with special sizes to maintain better performance, the minimum transistor building structure in a 28nm process library can be selected, the gate lengths of all the MOS transistors are 30nm, and the gate widths of all the MOS transistors are 100 nm.

Fig. 5 shows timing waveform diagrams at the time of simulation of the DIGIT-14T circuit of the present embodiment. Wherein: 0.5ns-1.5ns is a write "0" operation, 1.5ns-2.5ns is a read "0" operation, 2.5sn-3.5ns is a write "1" operation, 3.5ns-4.5ns is a read "1" operation, and 4.5ns-5.5ns is hold (simulation conditions: Corner: TT; Temperature: 27 ℃; VDD: 0.9V).

Table 1 shows simulated comparison tables of write time, write "0" power consumption, write "1" power consumption, attack resistance (difference between write "1" and write "0" power consumption), read noise margin RSNM and hold noise margin HSNM (simulation conditions: Corner: TT; Temperature: 27 ℃; VDD: 0.9V) for prior art SRAM cell circuits and DIGIT-14T circuits provided in this example.

Table 1 simulation comparison table

Therefore, the DIGIT-14T provided by the embodiment of the invention can improve the side channel attack resistance of the unit circuit, greatly improve the stability of the unit under the condition of sacrificing a small unit area, and reduce the power consumption of the unit.

It should be noted that the DIGIT-14T SRAM memory cell provided in the embodiment of the present invention is built by using the MOS transistor with the minimum size that can be provided in the process library, but if other sizes are selected or other transistors (such as TFET, etc.) are used to replace the transistor in the DIGIT-14T, the function of the SRAM memory cell can still be implemented to some extent. Meanwhile, in order to ensure good performance, the DIGIT-14T provided by the embodiment of the invention adopts a transmission gate, a pair of write-word lines, a pair of write-bit lines and the like which conform to the circuit structure of CMOS logic, but if the paired components are changed into a single MOS transistor, the original functions of the circuit can be realized to a certain extent.

In the description herein, numerous specific details are provided, such as examples of components and/or methods, to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention.

It will also be appreciated that one or more of the elements shown in the figures can also be implemented in a more separated or integrated manner, or even removed for inoperability in some circumstances or provided for usefulness in accordance with a particular application.

Additionally, any reference arrows in the drawings/figures should be considered only as exemplary, and not limiting, unless otherwise expressly specified. Further, as used herein, the term "or" is generally intended to mean "and/or" unless otherwise indicated. Combinations of components or steps will also be considered as being noted where terminology is foreseen as rendering the ability to separate or combine is unclear.

The above description of illustrated embodiments of the invention, including what is described in the abstract of the specification, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention, as those skilled in the relevant art will recognize and appreciate. As indicated, these modifications may be made to the present invention in light of the foregoing description of illustrated embodiments of the present invention and are to be included within the spirit and scope of the present invention.

The systems and methods have been described herein in general terms as the details aid in understanding the invention. Furthermore, various specific details have been given to provide a general understanding of the embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, and/or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.

Thus, although the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosures, and it will be appreciated that in some instances some features of the invention will be employed without a corresponding use of other features without departing from the scope and spirit of the invention as set forth. Thus, many modifications may be made to adapt a particular situation or material to the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular terms used in following claims and/or to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include any and all embodiments and equivalents falling within the scope of the appended claims. Accordingly, the scope of the invention is to be determined solely by the appended claims.

Claims

1. A digital mechanism-based storage unit for resisting power consumption attack, comprising:

2. The digital mechanism-based power attack resistant memory cell of claim 1 wherein the first write word line and the second write word line are configured to provide a pair of opposing control signals.

3. The digital mechanism-based power attack resistant memory cell of claim 1 wherein the first read wordline and the second read wordline are configured to provide a pair of opposing control signals.

4. The digital mechanism-based power attack resistant memory cell of claim 1, wherein a first write bit line and the second write bit line are used to provide a pair of opposing control signals.

5. The digital mechanism-based power attack resistant memory cell of claim 1, wherein the first transmission gate is a CMOS transmission gate.

6. The digital mechanism-based power attack resistant memory cell of claim 1, wherein the second transmission gate is a CMOS transmission gate.

7. The digital mechanism-based storage unit for resisting power consumption attack according to claim 1, wherein the first inverter, the second inverter and the third inverter are CMOS inverters.

8. The digital mechanism-based power attack resistant memory cell of claim 1 wherein during a hold phase, the first bitline and the second bitline are both precharged high, the first write bitline is low, the second write bitline is high, the first read wordline is low, the second read wordline is high, the first write wordline is low, and the second write wordline is high.

9. The digital mechanism-based power attack resistant memory cell of claim 1 wherein during a read data phase, the first bit line is precharged to a high level, the first read word line is at a high level, the second read word line is at a low level, the first write word line is at a low level, and the second write word line is at a high level.

10. The digital mechanism-based power attack resistant memory cell of claim 1 wherein during a write data phase, the first write bit line is high, the second write bit line is low, the first write word line is high, the second write word line is low, and the second write bit line is either high or low.