CN114691584B - SM1 encryption and decryption device based on PCIE interface high-speed data stream - Google Patents
SM1 encryption and decryption device based on PCIE interface high-speed data stream Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- H04L9/0819—Key transport or distribution, i.e. key establishment techniques where one party creates or otherwise obtains a secret value, and securely transfers it to the other(s)
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Abstract
The invention discloses an SM1 encryption and decryption device based on a PCIE interface high-speed data stream, which comprises a first processing unit; the PCIE output high-speed data stream interface processing flow is used for carrying out PCIE output high-speed data stream interface processing flow; a second processing unit; the key independent processing flow is used for sharing the multi-core SM1 algorithm; a third processing unit; the method is used for performing multi-core data processing flow for meeting PCIE high-speed data.
Description
Technical Field
The invention relates to the technical field of data processing, in particular to an SM1 encryption and decryption device based on a PCIE interface high-speed data stream.
Background
With the development of big data, artificial intelligence, cloud computing and other fields, the high-speed hardware requirements in the server become more urgent, and PCIE transmission technology is used as a ubiquitous I/O interconnection solution, and becomes a mainstream solution of a server bus.
While high-speed data develop, the safety demand is also increasing, especially in the security industry field in the artificial intelligence of novel infrastructure construction, 5G network car networking application field and industry internet field, these fields are based on the high-speed data under the safety premise, so slow safe hardware device becomes the bottleneck of developing at present.
In the current use process of large data volume, based on multiple users, the multi-thread scheduling use is the main flow requirement of current application, and an application layer needs a hardware device to support multi-hardware scheduling of a software layer and multi-thread parallel operation.
Therefore, under the condition of high-speed data flow and multi-user multi-threading, for the slow encryption and decryption algorithm SM1, a hardware solution is needed to be found, so that the requirements of multiple users and the requirement of high-speed data volume are met.
Disclosure of Invention
The invention aims to provide an SM1 encryption and decryption device based on a PCIE interface high-speed data stream, thereby solving the problems in the prior art.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
an SM1 encryption and decryption device based on PCIE interface high-speed data flow, the device comprises,
a first processing unit; the PCIE output high-speed data stream interface processing flow is used for carrying out PCIE output high-speed data stream interface processing flow;
a second processing unit; the key independent processing flow is used for sharing the multi-core SM1 algorithm;
a third processing unit; the method is used for performing multi-core data processing flow for meeting PCIE high-speed data.
Preferably, the PCIE output high-speed data stream interface processing procedure specifically includes,
s11, acquiring plaintext data and control data to be processed from a PCIE interface, and moving the plaintext data and the control data to be processed into a storage space inside the device by adopting DMA;
s12, the device automatically detects plaintext data from the storage space and analyzes accompanying information of the plaintext data; the accompanying information comprises encryption and decryption instructions of plaintext data, SM1 operation round number instructions and control instructions including encryption and decryption mode instructions;
s13, after the device analysis is completed, reading the plaintext data from the storage space, and starting to distribute data flow for operation according to a control instruction of the plaintext data;
and S14, after the device finishes the operation, storing the ciphertext data obtained by the operation into a storage space, and informing the PCIE interface to transmit.
Preferably, in the multi-core data processing flow for satisfying PCIE high-speed data, a plurality of algorithm cores can work independently at the same time and enjoy independent data storage spaces; the multi-core data processing flow for meeting the PCIE high-speed data specifically comprises the following contents,
s21, generating an accompanying Tag for each path of data in the data stream, wherein the accompanying Tag comprises state information of a plurality of algorithm cores and length information of the data;
s22, according to whether the information to be processed exists in the accompanying Tag, an idle algorithm core is allocated to the accompanying Tag, and the idle algorithm core calls an SM1 algorithm to carry out operation processing.
Preferably, S21 specifically includes the following,
s211, inputting data from a PCIE interface by a data stream, and detecting the data in a storage space by a device;
s212, carrying out data statistics according to the pointer written in the storage space;
s213, recording initial address pointers of the written data, and associating state information of a plurality of algorithm cores;
s214, according to the state information of a plurality of algorithm cores, the numbers of the algorithm cores in an idle state, the initial address of data and the length information of the data are generated to generate accompanying tags in a fixed format;
s215, each algorithm core processes the initial address of the data into data with the length larger than 0 according to the accompanying Tag in the fixed format.
Preferably, S22 specifically includes the following,
s221, inquiring data length information in the accompanying Tag format, wherein if the length is greater than 0, the information to be processed is indicated;
s222, inquiring an idle state index table for recording state information of a plurality of algorithm cores, setting the algorithm core in an idle state as a busy state, and distributing an address accompanied with information to be processed in the Tag to the algorithm core, wherein the algorithm core calls an SM1 algorithm for processing; if all algorithm cores in the idle state index table are busy, polling and inquiring are carried out every other period until the algorithm cores in the idle state are inquired;
s223, when the data processing distributed to the algorithm core is finished, after receiving the signal of finishing the processing, updating the idle state index table.
Preferably, in S222, the algorithm core in the idle state is queried according to the index number of the idle state index table in a fixed priority manner.
Preferably, the third processing unit is divided into a data processing unit, a key processing unit and a storage interface unit;
the data processing unit solves the encryption flow operation, divides the functions of large internal data processing occupation resources and long processing period into independent data processing units according to the multi-core requirement, and is arranged in a pipelining mode, so that the data processing unit is convenient for multi-core data pipelining and multi-core data management;
the key processing unit solves the key generation, and a plurality of data processing units share one key processing unit according to the multi-core requirement, and the key processing unit is arranged in a pipelining mode, so that multi-core data management is facilitated;
the storage interface unit is used for solving the problem of data storage and reading, according to the multi-core requirement, the data processing unit stores the original data address into the accompanying Tag when the data is stored, each algorithm core has the corresponding accompanying Tag, after the data processing is finished, the mode of covering the original data is adopted, the address information index in the accompanying Tag is kept unchanged, and the content in the index is changed from the original data into encrypted and decrypted data.
Preferably, the key independent processing flow shared by the multi-core SM1 algorithm specifically includes that a plurality of algorithm cores share a key processing unit, the key processing unit reads key data from a storage space according to a key address index of each algorithm core to perform related key operation, and the key operation result is issued to the algorithm core.
The beneficial effects of the invention are as follows: 1. the control of the encryption module by the processor (cpu) is simplified, and the processor only needs to configure the addresses of the data to be processed and the related control information, so that the device can automatically carry out data movement. 2. The multi-core synchronous processing data capacity is met, and the operation efficiency is improved. 3. The use of a separate key generation module reduces the logical resource consumption of key generation. 4. After the operation is finished, the dmas are automatically written back to the memory area of the data processor, so that the data movement is more efficient, and the processor is easier to process.
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Fig. 1 is a schematic diagram of an apparatus in an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the detailed description is presented by way of example only and is not intended to limit the invention.
As shown in fig. 1, in this embodiment, an SM1 encryption and decryption device based on PCIE interface high-speed data stream is provided, where the device includes,
a first processing unit; the PCIE output high-speed data stream interface processing flow is used for carrying out PCIE output high-speed data stream interface processing flow;
a second processing unit; the key independent processing flow is used for sharing the multi-core SM1 algorithm;
a third processing unit; the method is used for performing multi-core data processing flow for meeting PCIE high-speed data.
In this embodiment, the PCIE output high-speed data stream interface processing procedure specifically includes the following content,
s11, acquiring plaintext data and control data to be processed from a PCIE interface, and moving the plaintext data and the control data to be processed into a storage space inside the device by adopting DMA;
s12, the device automatically detects plaintext data from the storage space and analyzes accompanying information of the plaintext data; the accompanying information comprises control instructions such as encryption and decryption instructions of plaintext data, SM1 operation round number instructions, encryption and decryption mode instructions and the like;
s13, after the device analysis is completed, reading the plaintext data from the storage space, and starting to distribute data flow for operation according to a control instruction of the plaintext data;
and S14, after the device finishes the operation, storing the ciphertext data obtained by the operation into a storage space, and informing the PCIE interface to transmit.
In this embodiment, in the multi-core data processing flow performed to meet PCIE high-speed data, multiple algorithm cores may work independently at the same time and enjoy independent data storage spaces; the multi-core data processing flow for meeting the PCIE high-speed data specifically comprises the following contents,
s21, generating an accompanying Tag for each path of data in the data stream, wherein the accompanying Tag comprises state information of a plurality of algorithm cores and length information of the data;
s22, according to whether the information to be processed exists in the accompanying Tag, an idle algorithm core is allocated to the accompanying Tag, and the idle algorithm core calls an SM1 algorithm to carry out operation processing.
In this embodiment, S21 specifically includes the following,
s211, inputting data from a PCIE interface by a data stream, and detecting the data in a storage space by a device;
s212, carrying out data statistics according to the pointer written in the storage space;
s213, recording initial address pointers of the written data, and associating state information of a plurality of algorithm cores;
s214, according to the state information of a plurality of algorithm cores, the numbers of the algorithm cores in an idle state, the initial address of data and the length information of the data are generated to generate accompanying tags in a fixed format;
s215, each algorithm core processes the initial address of the data into data with the length larger than 0 according to the accompanying Tag in the fixed format.
In this embodiment, S22 specifically includes the following,
s221, inquiring data length information in the accompanying Tag format, wherein if the length is greater than 0, the information to be processed is indicated;
s222, inquiring an idle state index table for recording state information of a plurality of algorithm cores, setting the algorithm core in an idle state as a busy state, and distributing an address accompanied with information to be processed (with the length more than 0) in the Tag to the algorithm core, wherein the algorithm core calls an SM1 algorithm for processing; if all algorithm cores in the idle state index table are busy, polling and inquiring are carried out every other period until the algorithm cores in the idle state are inquired;
s223, when the data processing distributed to the algorithm core is finished, after receiving the signal of finishing the processing, updating the idle state index table.
In this embodiment, in S222, the algorithm core in the idle state is queried according to the index number of the idle state index table in a fixed priority manner.
In the embodiment, on the basis of the traditional SM1 algorithm, three independent structures are designed according to the multi-core processing requirement, so that the principles of minimum resources and priority of performance are met; the third processing unit is thus divided into a data processing unit, a key processing unit and a storage interface unit;
the data processing unit solves the encryption flow operation, divides the functions of large internal data processing occupation resources and long processing period into independent data processing units according to the multi-core requirement, and is arranged in a pipelining mode, so that the data processing unit is convenient for multi-core data pipelining and multi-core data management;
the key processing unit solves the key generation, and a plurality of data processing units share one key processing unit according to the multi-core requirement, and the key processing unit is arranged in a pipelining mode, so that multi-core data management is facilitated;
the storage interface unit is used for solving the problem of data storage and reading, according to the multi-core requirement, the data processing unit stores the original data address into the accompanying Tag when the data is stored, each algorithm core is provided with a corresponding accompanying Tag (the algorithm cores are in one-to-one correspondence with the accompanying Tag), after the data processing is finished, the original data is covered, the address information index in the accompanying Tag is kept unchanged, and the content in the index is changed from the original data into encrypted and decrypted data.
In this embodiment, the key independent processing flow shared by the multi-core SM1 algorithm specifically includes that a plurality of algorithm cores share a key processing unit, and the key processing unit reads key data from a storage space according to a key address index of each algorithm core to perform related key operation, and issues a result of the key operation to the algorithm core.
By adopting the technical scheme disclosed by the invention, the following beneficial effects are obtained:
the invention provides an SM1 encryption and decryption device based on PCIE interface high-speed data flow, which simplifies the control of a processor (cpu) on an encryption module, and the processor only needs to configure addresses of data to be processed and related control information, so that equipment can automatically carry out data movement. The encryption and decryption device meets the requirement of multi-core simultaneous data processing capability, and improves operation efficiency. The encryption and decryption device uses an independent key generation module, so that the logic resource consumption of key generation is reduced. After the encryption and decryption device is operated, the dma is automatically written back to the memory area of the data processor, so that the data movement is more efficient, and the processor is easier to process.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which is also intended to be covered by the present invention.
Claims (7)
1. SM1 encryption and decryption device based on PCIE interface high-speed data stream, characterized in that: the apparatus comprises a device for the treatment of a patient,
a first processing unit; the PCIE output high-speed data stream interface processing flow is used for carrying out PCIE output high-speed data stream interface processing flow;
a second processing unit; the key independent processing flow is used for sharing the multi-core SM1 algorithm;
a third processing unit; the multi-core data processing flow is used for processing multi-core data for meeting PCIE high-speed data;
in the multi-core data processing flow for meeting PCIE high-speed data, a plurality of algorithm cores can work independently at the same time and enjoy independent data storage space; the multi-core data processing flow for meeting the PCIE high-speed data specifically comprises the following contents,
s21, generating an accompanying Tag for each path of data in the data stream, wherein the accompanying Tag comprises state information of a plurality of algorithm cores and length information of the data;
s22, according to whether the information to be processed exists in the accompanying Tag, an idle algorithm core is allocated to the accompanying Tag, and the idle algorithm core calls an SM1 algorithm to carry out operation processing.
2. The SM1 encryption and decryption device based on PCIE interface high-speed data stream of claim 1, wherein: the PCIE output high-speed data stream interface processing flow specifically includes the following contents,
s11, acquiring plaintext data and control data to be processed from a PCIE interface, and moving the plaintext data and the control data to be processed into a storage space inside the device by adopting DMA;
s12, the device automatically detects plaintext data from the storage space and analyzes accompanying information of the plaintext data; the accompanying information comprises encryption and decryption instructions of plaintext data, SM1 operation round number instructions and control instructions including encryption and decryption mode instructions;
s13, after the device analysis is completed, reading the plaintext data from the storage space, and starting to distribute data flow for operation according to a control instruction of the plaintext data;
and S14, after the device finishes the operation, storing the ciphertext data obtained by the operation into a storage space, and informing the PCIE interface to transmit.
3. The SM1 encryption and decryption device based on PCIE interface high-speed data stream of claim 1, wherein: s21 specifically includes the following,
s211, inputting data from a PCIE interface by a data stream, and detecting the data in a storage space by a device;
s212, carrying out data statistics according to the pointer written in the storage space;
s213, recording initial address pointers of the written data, and associating state information of a plurality of algorithm cores;
s214, according to the state information of a plurality of algorithm cores, the numbers of the algorithm cores in an idle state, the initial address of data and the length information of the data are generated to generate accompanying tags in a fixed format;
s215, each algorithm core processes the initial address of the data into data with the length larger than 0 according to the accompanying Tag in the fixed format.
4. The SM1 encryption and decryption device based on PCIE interface high-speed data stream according to claim 3, wherein: s22 specifically includes the following,
s221, inquiring data length information in the accompanying Tag format, wherein if the length is greater than 0, the information to be processed is indicated;
s222, inquiring an idle state index table for recording state information of a plurality of algorithm cores, setting the algorithm core in an idle state as a busy state, and distributing an address accompanied with information to be processed in the Tag to the algorithm core, wherein the algorithm core calls an SM1 algorithm for processing; if all algorithm cores in the idle state index table are busy, polling and inquiring are carried out every other period until the algorithm cores in the idle state are inquired;
s223, when the data processing distributed to the algorithm core is finished, after receiving the signal of finishing the processing, updating the idle state index table.
5. The SM1 encryption and decryption device based on PCIE interface high-speed data stream of claim 4, wherein: in S222, the algorithm core in the idle state is queried according to the index number of the idle state index table in a fixed priority manner.
6. The SM1 encryption and decryption device based on PCIE interface high-speed data stream of claim 5, wherein: dividing the third processing unit into a data processing unit, a key processing unit and a storage interface unit;
the data processing unit solves the encryption flow operation, divides the functions of large internal data processing occupation resources and long processing period into independent data processing units according to the multi-core requirement, and is arranged in a pipelining mode, so that the data processing unit is convenient for multi-core data pipelining and multi-core data management;
the key processing unit solves the key generation, and a plurality of data processing units share one key processing unit according to the multi-core requirement, and the key processing unit is arranged in a pipelining mode, so that multi-core data management is facilitated;
the storage interface unit is used for solving the problem of data storage and reading, according to the multi-core requirement, the data processing unit stores the original data address into the accompanying Tag when the data is stored, each algorithm core has the corresponding accompanying Tag, after the data processing is finished, the mode of covering the original data is adopted, the address information index in the accompanying Tag is kept unchanged, and the content in the index is changed from the original data into encrypted and decrypted data.
7. The SM1 encryption and decryption device based on PCIE interface high-speed data stream of claim 6, wherein: the key independent processing flow shared by the multi-core SM1 algorithm is characterized in that a plurality of algorithm cores share a key processing unit, the key processing unit reads key data from a storage space according to a key address index of each algorithm core to perform related key operation, and the key operation result is issued to the algorithm core.
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