CN114691552A - Low-resource memory protection device applied to RISC _ V architecture - Google Patents
Low-resource memory protection device applied to RISC _ V architecture Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
- G06F12/1483—Protection against unauthorised use of memory or access to memory by checking the subject access rights using an access-table, e.g. matrix or list
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0882—Page mode
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
Abstract
The present invention relates to a low-resource memory protection device applied to RISC _ V architecture. The low-resource memory protection device applied to the RISC _ V architecture comprises an SoC module, an address merging module, an associative memory TLB module and a PMP module which are sequentially connected; the address merging module is used for merging the instruction acquisition address and the memory access address; the associative memory TLB module is used for realizing the quick search from the virtual address to the real physical address; the PMP module is used for realizing the access authority of a physical address and instruction execution information; the SoC module is used for executing SoC programs and realizing memory protection. The low-resource memory protection device applied to the RISC _ V architecture has a simple structure, combines the instruction acquisition address and the memory access address into a virtual address, greatly reduces the internal resource application area of the TLB and PMP processing logic and the processing power consumption of the physical memory protection structure, and has higher practical value.
Description
Technical Field
The invention relates to the technical field of SoC (system on chip) memory protection, in particular to a low-resource memory protection device applied to a RISC (reduced instruction-set computer) V (reduced instruction-set computer) architecture.
Background
RISC _ V is an open source instruction set architecture that has developed very rapidly in recent years. In order to support SoC (System on Chip) security processing and fault control, the RISC _ V privileged architecture standard provides a physical memory protection PMP structure. RISC _ V supports that at most 16 physical memory protection table entries are configurable, each table entry corresponds to a 32-bit or 64-bit address field, i.e., PMPAddr 0-PMPAddr 15 registers, and 8-bit configuration registers, combined to 32-bit PMPCFG 0-PMPCFG 3 registers.
Currently, a main PMP processing structure separately determines an instruction acquisition address and a memory access address to realize rapid address validity check, but for some socs with low speed requirements and a tight resource area, a large amount of SoC resources are occupied.
Based on the above situation, the present invention provides a low-resource memory protection device applied to RISC _ V architecture.
Disclosure of Invention
In order to make up for the defects of the prior art, the invention provides a simple and efficient low-resource memory protection device applied to a RISC _ V architecture.
The invention is realized by the following technical scheme:
a low-resource memory protection device applied to RISC _ V architecture is characterized in that: the system comprises an SoC module, an address merging module, an associative memory TLB module and a PMP (physical memory protection) module which are connected in sequence;
the address merging module is used for merging the instruction acquisition address and the memory access address;
the associative memory TLB module is used for realizing the quick search from the virtual address to the real physical address;
the PMP module is used for realizing the access authority of a physical address and instruction execution information;
and the SoC module is responsible for executing SoC programs according to the real physical address fed back by the associated memory TLB module and the PMP check result so as to realize memory protection.
The address merging module merges the instruction acquisition address and the memory access address into a virtual address and generates an address type judgment signal for judging the instruction acquisition address and the memory access address;
the associative memory TLB module comprises a quick positioning page table entry and is responsible for mapping a virtual address to an actual physical address and generating instruction execution information, access permission information and address valid hit information;
when the address from the address merging module misses the quick positioning page table entry in the associative memory TLB module, the associative memory TLB module traverses all page tables to realize the mapping from the virtual address to the actual physical address;
the PMP module traverses a PMP address register through the actual physical address after receiving the actual physical address and address type judging signal, judges whether the address hits an effective physical address space, and judges instruction execution information and access permission information through the address type judging signal and a PMP configuration register;
and after the judgment is finished, feeding back the PMP check result to the associated memory TLB module and the SoC module.
The PMP module is preset with 16 address registers and 4 configuration registers, each configuration register contains 8-bit authority setting of 4 table entries, and each authority setting comprises PMP table entry register locking bits, address matching mode bits, instruction execution attribute bits, access and write attribute bits and access and read attribute bits.
For a low-resource memory protection structure, an instruction acquisition address and a memory access address which cannot be generated by the SoC module at the same time are specifically as follows:
step S1, after power-on, the SoC module configures 16 address registers and 4 configuration registers through an address bus, and starts the memory protection function;
step S2, the SoC program starts to run, generates an instruction acquisition address or a memory access address, and transmits the instruction acquisition address or the memory access address to the address merging module;
step S3, the address merging module judges the address type, if the address type is the instruction acquisition address, the address type judgment signal is high, and the output virtual address is the instruction acquisition address; otherwise, the address type judgment signal is low, and the output virtual address is a memory access address;
step S4, the associative memory TLB module traverses the internal fast positioning page table item according to the virtual address, if the traversal is hit, the real physical address is directly mapped and obtained, meanwhile, the PMP check result, namely the address effective hit information, the instruction execution information or the access permission information, is obtained according to the address type judging signal; feeding back the mapped real physical address and PMP check result to the SoC;
if the traversal is not hit, the associated memory TLB module traverses all address mapping page table entries through the virtual address to acquire a real physical address.
The PMP module judges different effective address sections under three working modes of TOR (The on Router, Onion Router), NA4 or NAPOT of The PMP module according to The address matching mode bit and The address register in The configuration register;
the PMP module acquires a real physical address transmitted by the associated memory TLB module, traverses 16 effective address fields, and judges a hit address field of the real physical address.
When the real physical address hits a certain address segment, a PMP check result, namely address valid hit information, instruction execution information or access permission information, is generated according to the address type judgment signal and the instruction execution attribute bit, the access write attribute bit and the access read attribute bit of the corresponding table entry in the configuration register; the PMP check result is fed back to the associative memory TLB module, and the associative memory TLB module updates the virtual address, the corresponding real physical address and the PMP check result to a fast positioning page table entry according to a page replacement algorithm and a strategy; meanwhile, the associative memory TLB module feeds back the real physical address and the PMP check result to the SoC module.
If any effective address field is not hit by the real physical address, the PMP module returns the miss information to the associated memory TLB module according to the current working mode of the SoC module, namely a machine mode, a user mode and a monitoring mode, and the associated memory TLB module updates the virtual address, the corresponding real physical address and the PMP check result to a fast positioning page table item according to a page replacement algorithm and a strategy; meanwhile, the associative memory TLB module feeds back the real physical address and the PMP check result to the SoC module.
The invention is applied to the low-resource memory protection device of RISC _ V framework, including SoC module, address merge module and PMP (physical memory protection) module connected sequentially;
the address transmitted by the SoC module is a real physical address, and the address output by the address merging module is a real physical address; after receiving the real physical address, the PMP module traverses all effective address segments, and feeds back PMP check results, namely address effective hit information, instruction execution information or access authority information, to the SoC module according to hit results.
The invention has the beneficial effects that: the low-resource memory protection device applied to the RISC _ V architecture has a simple structure, combines the instruction acquisition address and the memory access address into a virtual address, greatly reduces the internal resource application area of the TLB and PMP processing logic and the processing power consumption of the physical memory protection structure, and has higher practical value.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a diagram of a low-resource memory protection device applied to RISC _ V architecture according to the present invention.
FIG. 2 is a diagram illustrating a low-resource memory protection method applied to a RISC _ V architecture according to the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the embodiment of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The low-resource memory protection device applied to the RISC _ V architecture comprises an SoC module, an address merging module, an associative memory TLB module and a PMP (physical memory protection) module which are sequentially connected;
the address merging module is used for merging the instruction acquisition address and the memory access address;
the associative memory TLB module is used for realizing the quick search from the virtual address to the real physical address;
the PMP module is used for realizing the access authority of a physical address and instruction execution information;
and the SoC module is responsible for executing SoC programs according to the real physical address fed back by the associated memory TLB module and the PMP check result so as to realize memory protection.
The address merging module merges the instruction acquisition address and the memory access address into a virtual address and generates an address type judgment signal for judging the instruction acquisition address and the memory access address;
the associative memory TLB module comprises a quick positioning page table entry and is responsible for mapping a virtual address to an actual physical address and generating instruction execution information, access permission information and address valid hit information;
when the address from the address merging module misses the quick positioning page table entry in the associative memory TLB module, the associative memory TLB module traverses all page tables to realize the mapping from the virtual address to the actual physical address;
the PMP module traverses a PMP address register through the actual physical address after receiving the actual physical address and address type judging signal, judges whether the address hits an effective physical address space, and judges instruction execution information and access permission information through the address type judging signal and a PMP configuration register;
and after the judgment is finished, feeding back the PMP check result to the associated memory TLB module and the SoC module.
The PMP module is preset with 16 address registers and 4 configuration registers, each configuration register contains 8-bit authority setting of 4 table entries, and each authority setting comprises PMP table entry register locking bits, address matching mode bits, instruction execution attribute bits, access and write attribute bits and access and read attribute bits.
The PMP module is interconnected with a system bus and is responsible for realizing the read-write functions of 16 address registers and 4 configuration registers.
For a low-resource memory protection structure, an instruction acquisition address and a memory access address which cannot be generated by the SoC module at the same time are specifically as follows:
step S1, after power-on, the SoC module configures 16 address registers and 4 configuration registers through an address bus, and starts the memory protection function;
step S2, the SoC program starts to run, generates an instruction acquisition address or a memory access address, and transmits the instruction acquisition address or the memory access address to the address merging module;
step S3, the address merging module judges the address type, if the address type is the instruction acquisition address, the address type judgment signal is high, and the output virtual address is the instruction acquisition address; otherwise, the address type judgment signal is low, and the output virtual address is a memory access address;
step S4, the associative memory TLB module traverses the internal fast positioning page table item according to the virtual address, if the traversal is hit, the real physical address is directly mapped and obtained, meanwhile, the PMP check result, namely the address effective hit information, the instruction execution information or the access permission information, is obtained according to the address type judging signal; feeding back the mapped real physical address and PMP check result to the SoC;
if the traversal is not hit, the associated memory TLB module traverses all address mapping page table entries through the virtual address to obtain a real physical address.
The PMP module judges different effective address sections under three working modes of TOR (The on Router, Onion Router), NA4 or NAPOT of The PMP module according to The address matching mode bit and The address register in The configuration register;
the PMP module acquires a real physical address transmitted by the associated memory TLB module, traverses 16 effective address fields, and judges a hit address field of the real physical address.
When the real physical address hits a certain address segment, a PMP check result, namely address valid hit information, instruction execution information or access permission information, is generated according to the address type judgment signal and the instruction execution attribute bit, the access write attribute bit and the access read attribute bit of the corresponding table entry in the configuration register; the PMP check result is fed back to the associative memory TLB module, and the associative memory TLB module updates the virtual address, the corresponding real physical address and the PMP check result to a fast positioning page table entry according to a page replacement algorithm and a strategy; meanwhile, the associative memory TLB module feeds back the real physical address and the PMP check result to the SoC module.
If any effective address field is not hit by the real physical address, the PMP module returns the miss information to the associated memory TLB module according to the current working mode of the SoC module, namely a machine mode, a user mode and a monitoring mode, and the associated memory TLB module updates the virtual address, the corresponding real physical address and the PMP check result to a fast positioning page table item according to a page replacement algorithm and a strategy; meanwhile, the associative memory TLB module feeds back the real physical address and the PMP check result to the SoC module.
The page replacement algorithm and the strategy can adopt different structures such as an optimal algorithm, a first-in first-out algorithm, a recently unused algorithm and the like according to different design requirements.
The address register and the configuration register of the PMP module only use parts thereof according to design requirements, such as configuring 4 effective address fields and 8 address fields.
To achieve real-time address validity detection, the TLB module may be deleted. The low-resource memory protection device applied to the RISC _ V architecture comprises an SoC module, an address merging module and a PMP (physical memory protection) module which are sequentially connected;
the address transmitted by the SoC module is a real physical address, and the address output by the address merging module is a real physical address; after receiving the real physical address, the PMP module traverses all effective address segments, and feeds back PMP check results, namely address effective hit information, instruction execution information or access authority information, to the SoC module according to hit results.
The above-described embodiment is only one specific embodiment of the present invention, and general changes and substitutions by those skilled in the art within the technical scope of the present invention are included in the protection scope of the present invention.
Claims (8)
1. A low-resource memory protection device applied to RISC _ V architecture is characterized in that: the system comprises an SoC module, an address merging module, an associative memory TLB module and a PMP module which are connected in sequence;
the address merging module is used for merging the instruction acquisition address and the memory access address;
the associative memory TLB module is used for realizing the quick search from the virtual address to the real physical address;
the PMP module is used for realizing the access authority of a physical address and instruction execution information;
and the SoC module is responsible for executing SoC programs according to the real physical address fed back by the associated memory TLB module and the PMP check result so as to realize memory protection.
2. A low-resource memory protection device applied to RISC _ V architecture as claimed in claim 1, wherein: the address merging module merges the instruction acquisition address and the memory access address into a virtual address and generates an address type judgment signal for judging the instruction acquisition address and the memory access address;
the associative memory TLB module comprises a quick positioning page table entry and is responsible for mapping a virtual address to an actual physical address and generating instruction execution information, access permission information and address valid hit information;
when the address from the address merging module misses the quick positioning page table entry in the associative memory TLB module, the associative memory TLB module traverses all page tables to realize the mapping from the virtual address to the actual physical address;
the PMP module traverses a PMP address register through the actual physical address after receiving the actual physical address and address type judging signal, judges whether the address hits an effective physical address space, and judges instruction execution information and access permission information through the address type judging signal and a PMP configuration register;
and after the judgment is finished, feeding back the PMP check result to the associated memory TLB module and the SoC module.
3. A low-resource memory protection device applied to RISC _ V architecture as claimed in claim 2, wherein: the PMP module is preset with 16 address registers and 4 configuration registers, each configuration register contains 8-bit authority setting of 4 table entries, and each authority setting comprises PMP table entry register locking bits, address matching mode bits, instruction execution attribute bits, access and write attribute bits and access and read attribute bits.
4. A low-resource memory protection device applied to RISC _ V architecture as claimed in claim 3, wherein: for a low-resource memory protection structure, an instruction acquisition address and a memory access address which cannot be generated by the SoC module at the same time are specifically as follows:
step S1, after power-on, the SoC module configures 16 address registers and 4 configuration registers through an address bus, and starts the memory protection function;
step S2, the SoC program starts to run, generates an instruction acquisition address or a memory access address, and transmits the instruction acquisition address or the memory access address to the address merging module;
step S3, the address merging module judges the address type, if the address type is the instruction acquisition address, the address type judgment signal is high, and the output virtual address is the instruction acquisition address; otherwise, the address type judgment signal is low, and the output virtual address is a memory access address;
step S4, the associative memory TLB module traverses the internal fast positioning page table item according to the virtual address, if the traversal is hit, the real physical address is directly mapped and obtained, meanwhile, the PMP check result, namely the address effective hit information, the instruction execution information or the access permission information, is obtained according to the address type judging signal; feeding back the mapped real physical address and PMP check result to the SoC;
if the traversal is not hit, the associated memory TLB module traverses all address mapping page table entries through the virtual address to obtain a real physical address.
5. The apparatus of claim 4, wherein the memory protection device with low resource is applied to RISC _ V architecture, and is characterized in that: the PMP module judges different effective address segments under three working modes of TOR, NA4 or NAPOT of the PMP module according to an address matching mode bit and an address register in a configuration register;
the PMP module acquires a real physical address transmitted by the associated memory TLB module, traverses 16 effective address fields, and judges a hit address field of the real physical address.
6. A low-resource memory protection device applied to RISC _ V architecture as claimed in claim 5, wherein: when the real physical address hits a certain address segment, a PMP check result, namely address valid hit information, instruction execution information or access permission information, is generated according to the address type judgment signal and the instruction execution attribute bit, the access write attribute bit and the access read attribute bit of the corresponding table entry in the configuration register; the PMP check result is fed back to the associative memory TLB module, and the associative memory TLB module updates the virtual address, the corresponding real physical address and the PMP check result to a fast positioning page table entry according to a page replacement algorithm and a strategy; meanwhile, the associative memory TLB module feeds back the real physical address and the PMP check result to the SoC module.
7. A low-resource memory protection device applied to RISC _ V architecture as claimed in claim 5, wherein: if any effective address field is not hit by the real physical address, the PMP module returns the miss information to the associated memory TLB module according to the current working mode of the SoC module, namely a machine mode, a user mode and a monitoring mode, and the associated memory TLB module updates the virtual address, the corresponding real physical address and the PMP check result to a fast positioning page table item according to a page replacement algorithm and a strategy; meanwhile, the associative memory TLB module feeds back the real physical address and the PMP check result to the SoC module.
8. A low-resource memory protection device applied to RISC _ V architecture according to any of claims 1 to 7, wherein: the system comprises an SoC module, an address merging module and a PMP module which are connected in sequence;
the address transmitted by the SoC module is a real physical address, and the address output by the address merging module is a real physical address; after receiving the real physical address, the PMP module traverses all effective address segments, and feeds back PMP check results, namely address effective hit information, instruction execution information or access authority information, to the SoC module according to hit results.
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| CN202210382526.5A CN114691552A (en) | 2022-04-13 | 2022-04-13 | Low-resource memory protection device applied to RISC _ V architecture |
| PCT/CN2023/082094 WO2023197823A1 (en) | 2022-04-13 | 2023-03-17 | Low-resource memory protection apparatus applied to risc_v architecture |
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| WO2024067018A1 (en) * | 2022-09-28 | 2024-04-04 | 华为技术有限公司 | Memory management method and related device |
| CN117891510A (en) * | 2024-03-18 | 2024-04-16 | 芯来智融半导体科技(上海)有限公司 | Instruction acquisition method, apparatus, computer device and storage medium |
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| CN113569245A (en) * | 2020-04-28 | 2021-10-29 | 阿里巴巴集团控股有限公司 | Processing device, embedded system, system on chip and security control method |
| CN111651778A (en) * | 2020-05-26 | 2020-09-11 | 上海交通大学 | Physical memory isolation method based on RISC-V instruction architecture |
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| CN117891510A (en) * | 2024-03-18 | 2024-04-16 | 芯来智融半导体科技(上海)有限公司 | Instruction acquisition method, apparatus, computer device and storage medium |
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