CN114691542A - Data processing device and data access circuit thereof - Google Patents

Abstract

A data processing apparatus includes a memory circuit and a data access circuit. The memory circuit includes a plurality of cache ways for storing data. In response to a first logic state of the enable signal, the data access circuit determines that a cache hit occurs if the tag of the address of the access request is the same as the corresponding tags of the plurality of cache ways. In response to the second logic state of the enable signal, the data access circuit determines that a cache hit occurs if the address is within one or more default address intervals specified by the data access circuit, and determines that a cache miss occurs if the address is outside of the one or more default address intervals.

Description

Data processing device and data access circuit thereof

Technical Field

The present invention relates to a data processing apparatus and a data access circuit thereof, and more particularly, to a data processing apparatus and a data access circuit thereof capable of setting a cache memory as a tightly coupled memory.

Background

The processor can access the cache (cache) in one to several cycles of memory, so that the cache is often used for storing copies of data required by the processor, thereby improving the overall operation efficiency. However, the cache has limited storage space, and in some cases important data is replaced back into (episted) main memory, so that the processor needs to spend extra time retrieving the data from the main memory. Moreover, the user cannot know the address of the cache and cannot directly access the data in the cache to observe the execution state of the program.

Tightly coupled memory (also known as tightly coupled memory) is a storage device that can be accessed by a processor in one to several cycles, making it suitable for storing program code that has strict requirements on processing time, or storing data that needs to be accessed frequently. The storage space of the tightly coupled memory is mapped to a fixed address range, so that the data can be easily accessed by the user and is not replaced under normal conditions. However, tightly coupled memory is less resilient to use than cache because of address fixing.

Disclosure of Invention

A data processing apparatus includes a memory circuit and a data access circuit. The memory circuit includes a plurality of cache ways for storing data. In response to a first logic state of the enable signal, the data access circuit determines that a cache hit occurs if a tag (tag) of the access requested address is the same as a corresponding tag of the plurality of cache ways. In response to the second logic state of the enable signal, the data access circuit determines that a cache hit occurs if the address is within one or more default address intervals specified by the data access circuit, and determines that a cache miss (cache miss) occurs if the address is outside of the one or more default address intervals.

The application provides a data access circuit which is used for being coupled with a memory circuit to access the memory circuit. The memory circuit includes a plurality of cache ways for storing data. The data access circuit is used for executing the following operations: responding to a first logic state of an enabling signal, and if the label of the address of the access request is the same as the corresponding labels of the plurality of cache ways, judging that cache hit occurs; responding to a second logic state of the enabling signal, and judging that cache hit occurs if the address is located in one or more default address intervals specified by the data access circuit; in response to the second logic state of the enable signal, it is determined that a cache miss occurred if the address is outside of one or more default address intervals.

One of the advantages of the above embodiments is that the flexibility of program development and the operation efficiency of the product can be considered.

Another advantage of the above embodiments is that they provide a simple way to read files in a cache.

Drawings

FIG. 1 is a simplified functional block diagram of a data processing system according to an embodiment of the present application.

Fig. 2 is a simplified functional block diagram of a cache according to an embodiment of the present application.

FIG. 3 is a diagram illustrating operations of the data access circuit searching for a target cache line.

FIG. 4 is a simplified functional block diagram of a data access circuit according to an embodiment of the present application.

FIG. 5 is a functional block diagram of a first logic circuit according to an embodiment of the present application.

FIG. 6 is a functional block diagram of a second logic circuit according to an embodiment of the present application.

FIG. 7 is a simplified functional block diagram of a data access circuit according to another embodiment of the present application.

FIG. 8 is a functional block diagram of a first logic circuit according to another embodiment of the present application.

FIG. 9 is a functional block diagram of a second logic circuit according to another embodiment of the present application.

Detailed Description

Embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, the same reference numbers indicate the same or similar components or process flows.

FIG. 1 is a simplified functional block diagram of a data processing system 100 according to an embodiment of the present application. The data processing system 100 includes an arithmetic circuit 110, a cache memory 120, and a main memory 130, the arithmetic circuit 110 and the cache memory 120 are coupled to each other through a data transfer interface, and the cache memory 120 and the main memory 130 are also coupled to each other through a data transfer interface. The operation circuit 110 issues a plurality of read access commands to retrieve the required data during the operation process. If a cache hit occurs, which means that the data to be fetched by the computing circuit 110 is stored in the cache 120, the computing circuit 110 directly fetches the data from the cache 120 to avoid a time penalty (time penalty) for accessing the main memory 130.

When the operation circuit 110 issues a write access request, if the address of the write access request is located in a cacheable (cacheable) interval and a cache hit occurs, the operation circuit 110 directly updates the data in the cache 120. If the address requested by the write-access is located in the write-through interval, the corresponding data in the main memory 130 is also updated. If the address requested by the write-access is in the write-back (write-back) interval, the main memory 130 is not updated for the time being, and the updated cache line in the cache 120 is given a dirty tag. In subsequent operations, the data stored in the dirty marked cache line is used to update the main memory 130 when the dirty marked cache line is selected to replace the data stored therein.

In this embodiment, the cache 120 may be a unified cache (unified cache) for storing data and instructions, or may be implemented by a data cache (data cache) and an instruction cache (instruction cache) together. The arithmetic circuitry 110 may be implemented with one or more processors, Digital Signal Processors (DSPs), Field Programmable Gate Arrays (FPGAs), and the like.

Fig. 2 is a simplified functional block diagram of the cache 120 according to an embodiment of the present application. The cache 120 includes a data access circuit 210 and a memory circuit 220 coupled to each other. The data access circuit 210 is configured to receive an address of a read access request from the operation circuit 110, retrieve data from the memory circuit 220 according to the received address, and transmit the data back to the operation circuit 110. When the operation circuit 110 issues a write access request, the data access circuit 210 is configured to receive write data from the operation circuit 110 and store the write data in the memory circuit 220 according to an address of the write access request.

There are many implementations of memory circuit 220, and for ease of illustration, this application assumes that memory circuit 220 is multi-way set association. In detail, the memory circuit 220 includes a tag memory (tag RAM)222 and a data memory (data RAM) 224. The data access circuit 210 compares the tag of the address requested by the access with the tag stored in the tag memory 222, and searches the data memory 224 for the corresponding cache line to access the data according to the comparison result.

FIG. 3 is a diagram illustrating the operation of the data access circuit 210 in searching for a target cache line. As shown in FIG. 3, the address 300 of the access request includes fields for a tag 312, an index (index)314, and a byte offset (byte offset) 316. The tag memory 222 includes four cache ways (cache ways), and each way of the tag memory 222 stores a plurality of tags. The data memory 224 also includes four cache ways, and each way of the data memory 224 includes a plurality of cache lines for storing data. In addition, since the memory circuit 220 is configured as a multi-way set associative, the memory circuit 220 includes a plurality of cache sets (cache sets) 320. Each cache set 320 includes one tag per cache way of tag memory 222 and one cache line per cache way of data memory 224, i.e., cache set 320 includes four tags and four cache lines. The tags in the cache set 320 are respectively associated with the cache lines in the cache set 320, and when any tag in the cache set 320 is determined to be the same as the tag 312 of the access request, a cache hit occurs, and the associated cache line is accessed.

In particular, the index 314 of access requests is used to identify a particular cache set 320. Then, the tags in the cache set 320 are respectively transmitted to the comparators 330 for comparison with the tags 312 of the access request. The path selector 340 instructs the multiplexer 350 to select one of the cache rows in the cache set 320 and output the stored data 360 according to the outputs of the comparators 330. At this time, if any tag in the cache set 320 is the same as the tag 312 of the access request, the way selector 340 informs the arithmetic circuit 110 of a cache hit via the line 370. In some embodiments, the comparator 330, the path selector 340 and the multiplexer 350 may be disposed in the data access circuit 210.

Since a cache line typically has a storage capacity of multiple bytes (e.g., byte 0, byte 1, byte 2, and byte 3), the byte offset 316 of the access request may be used to specify a byte (e.g., byte 3) in the data 360. In the case where the address 300 corresponds to a read access request, the specified byte is output to the arithmetic circuitry 110 via line 380. On the other hand, in the case where the address 300 corresponds to a write access request, the cache set 320 may receive write data from the operational circuit 110 via the line 390 and store the write data in its cache line.

FIG. 4 is a simplified functional block diagram of a data access circuit 210 according to an embodiment of the present application. The data access circuit 210 includes a first logic circuit 410, a second logic circuit 420, a third logic circuit 430, a plurality of comparators 440, and a multiplexer 450, but the present application is not limited thereto. In some embodiments, the comparator 440 and the multiplexer 450 may be implemented by a circuit different from the data access circuit 210. The first logic circuit 410 and the second logic circuit 420 are used for examining tags stored in the plurality of cache ways 10[0] to 10[3] of the tag memory 222 according to the address 300 of the access request to search for associated cache lines in the plurality of cache ways 20[0] to 20[3] of the data memory 224.

When the enable signal EN has a first logic state (e.g., logic 0), the first logic circuit 410 and the second logic circuit 420 operate the tag memory 222 and the data memory 224 as cache memories in response to an access request. I.e., the tag memory 222 and the data memory 224 are accessible by access requests having arbitrary addresses. On the other hand, when the enable signal EN has a second logic state (e.g., logic 1), the first logic circuit 410 and the second logic circuit 420 operate the tag memory 222 and the data memory 224 as tightly coupled memories in response to the access request. I.e., the tag memory 222 and the data memory 224 are only accessible by access requests having a particular address. The operation of the data access circuit 210 when the enable signal EN has a first logic state will be described first, and it is assumed that the first logic state of the enable signal EN represents that the enable signal EN is logic 0.

Fig. 5 is a functional block diagram of a first logic circuit 410 according to an embodiment of the present application. Referring to fig. 4 and 5, first, the data access circuit 210 identifies a target cache set in the tag memory 222 and the data memory 224 according to the index 314 of the address 300. Multiplexer 440 is associated with each of cache ways 10[0] 10[3] of tag memory 222, and multiplexer 440 compares tag 312 at address 300 with tags in cache ways 10[0] 10[3] that belong to the target cache set. The comparison signals Ma [0] Ma [3] output by the multiplexer 440 to the first logic circuit 410 correspond to the comparison results of the cache ways 10[0] 10[3], respectively. For example, if the tag in cache way 10[0] belonging to the target cache set is different from tag 312 of address 300, compare signal Ma [0] is set to logic 0, and if the tag in cache way 10[0] belonging to the target cache set is the same as tag 312 of address 300, compare signal Ma [0] is set to logic 1, and so on.

The first logic circuit 410 includes a plurality of first and gates 31, a plurality of second and gates 32, and a plurality of first or gates 41. The first AND gates 31 are used for receiving the inverted signals of the enable signal EN and receiving the comparison signals Ma [0] Ma [3], respectively. Under the condition that the enable signal EN is logic 0, the outputs of the plurality of first AND gates 31 are respectively identical to the comparison signals Ma [0] to Ma [3 ]. In addition, since the second and gates 32 also receive the enable signal EN, the second and gates 32 output a logic 0. Each first OR gate 41 is used for receiving an output of a corresponding first AND gate 31 and an output of a corresponding second AND gate 32, so that the outputs of the first OR gates 41 are respectively identical to the comparison signals Ma [0] Ma [3 ]. The outputs of first OR-gates 41 are output as MUX signals to multiplexer 450 to instruct multiplexer 450 to select one of the cache lines belonging to the target cache set from cache ways 20[0] -20 [3] and output the data in that cache line. As mentioned above, the byte offset 316 of the address 300 is used to select a specific byte of data to provide to the operation circuit 110, and is not described herein.

Fig. 6 is a functional block diagram of a second logic circuit 420 according to an embodiment of the present application. Referring to fig. 4 and fig. 6, the second logic circuit 420 includes a third and gate 33, a fourth and gate 34, a second or gate 42 and a third or gate 43, wherein the second or gate 42 is configured to receive the comparison signals Ma [0] to Ma [3] and output the or operation result of the comparison signals Ma [0] to Ma [3] to the fourth and gate 34. The third AND gate 33 and the fourth AND gate 34 are both used for receiving the enable signal EN, so that when the enable signal EN is logic 0, the third AND gate 33 outputs logic 0, and the output of the fourth AND gate 34 is the same as the OR result of the comparison signals Ma [0] Ma [3 ]. The third OR gate 43 is used to receive the outputs of the third AND gate 33 and the fourth AND gate 34, so that the third OR gate 43 will use the OR operation result of the comparison signals Ma [0] to Ma [3] as the HIT signal HIT, which is used to notify the operation circuit 110 of the occurrence of cache HIT or cache miss in the cache 120. For example, HIT signal HIT is set to logic 0 if a cache miss occurs, and to logic 1 if a cache HIT occurs.

In summary, when the enable signal EN is logic 0, the data access circuit 210 determines that a cache hit occurs if the tag 312 of the address 300 is identical to a corresponding tag in the cache ways 10[0] to 10[3 ]. Otherwise, the data access circuit 210 determines that a cache miss occurs. The operation of the data access circuit 210 when the enable signal EN has the second logic state is described below, and it is assumed that the second logic state of the enable signal EN represents that the enable signal EN is logic 1.

Referring to fig. 4 and 5, when the enable signal EN is logic 1, the first and gate 31 outputs logic 0 by receiving the inverted signal of the enable signal EN, that is, the first and gate 31 masks the comparison signals Ma [0] to Ma [3 ]. The second AND gate 32 is used for receiving a plurality of selection signals W [0] W [3], respectively. The selection signals W [0] to W [3] are generated by decoding a plurality of corresponding bits in the tag 312. In some embodiments, the number of these corresponding bits may be represented by "equation 1" below, where M is the number of corresponding bits and N is the number of cache way or select signals.

M＝log₂N formula 1

In the embodiment of FIG. 5, data access circuit 210 decodes two bits in tag 312 to obtain four select signals W [0] W [3 ]. For example, if the address 300 includes 32 bits (bit [31:0]), and the 14 th bit to 32 th bit (bit [31:13]) are the tags 312, the data access circuit 210 can decode the 14 th bit to 15 th bit (bit [14:13 ]). One of the selection signals W [0] W [3] has a different logic value from the others. For example, if the decoded bit is 00, the selection signal W [0] is logic 1 and the selection signals W [1] to W [3] are logic 0. For another example, if the decoded bit is 01, the selection signal W [1] is logic 1 and the selection signals W [0], W [2] to W [3] are logic 0. For another example, if the decoded bit is 10, the selection signal W [2] is logic 1 and the selection signals W [0] -W [1], W [3] are logic 0, and so on.

The address determination signal RAN generated by the third logic circuit 430 is transmitted to the second and gate 32. The third logic 430 includes registers 431 and 432 storing an address upper bound value Add1 and an address lower bound value Add2, respectively, and the third logic 430 is used for determining whether the address 300 is located between the address upper bound value Add1 and the address lower bound value Add 2. If not, the third logic 430 sets the address determination signal RAN to logic 0. If so, the third logic 430 sets the address determination signal RAN to logic 1. However, the present application is not limited thereto, the third logic circuit 430 may generate different first logic states and second logic states to indicate that the address 300 is located and not located between the address upper limit value Add1 and the address lower limit value Add2, respectively, and the respective values of the first logic states and the second logic states may be determined according to the actual circuit design. Therefore, if the determination signal RAN is logic 0, the second AND gate 32 will mask the selection signals W [0] W [3 ]; if the determination signal RAN is logic 1, the outputs of the second AND gates 32 are respectively identical to the selection signals W [0] W [3], and the outputs of the first OR gates 41 are also respectively identical to the selection signals W [0] W [3 ].

In summary, when the enable signal EN is logic 0, the first logic circuit 410 takes the comparison signals Ma [0] Ma [3] as the multiplexing signal MUX; when the enable signal EN and the determination signal RAN are logic 1, the first logic circuit 410 uses the selection signals W [0] W [3] as the multiplexing signal MUX to designate the data of a corresponding one of the cache ways 20[0] 20[3 ].

Referring to FIG. 4 and FIG. 6, when the enable signal EN is logic 1, the determination signal RAN is transmitted to the second OR gate 43 through the third AND gate 33, and the fourth AND gate 34 masks the OR operation results of the comparison signals M [0] M [3 ]. Therefore, when the determination signal RAN is logic 1, the data access circuit 210 determines that a cache HIT occurs (the HIT signal HIT is logic 1); when the determination signal RAN is logic 0, the data access circuit 210 determines that a cache miss occurs (the hit signal is logic 0).

In summary, in the development stage of the program, since the storage addresses of the instructions and the data are not fixed, the user can operate the memory circuit 220 as a cache memory through the data access circuit 210 to obtain the acceleration function suitable for all the address intervals. When the user determines the storage address of the program code or data to be accelerated, the user can operate the memory circuit 220 as a tightly coupled memory through the data access circuit 210 to focus on accelerating the default address range (i.e., the range defined by the address upper limit value Add1 and the address lower limit value Add 2).

When the conventional cache control circuit responds to the write-in access request with the address in the write-back interval, if a cache miss occurs, the corresponding data in the main memory is loaded into the cache, and then the cache control circuit updates the cache according to the rule of cache hit. In some embodiments, when the data access circuit 210 responds to a write access request with an address in the write-back interval, even if a cache miss occurs, the data access circuit 210 will not load data in the main memory 130 into the memory circuit 220 and will not store write data corresponding to the write access request in the memory circuit 220. Otherwise, the data access circuit 210 writes the write data directly back to the main memory 130. That is, the data in the memory circuit 220 is not replaced randomly, thereby further improving the acceleration efficiency.

In addition, since the user cannot specify a specific storage space for reading the conventional cache memory, it is difficult for the user to obtain a temporary file during the program running process for debugging. With the data access circuit 210 in the above embodiments, a user can switch the memory circuit 220 from a cache memory to a tightly coupled memory in the middle of the execution of a program. Therefore, the user can easily read the files in the cache through the designated address in the program execution process.

FIG. 7 is a simplified diagram of a data access circuit 210 according to another embodiment of the present application. In the embodiment, the data access circuit 210 includes a first logic circuit 710, a second logic circuit 720 and a third logic circuit 730, and the enable signal EN includes a plurality of sub-enable signals EN [0] EN [3 ]. Fig. 8 is a functional block diagram of a first logic circuit 710 according to an embodiment of the present application. As shown in FIG. 8, the inverted signals of the sub-enable signals EN [0] EN [3] are respectively transmitted to the first AND gates 31, and the sub-enable signals EN [0] EN [3] are respectively transmitted to the second AND gates 32.

Referring again to fig. 7, the third logic circuit 730 includes a plurality of buffers 431 and a plurality of buffers 432. The plurality of buffers 431 respectively store a plurality of address upper limit values Add1, Add3, Add5 and Add7, the plurality of buffers 432 respectively store a plurality of address lower limit values Add2, Add4, Add6 and Add8, and the address upper limit values Add1, Add3, Add5 and Add7 respectively define four address intervals with the address lower limit values Add2, Add4, Add6 and Add 8. The address determination signal RAN provided by the third logic circuit 430 includes a plurality of sub-address determination signals RAN [0] -RAN [3], and the sub-address determination signals RAN [0] -RAN [3] are respectively used for indicating whether the address 300 of the access request is located in the four address intervals. In some embodiments, the four address ranges do not overlap.

For example, if the address 300 is located in the address interval defined by the upper address limit value Add1 and the lower address limit value Add2, the sub-address determination signal RAN [0] is set to logic 1; otherwise, the sub-address determination signal RAN [0] is set to logic 0. For another example, if the address 300 is located in the address range defined by the upper address limit value Add3 and the lower address limit value Add4, the sub-address determination signal RAN [1] is set to logic 1; otherwise, the sub-address determination signal RAN [0] is set to logic 0, and so on.

Fig. 9 is a functional block diagram of a second logic circuit 720 according to an embodiment of the present application. The second logic circuit 720 is similar to the second logic circuit 420 of fig. 6, except that the second logic circuit 720 further includes a fourth or gate 44 and a fifth or gate 45. The fourth OR gate 44 is for receiving the sub-address determination signals RAN [0] to RAN [3], and the third AND gate 33 is for receiving an output of the fourth OR gate 44. The fifth OR gate 45 is for receiving the sub-enable signals EN [0] EN [3], the third AND gate 33 is for receiving the output of the fifth OR gate 45, and the fourth AND gate 34 is for receiving the inverted output of the fifth OR gate 45.

In the present embodiment, if the enable signal EN has a first logic state (e.g., the sub-enable signals EN [0] EN [3] are all logic 0), the data reading circuit 210 will operate the memory circuit 220 as a cache memory. If the enable signal EN has a second logic state (e.g., one of the sub-enable signals EN [0] EN [3] is logic 1), the data reading circuit 210 will operate the memory circuit 220 as a tightly coupled memory. In addition, when the address 300 of the access request is not located in the four address ranges, the determination signal RAN has a first logic state (e.g., the sub-determination signals RAN [0] to RAN [3] are all logic 0); when the address 300 of the access request is located in one of the four address ranges, the determination signal RAN has a second logic state (e.g., one of the sub-determination signals RAN [0] RAN [3] is logic 1), and the data access circuit 210 generates the MUX signal according to the selection signals W [0] W [3 ].

As can be seen from the above, the data access circuit 210 of FIG. 7 can operate the memory circuit 220 as a tightly coupled memory having a plurality of address intervals that do not overlap with each other, so as to increase the flexibility of application. The rest of the connection manners, components, embodiments and advantages of the data access circuit 210 of fig. 4 are all applicable to the data access circuit 210 of fig. 7, and for brevity, the description is not repeated herein.

Certain terms are used throughout the description and claims to refer to particular components. However, it will be understood by those skilled in the art that the same elements may be referred to by different names. The description and claims do not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Further, "coupled" herein includes any direct and indirect connection. Therefore, if the first component is coupled to the second component, it means that the first component can be directly connected to the second component through electrical connection or signal connection such as wireless transmission, optical transmission, etc., or indirectly connected to the second component through other components or connection means.

In addition, any reference to singular is intended to include the plural unless the specification specifically states otherwise.

The above is merely a preferred embodiment of the present application and all equivalent changes and modifications made in the claims of the present application shall fall within the protection scope of the present application.

Description of the reference numerals

100 data processing system

110 arithmetic circuit

120: cache

130 main memory

210 data access circuit

220 memory circuit

222 tag memory

224 data memory

300 address

312 label

314 index

316 byte offset

320 buffer group

330,440 comparator

340 route selector

350,450 multiplexer

360 data

370,380,390 line

410,710 first logic circuit

420,720 second logic circuit

430,730 third logic circuit

431,432 buffer

Add1, Add3, Add5, Add7 Address ceiling value

Add2, Add4, Add6, Add8 lower Address Limit values

Ma 0-Ma 3 comparing signals

EN enable signal

EN 0-EN 3 sub-enable signals

RAN address judgment signal

Sub-address judging signal of RAN [0] to RAN [3]

W0-W3 is a selection signal

10[0] to 10[3],20[0] to 20[3] cache way

HIT signal

31 first AND gate

32 second AND gate

33 third AND gate

34 fourth AND gate

41 first OR gate

42 second or door

43 third OR door

Fourth OR gate 44

45 the fifth or door

Claims (10)

1. A data processing apparatus comprising:

a memory circuit comprising a plurality of cache ways for storing data; and

a data access circuit;

in response to a first logic state of an enable signal, the data access circuit determines that a cache hit occurs if a tag of an address of an access request is the same as a corresponding tag of the cache ways;

in response to a second logic state of the enable signal, the data access circuit determines that the cache hit occurs if the address is within one or more default address ranges specified by the data access circuit, and determines that a cache miss occurs if the address is outside of the one or more default address ranges.

2. The data processing apparatus of claim 1, wherein each of the plurality of cache ways comprises a cache line, and the data processing apparatus further comprises:

a plurality of comparators respectively associated with the plurality of cache ways, each comparator for comparing the tag of the address with a tag of a corresponding one of the plurality of cache ways;

in response to the first logic state of the enable signal, the data access circuit takes the outputs of the comparators as a multitasking signal, and the multitasking signal is used for appointing the cache line of one of the cache ways so as to enable the data of the cache line to be output to an arithmetic circuit;

in response to the second logic state of the enable signal, the data access circuit generates the multitasking signal according to a plurality of corresponding bits in the address if the address is located in the one or more default address intervals.

3. The data processing apparatus of claim 2, wherein the data access circuit comprises:

a first logic circuit, coupled to the plurality of comparators, for responding to the first logic state of the enable signal by using outputs of the plurality of comparators as the multitasking signal, and for responding to the second logic state of the enable signal by generating the multitasking signal according to the corresponding bits of the address when the address is in the one or more default address intervals; and

a second logic circuit, configured to determine that the cache hit or the cache miss occurs according to an or operation result output by the comparators in response to the first logic state of the enable signal, and determine that the cache hit or the cache miss occurs according to the address in response to the second logic state of the enable signal.

4. The data processing apparatus of claim 3, wherein the first logic circuitry comprises:

a plurality of first and gates for receiving the inverted signal of the enable signal and for receiving the outputs of the plurality of comparators, respectively;

a plurality of second and gates for receiving the enable signal and an address determination signal, and for receiving a plurality of selection signals corresponding to the bits of the address, respectively, wherein a first logic state and a second logic state of the address determination signal respectively represent that the address is outside the one or more default address intervals and the address is within the one or more default address intervals; and

and the data access circuit takes the outputs of the first OR gates as the multitask signal.

5. The data processing apparatus of claim 4, wherein the second logic circuitry comprises:

a second OR gate for receiving the outputs of said plurality of comparators to generate the OR result of the outputs of said plurality of comparators;

a third and gate for receiving the enable signal and the address determination signal;

a fourth and gate for receiving an inverted signal of the enable signal and an output of the second or gate; and

and the third OR gate is used for receiving the outputs of the third AND gate and the fourth AND gate and outputting a hit signal, when the hit signal has a first logic value, the data access circuit judges that the cache miss occurs, and when the hit signal has a second logic value, the data access circuit judges that the cache hit occurs.

6. The data processing apparatus according to claim 4, wherein the address determination signal comprises a plurality of sub-address determination signals, the plurality of second AND gates are respectively configured to receive the plurality of sub-address determination signals, the first logic state of the address determination signal is that all of the plurality of sub-address determination signals have a first logic value, the second logic state of the address determination signal is that one of the plurality of sub-address determination signals has a second logic value,

the enabling signal comprises a plurality of sub-enabling signals, the first AND gates are respectively used for receiving a plurality of inverted signals of the sub-enabling signals, the second AND gates are respectively used for receiving the sub-enabling signals, the first logic state of the enabling signal is that the sub-enabling signals are all the first logic value, and the second logic state of the enabling signal is that one of the sub-enabling signals is the second logic value.

7. The data processing apparatus of claim 6, wherein the second logic circuitry comprises:

a fourth or gate for receiving the address judgment signal;

a fifth or gate for receiving the enable signal;

a second OR gate for receiving the outputs of said plurality of comparators to generate the OR result of the outputs of said plurality of comparators;

a third and gate for receiving the output of said fourth or gate and the output of said fifth or gate;

a fourth and gate for receiving the output of said second or gate and the output of said fifth or gate; and

and the third OR gate is used for receiving the outputs of the third AND gate and the fourth AND gate and outputting a hit signal, when the hit signal has the first logic value, the data access circuit judges that the cache miss occurs, and when the hit signal has the second logic value, the data access circuit judges that the cache hit occurs.

8. A data access circuit for coupling to a memory circuit for accessing the memory circuit, the memory circuit including a plurality of cache ways for storing data, the data access circuit being configured to: in response to a first logic state of an enable signal, if a tag of an address of an access request is the same as a corresponding tag of the plurality of cache ways, determining that a cache hit occurs;

in response to a second logic state of the enable signal, if the address is located in one or more default address intervals specified by the data access circuit, determining that the cache hit occurs; and

in response to the second logic state of the enable signal, determining that a cache miss occurs if the address is outside of the one or more default address intervals.

9. The data access circuit of claim 8, wherein each of the plurality of cache ways comprises a cache line, the data access circuit configured to be coupled to a plurality of comparators respectively associated with the plurality of cache ways, each comparator configured to compare the tag of the address with a tag of a corresponding cache way of the plurality of cache ways, the data access circuit further configured to:

in response to the first logic state of the enable signal, using the outputs of the comparators as a multitasking signal, the multitasking signal being used for designating the cache line of one of the cache ways so as to output the data of the cache line to an arithmetic circuit; and

in response to the second logic state of the enable signal, the multitasking signal is generated according to a plurality of corresponding bits in the address if the address is located in the one or more default address intervals.

10. The data access circuit of claim 9, comprising:

a first logic circuit, coupled to the plurality of comparators, for responding to the first logic state of the enable signal by using outputs of the plurality of comparators as the multitasking signal, and for responding to the second logic state of the enable signal by generating the multitasking signal according to the corresponding bits of the address when the address is in the one or more default address intervals; and

a second logic circuit, configured to determine that the cache hit or the cache miss occurs according to an or operation result output by the comparators in response to the first logic state of the enable signal, and determine that the cache hit or the cache miss occurs according to the address in response to the second logic state of the enable signal.

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