CN114690018A - Method and device for testing integrated circuit chip and storage medium - Google Patents
Method and device for testing integrated circuit chip and storage medium Download PDFInfo
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- CN114690018A CN114690018A CN202011589999.XA CN202011589999A CN114690018A CN 114690018 A CN114690018 A CN 114690018A CN 202011589999 A CN202011589999 A CN 202011589999A CN 114690018 A CN114690018 A CN 114690018A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
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Abstract
The invention aims to provide a method, a device and a storage medium for testing an integrated circuit chip, thereby effectively reducing the test power consumption of the integrated circuit chip; to achieve the above object, the present invention provides a method and an apparatus for testing an integrated circuit chip, in which the test apparatus supplies data of each register as a test signal to each circuit block of the integrated circuit chip by an initial shift operation and then acquires output data of each logic circuit in each register by a capture operation, and a storage medium. Then, the shift operation and the capture operation are repeated, and the obtained output data of each circuit block is compared with an expected value thereof, thereby performing a test of each logic circuit.
Description
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to a method and an apparatus for testing an integrated circuit chip, a computer device, and a storage medium.
Background
With the rapid development of integrated circuit chip technology, the design requirements of low power consumption, high performance and high reliability are higher and higher. Scan test (Scan test) techniques for circuits are common design for testability (DFT) techniques used to test integrated circuit chips. The scan test technology converts a common register in a sequential circuit into a scannable register, then serializes the scannable register into a scan chain, and completes the test of an integrated circuit chip in a scanning mode. The scan test technique first shifts a pseudo-random or predetermined test stimulus source (stimuli) into all scan chains in a Shift (Shift) cycle. Subsequently, in a Capture (Capture) cycle, the test response is latched in some or all of the scan chains, and the values captured into the scan chains may be shifted out in the next cycle. The shift cycle and the capture cycle are repeated continuously to perform a test, and the output response is compared with an expected correct result to determine whether the integrated circuit chip has a fault.
With the increase of Scan registers (Scan Cells), the power consumption of the integrated circuit chip is increased during the Scan test. The increase of power consumption can lead to the temperature rise of the integrated circuit chip, so that the electrical parameters in the integrated circuit chip are deviated, the test failure is finally caused, and the yield of the chip is influenced. The power consumption of the scan test of the integrated circuit chip is mainly divided into shift power consumption and capture power consumption. The shift power consumption refers to power consumption of a register in a chip in a shift period, and the capture power consumption refers to power consumption of the register in the chip in a capture period. The registers in the integrated circuit chip in the scan test mode are in a frequently flipped state, and the power consumption of the registers is usually several times greater than that in the normal functional mode. In the prior art, a scheme for reducing test power consumption by reducing clock frequency exists, but with the increase of the scale of an integrated circuit chip, the requirement for reducing test power consumption cannot be met by reducing the clock frequency. Meanwhile, in the prior art, a method for rearranging scan chains through digital modeling is adopted to reduce test power consumption, but the method is still difficult to apply to large-scale production test. Therefore, a test method and apparatus that can reduce test power consumption for mass production are required.
Disclosure of Invention
In view of the above, it is necessary to provide a method and an apparatus for testing a low power consumption integrated circuit chip, and a storage medium, which can be used for mass production.
According to an aspect of the present disclosure, there is provided a method for testing an integrated circuit chip, the method comprising:
generating a clock for the scan test of the integrated circuit chip at a shift stage of the scan test of the integrated circuit chip, wherein the clocks of different registers of the integrated circuit chip have delay time;
and capturing the output of the register of the integrated circuit chip in a capturing stage of the scanning test of the integrated circuit chip.
According to another aspect of the present disclosure, there is provided an apparatus for testing an integrated circuit chip, the apparatus comprising:
the shift module is used for generating a clock of the integrated circuit chip scanning test in a shift stage of the integrated circuit chip scanning test, wherein the clocks of different registers of the integrated circuit chip have delay time;
and the capturing module is used for capturing the output of the register of the integrated circuit chip in the capturing stage of the scanning test of the integrated circuit chip. According to another aspect of the present disclosure, there is provided a storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the above-described method.
According to another aspect of the present disclosure, there is provided another apparatus for testing an integrated circuit chip, comprising:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to carry out any of the above methods when executing the instructions.
According to another aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the method of any one of the above.
By the test method and the test device, the test power consumption of the integrated circuit chip can be effectively reduced.
Drawings
FIG. 1 is a schematic diagram of an application scenario in one embodiment;
FIG. 2 is a flow diagram of a testing method in one embodiment;
FIG. 3 is a schematic diagram of a method flow diagram of the shift step of the test method in one embodiment;
FIG. 4 is a schematic diagram of a method flow diagram of the capture step of the test method in one embodiment;
FIG. 5 is a schematic diagram illustrating a further method flow for the capture step of the test method in one embodiment;
FIG. 6 is a block diagram showing the structure of a test apparatus according to an embodiment;
FIG. 7 is a block diagram showing the structure of a shift module of the test apparatus in one embodiment;
FIG. 8 is a block diagram showing the structure of a capture module of the test apparatus in one embodiment;
FIG. 9 is a schematic block diagram illustrating a further configuration of a capture module of the test apparatus in one embodiment;
FIG. 10 is a block diagram showing the structure of a test apparatus in another embodiment;
FIG. 11 is a block diagram illustrating the structure of an integrated clock gating cell in one embodiment.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, not all embodiments of the present disclosure. All other embodiments, which can be derived by one skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the scope of protection of the present disclosure.
It should be understood that the terms "first," "second," and the like in the claims, the description, and the drawings of the present disclosure are used for distinguishing between different objects and not for describing a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.
As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
Fig. 1 shows a schematic diagram of an application scenario according to an embodiment of the present disclosure, as shown in fig. 1, including an integrated circuit chip 1 and a testing apparatus 2. The integrated circuit chip 1 may be any circuit type and size of integrated circuit chip, such as a chip, which may include circuit modules, such as gates, flip-flops, counters, codecs, and memories. The test apparatus 2 may be implemented by a computer device, a programmable circuit, an Application Specific Integrated Circuit (ASIC), an automatic test equipment ate (automatic test equipment), and the like. The integrated circuit chip 1 and the test device 2 are connected via a test interface 3.
After the functional design of the integrated circuit chip 1 is completed, the whole netlist is composed of a stack of registers and combinational logic. In the process of testing the scan chain, firstly, the scan chain needs to be inserted, registers in the netlist are replaced by scan registers, and then the scan registers are connected to form the scan chain. In the test, the test apparatus 2 supplies data of each register as a test signal to each circuit block of the integrated circuit chip 1 by an initial shift operation, and then acquires output data of each logic circuit in each register by a capture operation. Then, the shift operation and the capture operation are repeated, and the obtained output data of each circuit block is compared with an expected value thereof, thereby performing a test of each logic circuit.
However, as the number of scan registers increases, the shift power consumption and the capture power consumption of the integrated circuit chip also increase during the scan test. Based on this, the present disclosure provides a test method of an integrated circuit chip, which can reduce test power consumption of the entire integrated circuit chip by reducing shift power consumption of a shift stage and/or capture power consumption of a capture stage.
Optionally, in a shift stage of the test, the present disclosure may separately test a part of modules in the integrated circuit chip by controlling a clock of at least one module in the integrated circuit chip, for example, the shift stage may provide a clock to a single module, so that a register in the single module is turned over, and registers in other modules are not turned over, thereby reducing shift power consumption in the test process.
Optionally, in a shift stage of the test, the present disclosure may further control a clock of at least one module in the integrated circuit chip, so that the registers of the respective modules are not flipped at the same time, for example, the registers of the respective modules may be flipped alternately or at intervals by controlling the clock, thereby reducing shift power consumption in the test process. One embodiment of the present disclosure at the shift stage is described below in conjunction with fig. 2.
Fig. 2 shows a flow chart of a testing method according to an embodiment of the present disclosure, and as shown in fig. 2, the testing method of an integrated circuit chip provided by the present disclosure may include the following steps:
step S11, generating the clock of the IC chip scan test at the shift stage of the IC chip scan test, wherein the clock of different registers of the IC chip has delay time;
step S12, in the capturing stage of the scan test of the integrated circuit chip, capturing the output of the register of the integrated circuit chip.
Because the clocks of different registers of the integrated circuit chip have delay time, the turning time of each register is different during the shifting action, therefore, each register can not be turned over at the same time, and the shifting power consumption of the integrated circuit chip is reduced.
Fig. 3 shows a flowchart of a method for implementing step S11 according to an embodiment of the present disclosure, and as shown in fig. 3, for step S11, in one possible implementation, step S11 may include:
step S111, generating a shift control signal for the scan test of the integrated circuit chip, and controlling a register of a partial module in the integrated circuit chip to perform a shift action;
in step S112, a clock for scan test of the integrated circuit chip is generated, wherein the clocks of different registers of the integrated circuit chip have delay times.
Because the integrated circuit chip comprises a plurality of modules, the scanning test control signal of the integrated circuit chip can only shift the register in the module which needs to be tested at present, and the registers in other modules do not shift, thereby reducing the test power consumption.
Optionally, in the capture phase of the test, the present disclosure may control a part of registers of a certain module in the integrated circuit chip to operate by a clock or the registers of a certain module to be turned over at different times, thereby reducing the capture power consumption in the capture phase. An embodiment of the present disclosure at the capture stage is described below in conjunction with fig. 4.
Fig. 4 shows a flowchart of a method for implementing step S12 according to an embodiment of the present disclosure, and as shown in fig. 4, for step S12, in one possible implementation, step S12 may include:
step S121, selecting an integrated clock gating unit for controlling in the integrated circuit chip;
step S122, generating an enable control signal of the integrated clock gating unit.
In an integrated circuit chip, clock gating units, especially Integrated Clock Gating (ICG) units, are used in large numbers to control the switching of a clock and thus to reduce power consumption. As shown in fig. 11, for the integrated clock gating cell ICG, the CK terminal is a clock input terminal, the ECK terminal is an enable clock output terminal, the E terminal is a gating enable terminal, and the TE terminal is a test enable terminal. The E terminal is typically controlled by functional logic and the TE terminal is typically controlled by test circuitry. When the E end or the TE end has more than one level value of 1, the integrated clock gating unit is turned on, and when the two level values are both 0, the integrated clock gating unit is turned off. In step S121, the integrated clock gating unit for controlling is selected, and only the integrated clock gating unit of the circuit module to be tested may be controlled, so as to further reduce the test power consumption; in the step S122, an enable control signal cg _ ctrl for controlling the E terminal and/or the TE terminal of the selected integrated clock gating cell is generated.
In the embodiment shown in fig. 4, the test method of the present disclosure can not only reduce the shift power consumption by controlling the clock delay of the shift stage, but also control the clock gating unit in the capture stage to reduce the capture power consumption. The embodiment of the disclosure greatly reduces the power consumption in the test process of the integrated circuit chip by simultaneously reducing the shift power consumption and the capture power consumption.
Of course, in an embodiment of the present disclosure, the purpose of reducing the test power consumption may also be achieved only by the capture power consumption of the capture phase. Optionally, the test method may include:
step A1, in the shift stage of the scan test of the integrated circuit chip, generating the clock of the scan test of the integrated circuit chip, and controlling the register of the module in the integrated circuit chip to shift;
step A2, in the capture phase of the scan test of the integrated circuit chip, the output of the partial register in the integrated circuit chip is captured. Optionally, capturing the output of a part of registers in the integrated circuit may be implemented with reference to the control manner of the integrated clock gating unit shown in fig. 4. Specifically, refer to fig. 4 and the above description, which are not repeated herein.
Fig. 5 shows a flowchart of a method for implementing step S122 according to an embodiment of the present disclosure, and as shown in fig. 5, for step S122, in a possible implementation manner, step S122 may include:
step S1221, selecting an internal test mode or an external test mode of the integrated circuit chip;
in step S1222, an integrated clock gating cell enable control signal is generated.
In an integrated circuit chip, various types of circuit modules are included, such as various types of pre-designed circuit functional modules with specific functions, also called IP cores. Performing a scan test on a circuit module of the integrated circuit chip as an internal test; the scan test performed between different circuit modules of the integrated circuit chip is an external test. Step S1221, selecting to perform an internal test or an external test on the integrated circuit chip; in step S1222, an enable control signal of the integrated clock gating cell in the internal test mode or the external test mode is generated.
In the foregoing embodiment of the present disclosure, a method for testing an integrated circuit chip for reducing test power consumption is provided, where a clock of a register is controlled in a delay manner in a shift stage of a scan test of the integrated circuit chip, so as to prevent each register from turning over at the same time, thereby reducing shift power consumption; the clock is controlled by the integrated clock gating unit in the capturing stage of the scan test of the integrated circuit chip, so that the capturing power consumption is reduced.
It should be noted that the above-mentioned method for reducing the test power consumption is optional. For example, a power consumption reduction control signal may be provided for controlling whether to use the above-described test method for reducing test power consumption in the scan test; or, a control signal for reducing the shift power consumption can be provided, which is used for controlling whether the test method of the integrated circuit chip for reducing the shift test power consumption is used in the scanning test; alternatively, a control signal for reducing the capture power consumption may be provided for controlling whether to use the above-described test method for reducing the capture test power consumption in the scan test.
The test method for the integrated circuit chip for reducing the test power consumption has various optional configuration functions, can be applied to test conditions under different scenes, is suitable for being applied to actual production design, solves the technical problems of reducing the scan test shift power consumption and capturing the power consumption of the integrated circuit chip in the prior art, achieves the effect of not killing the yield of the chip by mistake due to larger power consumption in mass production test, is simple and flexible in the provided circuit, is suitable for various scan test modes and chip function modes, is very friendly to the design of the integrated circuit chip, and achieves the technical effect of simplifying the design.
The present disclosure also provides a testing apparatus of an integrated circuit chip, and fig. 6 shows a block diagram of the testing apparatus of an integrated circuit chip according to an embodiment of the present disclosure, and as shown in fig. 6, the apparatus may include:
a shift module 61, configured to generate a clock for the scan test of the integrated circuit chip at a shift stage of the scan test of the integrated circuit chip, where clocks of different registers of the integrated circuit chip have delay times;
and a capture module 62 for capturing the output of the register of the integrated circuit chip during a capture phase of the scan test of the integrated circuit chip.
Because the clocks of different registers of the integrated circuit chip have delay time, the turning time of each register is different during the shifting action, therefore, each register can not be turned over at the same time, and the shifting power consumption of the integrated circuit chip is reduced.
Fig. 7 shows a block diagram of a testing apparatus for an integrated circuit chip according to an embodiment of the disclosure, as shown in fig. 6, in one possible implementation manner, the shift module 61 may include:
the first shifting unit 611 is configured to generate a control signal for a scan test of the integrated circuit chip, and control a register of a partial module in the integrated circuit chip to perform a shifting operation;
a second shift unit 612 for generating a clock for scan testing of the integrated circuit chip, wherein clocks of different registers of the integrated circuit chip have delay times.
Because the integrated circuit chip comprises a plurality of modules, the scanning test control signal of the integrated circuit chip can only shift the register in the module which needs to be tested at present, and the registers in other modules do not shift, thereby reducing the test power consumption.
Fig. 8 shows a block diagram of a testing apparatus for an integrated circuit chip according to an embodiment of the disclosure, and as shown in fig. 8, in one possible implementation, the capture module 62 may include:
a first capture unit 621, configured to select an integrated clock gating unit for controlling in the integrated circuit chip;
a second capture unit 622 for generating an integrated clock gating unit enable control signal.
In Integrated circuit chips, Clock Gating cells, especially Integrated Clock Gating (ICG) cells, are used in large numbers to control the switching of clocks to reduce power consumption. For an integrated clock gating unit, the CK terminal is a clock input terminal, the ECK terminal is an enable clock output terminal, the E terminal is a gating enable terminal, and the TE terminal is a test enable terminal. The E terminal is typically controlled by functional logic and the TE terminal is typically controlled by test circuitry. When more than one level value of the E end or the TE end is 1, the integrated clock gating unit is conducted, and when both the level values are 0, the integrated clock gating unit is closed. In step S121, the integrated clock gating unit for controlling is selected, and only the integrated clock gating unit of the circuit module to be tested may be controlled, so as to further reduce the test power consumption; in step S122, an enable control signal for the integrated clock gating unit is generated for controlling the E terminal and/or the TE terminal of the selected integrated clock gating unit.
Fig. 9 shows a block diagram of a testing apparatus for an integrated circuit chip according to an embodiment of the disclosure, and as shown in fig. 9, in one possible implementation, the second capturing unit 622 may include:
a mode selection unit 6221 for selecting an internal test mode or an external test mode of the integrated circuit chip;
an enable signal generation unit 6222 for generating an integrated clock gating unit enable control signal.
In an integrated circuit chip, various types of circuit modules are included, such as various types of pre-designed circuit functional modules with specific functions, also called IP cores. Performing a scan test on a circuit module of the integrated circuit chip as an internal test; the scan test performed between different circuit modules of the integrated circuit chip is an external test. Step S1221, selecting to perform an internal test or an external test on the integrated circuit chip; in step S1222, an enable control signal for the integrated clock gating cell under the internal test or the external test is generated.
In the above embodiment of the present disclosure, a testing apparatus for an integrated circuit chip for reducing test power consumption is provided, where in a shift stage of a scan test of the integrated circuit chip, a clock of a register is controlled in a delayed manner, so as to prevent each register from turning over at the same time, thereby reducing shift power consumption; the clock is controlled by the integrated clock gating unit in the capturing stage of the scan test of the integrated circuit chip, so that the capturing power consumption is reduced.
It should be noted that the above-mentioned means for reducing the test power consumption are optional. For example, a power consumption reduction control module may be provided for controlling whether to use the above-described test method for reducing test power consumption in the scan test; alternatively, a shift power consumption reduction control device may be provided for controlling whether to use the above-mentioned test method for reducing shift test power consumption of an integrated circuit chip in a scan test; alternatively, a capture power consumption reduction control means may be provided for controlling whether to use the above-described test method for an integrated circuit chip for reducing capture test power consumption at the time of scan test.
The test method for the integrated circuit chip for reducing the test power consumption has various optional configuration functions, can be applied to test conditions under different scenes, is suitable for being applied to actual production design, solves the technical problems of reducing the scan test shift power consumption and capturing the power consumption of the integrated circuit chip in the prior art, achieves the effect of not killing the chip yield by mistake due to larger power consumption in mass production test, is simple and flexible in circuit, is suitable for various scan test modes and chip function modes, is very friendly to the design of the integrated circuit chip, and achieves the technical effect of simplifying the design.
FIG. 10 is a block diagram illustrating an apparatus 2 for testing integrated circuit chips according to an exemplary embodiment of the present disclosure. For example, the apparatus 2 may be provided as a computer device, programmable circuit, Application Specific Integrated Circuit (ASIC), and automatic test equipment ate (automatic test equipment). Referring to fig. 10, the apparatus 2 comprises a processing component 21, which further comprises one or more processors, and memory resources, represented by memory 22, for storing instructions, e.g. applications, executable by the processing component 21. The application programs stored in memory 22 may include one or more modules that each correspond to a set of instructions. Further, the processing component 21 is configured to execute instructions to perform the above-described method.
In an exemplary embodiment, a non-transitory computer readable storage medium, such as the memory 22, is also provided, including computer program instructions executable by the processing component 21 of the apparatus 2 to perform the above-described method.
It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art will also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.
It is further noted that, although the various steps in the flowcharts of fig. 1-5 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1-5 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.
It should be understood that the above-described apparatus embodiments are merely exemplary, and that the apparatus of the present disclosure may be implemented in other ways. For example, the division of the units/modules in the above embodiments is only one logical function division, and there may be another division manner in actual implementation. For example, multiple units, modules, or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented.
In addition, unless otherwise specified, each functional unit/module in the embodiments of the present disclosure may be integrated into one unit/module, each unit/module may exist alone physically, or two or more units/modules may be integrated together. The integrated units/modules may be implemented in the form of hardware or software program modules.
If the integrated unit/module is implemented in hardware, the hardware may be a digital circuit, an analog circuit, or the like. Physical implementations of hardware structures include, but are not limited to, transistors, memristors, and the like. The processor may be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, ASIC, etc., unless otherwise specified. Unless otherwise specified, the Memory unit may be any suitable magnetic storage medium or magneto-optical storage medium, such as resistive Random Access Memory rram (resistive Random Access Memory), Dynamic Random Access Memory dram (Dynamic Random Access Memory), Static Random Access Memory SRAM (Static Random-Access Memory), enhanced Dynamic Random Access Memory edram (enhanced Dynamic Random Access Memory), High-Bandwidth Memory HBM (High-Bandwidth Memory), hybrid Memory cubic hmc (hybrid Memory cube), and so on.
The integrated units/modules may be stored in a computer readable memory if implemented in the form of software program modules and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. The technical features of the embodiments may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The foregoing may be better understood in light of the following clauses:
clause a1, a method of testing an integrated circuit chip, the method comprising:
generating a clock for the scan test of the integrated circuit chip at a shift stage of the scan test of the integrated circuit chip, wherein the clocks of different registers of the integrated circuit chip have delay time;
and capturing the output of the register of the integrated circuit chip in a capturing stage of the scanning test of the integrated circuit chip.
The method of clause a2, the method of claim 1, wherein the generating the clock for the scan test of the integrated circuit chip during the shift phase of the scan test of the integrated circuit chip, wherein the clocks for the different registers of the integrated circuit chip have delay times, comprises:
and generating a shift control signal for the scanning test of the integrated circuit chip, and controlling a register of a partial module in the integrated circuit chip to perform a shift action.
Clause a3, the method of claim 1, wherein capturing the output of the register of the integrated circuit chip during a capture phase of a scan test of the integrated circuit chip comprises:
selecting an integrated clock gating unit for controlling in the integrated circuit chip;
an enable control signal for the integrated clock gating cell is generated.
Clause a4, the method of claim 3, wherein the generating the enable control signal for the integrated clock gating cell comprises:
and selecting an internal test mode or an external test mode of the integrated circuit chip.
Clause a5, the method according to any one of claims 1 to 4, further comprising:
generating a power consumption reduction control signal for controlling whether to use the test method of the integrated circuit chip during the scan test; alternatively, the first and second electrodes may be,
generating a control signal for reducing shift power consumption, wherein the control signal is used for controlling whether a clock for the scan test of the integrated circuit chip is generated in a shift stage of the scan test of the integrated circuit chip, and clocks of different registers of the integrated circuit chip have delay time; alternatively, the first and second electrodes may be,
and generating a control signal for reducing capture power consumption, controlling whether an integrated clock gating unit for controlling in the integrated circuit chip is selected, and generating an enabling control signal of the integrated clock gating unit.
Clause a6, an apparatus for testing an integrated circuit chip, comprising:
the shift module is used for generating a clock of the integrated circuit chip scanning test in a shift stage of the integrated circuit chip scanning test, wherein the clocks of different registers of the integrated circuit chip have delay time;
and the capturing module is used for capturing the output of the register of the integrated circuit chip in the capturing stage of the scanning test of the integrated circuit chip.
Clause a7, the apparatus of claim 6, wherein the shifting module comprises:
and the first shifting unit is used for generating a shifting control signal of the scanning test of the integrated circuit chip and controlling a register of a partial module in the integrated circuit chip to shift.
Clause A8, the apparatus of claim 6, wherein the capturing module comprises:
a first capture unit for selecting an integrated clock gating unit in the integrated circuit chip for control;
a second capture unit to generate an enable control signal for the integrated clock gating unit.
Clause a9, the apparatus according to claim 8, wherein the second capturing unit comprises:
and the mode selection unit is used for selecting the internal test mode or the external test mode of the integrated circuit chip.
Clause a10, the apparatus according to any one of claims 6 to 9, further comprising any one of the following modules:
the power consumption reduction control module is used for controlling whether to use the test method of the integrated circuit chip during the scanning test;
the control module for reducing the shift power consumption is used for controlling whether a clock for the scan test of the integrated circuit chip is generated in the shift stage of the scan test of the integrated circuit chip, wherein the clocks of different registers of the integrated circuit chip have delay time;
and the capture power consumption reduction control module is used for controlling whether the integrated clock gating unit for controlling in the integrated circuit chip is selected or not and generating an enabling control signal of the integrated clock gating unit.
Clause a11, an apparatus for testing an integrated circuit chip, comprising:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to carry out the method of any one of claims 1 to 5 when executing the instructions.
Clause a12, a non-transitory computer readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the method of any one of claims 1 to 5.
The foregoing detailed description of the embodiments of the present disclosure has been presented for purposes of illustration and description and is intended to be exemplary only and is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Meanwhile, a person skilled in the art should, according to the idea of the present disclosure, change or modify the embodiments and applications of the present disclosure. In view of the above, this description should not be taken as limiting the present disclosure.
Claims (12)
1. A method of testing an integrated circuit chip, the method comprising:
generating a clock for the scan test of the integrated circuit chip at a shift stage of the scan test of the integrated circuit chip, wherein the clocks of different registers of the integrated circuit chip have delay time;
and capturing the output of the register of the integrated circuit chip in a capturing stage of the scanning test of the integrated circuit chip.
2. The method of claim 1, wherein generating a clock for a scan test of the integrated circuit chip during a shift phase of the scan test of the integrated circuit chip, wherein clocks for different registers of the integrated circuit chip have delay times, comprises:
and generating a shift control signal for the scanning test of the integrated circuit chip, and controlling a register of a partial module in the integrated circuit chip to perform a shift action.
3. The method of claim 1, wherein capturing the output of the register of the integrated circuit chip during a capture phase of the scan test of the integrated circuit chip comprises:
selecting an integrated clock gating unit for controlling in the integrated circuit chip;
an enable control signal for the integrated clock gating cell is generated.
4. The method of claim 3, wherein generating the enable control signal for the integrated clock gating cell comprises:
and selecting an internal test mode or an external test mode of the integrated circuit chip.
5. The method of any one of claims 1 to 4, further comprising:
generating a power consumption reduction control signal for controlling whether to use the test method of the integrated circuit chip during the scan test; alternatively, the first and second electrodes may be,
generating a control signal for reducing shift power consumption, wherein the control signal is used for controlling whether a clock for the scan test of the integrated circuit chip is generated in a shift stage of the scan test of the integrated circuit chip, and clocks of different registers of the integrated circuit chip have delay time; alternatively, the first and second electrodes may be,
and generating a control signal for reducing capture power consumption, controlling whether an integrated clock gating unit for controlling in the integrated circuit chip is selected, and generating an enabling control signal of the integrated clock gating unit.
6. An apparatus for testing an integrated circuit chip, the apparatus comprising:
the shift module is used for generating a clock of the integrated circuit chip scanning test in a shift stage of the integrated circuit chip scanning test, wherein the clocks of different registers of the integrated circuit chip have delay time;
and the capturing module is used for capturing the output of the register of the integrated circuit chip in the capturing stage of the scanning test of the integrated circuit chip.
7. The apparatus of claim 6, wherein the shifting module comprises:
and the first shifting unit is used for generating a shifting control signal of the scanning test of the integrated circuit chip and controlling a register of a partial module in the integrated circuit chip to shift.
8. The apparatus of claim 6, wherein the capture module comprises:
a first capture unit for selecting an integrated clock gating unit in the integrated circuit chip for control;
a second capture unit to generate an enable control signal for the integrated clock gating unit.
9. The apparatus of claim 8, wherein the second capturing unit comprises:
and the mode selection unit is used for selecting the internal test mode or the external test mode of the integrated circuit chip.
10. The device according to any one of claims 6 to 9, characterized by further comprising any one of the following modules:
the power consumption reduction control module is used for controlling whether to use the test method of the integrated circuit chip during the scanning test;
the control module for reducing the shift power consumption is used for controlling whether a clock for the scan test of the integrated circuit chip is generated in the shift stage of the scan test of the integrated circuit chip, wherein the clocks of different registers of the integrated circuit chip have delay time;
and the capture power consumption reduction control module is used for controlling whether the integrated clock gating unit for controlling in the integrated circuit chip is selected or not and generating an enabling control signal of the integrated clock gating unit.
11. An apparatus for testing an integrated circuit chip, comprising:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to carry out the method of any one of claims 1 to 5 when executing the instructions.
12. A non-transitory computer readable storage medium having computer program instructions stored thereon, wherein the computer program instructions, when executed by a processor, implement the method of any of claims 1 to 5.
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|---|---|---|---|
| CN202011589999.XA CN114690018A (en) | 2020-12-28 | 2020-12-28 | Method and device for testing integrated circuit chip and storage medium |
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| CN202011589999.XA CN114690018A (en) | 2020-12-28 | 2020-12-28 | Method and device for testing integrated circuit chip and storage medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117289114A (en) * | 2023-10-10 | 2023-12-26 | 苏州异格技术有限公司 | Logic function test circuit and test method |
| WO2024074017A1 (en) * | 2022-10-08 | 2024-04-11 | 深圳市中兴微电子技术有限公司 | Chip test method, register, electronic device, and storage medium |
-
2020
- 2020-12-28 CN CN202011589999.XA patent/CN114690018A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024074017A1 (en) * | 2022-10-08 | 2024-04-11 | 深圳市中兴微电子技术有限公司 | Chip test method, register, electronic device, and storage medium |
| CN117289114A (en) * | 2023-10-10 | 2023-12-26 | 苏州异格技术有限公司 | Logic function test circuit and test method |
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