CN114684037B - Controller, control system and vehicle - Google Patents
Controller, control system and vehicle Download PDFInfo
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- CN114684037B CN114684037B CN202210330821.6A CN202210330821A CN114684037B CN 114684037 B CN114684037 B CN 114684037B CN 202210330821 A CN202210330821 A CN 202210330821A CN 114684037 B CN114684037 B CN 114684037B
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Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B60—VEHICLES IN GENERAL
- B60R—VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
- B60R16/00—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for
- B60R16/02—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B60—VEHICLES IN GENERAL
- B60R—VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
- B60R16/00—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for
- B60R16/02—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements
- B60R16/03—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements for supply of electrical power to vehicle subsystems or for
Abstract
The embodiment of the invention discloses a controller, a control system and a vehicle, comprising: the controller chip comprises a first voltage transformation circuit, a second voltage transformation circuit, a power end, a first voltage input end and a second voltage input end; the management chip comprises a power supply end, and the power supply end is connected with the power supply end; the power supply comprises a first power supply chip, wherein the input end of the first power supply chip is connected with a power supply end, the output end of the first power supply chip is connected with a first voltage input end, and the output end of the first power supply chip outputs a first voltage; and the input end of the second power supply chip is connected with the power supply end, the output end of the second power supply chip is connected with the second voltage input end, and the output end of the second power supply chip outputs the second voltage. The embodiment of the invention can ensure that the controller normally supplies the first voltage and the second voltage when the power supply of the controller chip is in a problem. And the controller can be debugged and verified according to the normal development flow, so that the development progress is ensured.
Description
Technical Field
The embodiment of the invention relates to a controller technology, in particular to a controller, a control system and a vehicle.
Background
With the development of new energy electric vehicles, the number of controllers on the vehicles is also increased. The stability and reliability of the controller is a focus of attention.
Taking a whole vehicle controller as an example, the whole vehicle controller judges the driving intention of a driver by collecting signals such as an accelerator pedal, a brake pedal and the like, monitors vehicle state information, sends a control instruction to a vehicle motor battery system, and simultaneously carries out tasks such as energy management, fault diagnosis and the like of the whole vehicle. The reliability of the system is related to the driving safety.
Considering the harsh conditions of real vehicle application, the problems that a Microcontroller (MCU) chip of the first streaming chip possibly exists in the real vehicle application process, the development period of the microcontroller chip and an automobile controller can be influenced by parallel development, and the like. Existing controller circuit designs are inadequate to address the above-described issues.
Disclosure of Invention
The invention provides a controller, which ensures that an automobile controller can be debugged and verified according to a normal development flow when an MCU has a problem. The stability and the reliability of the automobile controller are guaranteed, and the safety of the automobile is further guaranteed.
In a first aspect, an embodiment of the present invention provides a controller, including:
the controller chip comprises a first voltage transformation circuit, a second voltage transformation circuit, a power end, a first voltage input end and a second voltage input end, wherein the first voltage transformation circuit is used for providing a first voltage, and the second voltage transformation circuit is used for providing a second voltage;
the management chip comprises a power supply end, and the power supply end is connected with the power supply end;
the input end of the first power supply chip is connected with the power supply end, the output end of the first power supply chip is connected with the first voltage input end, and the output end of the first power supply chip outputs the first voltage;
the input end of the second power chip is connected with the power supply end, the output end of the second power chip is connected with the second voltage input end, and the output end of the second power chip outputs the second voltage.
Optionally, the device further comprises a bus transceiver chip, a key door signal wire is respectively connected with the controller chip and the management chip, a first communication bus is connected with the management chip, a direct-current charging signal wire and an alternating-current charging signal wire are both connected with a wake-up end of the bus transceiver chip, and a second communication bus is connected with the bus transceiver chip;
the wake-up signals output by the key door signal line, the first communication bus, the second communication bus, the direct-current charging signal line and the alternating-current charging signal line can wake up the controller;
the key door signal line, the first communication bus, the second communication bus, the direct-current charging signal line and the alternating-current charging signal line all output dormancy signals, and the controller enters dormancy.
Optionally, during power-on reset, the management chip sends a reset signal to a reset input pin of the controller chip, and after the controller chip resets, the management chip sends a reset signal to the bus transceiver chip through an input and output end of the controller chip;
when the brushing program is reset, the external writer sends a reset signal to a reset input pin of the controller chip, and the controller chip is reset;
when in fault reset, the watchdog circuit of the management chip sends a reset signal to a reset input pin of the controller chip, and the controller chip is reset; when the controller chip diagnoses that the bus transceiver chip works abnormally, the input and output ends of the controller chip send reset signals to the bus transceiver chip.
Optionally, the controller further comprises an input processing circuit, wherein a signal output end of the input processing circuit is connected with an input end and an output end of the controller chip, a signal input end of the input processing circuit is used for receiving signals, and the input processing circuit comprises a transient diode pad, a first capacitor pad, a second capacitor pad, a first diode pad, a second diode pad, a third diode pad, a first resistor pad, a second resistor pad, a third resistor pad, a fourth resistor pad, a fifth resistor pad, a sixth resistor pad and a seventh resistor pad;
the signal input terminal is respectively connected with a first end of the transient diode pad, a first end of the first capacitor pad, a negative end of the first diode pad and a first end of the first resistor pad, a second end of the transient diode pad is grounded to a second end of the first capacitor pad, a positive end of the first diode pad, a second end of the first resistor pad, a first end of the second resistor pad, a first end of the fourth resistor pad and a first end of the fifth resistor pad are connected, a second end of the second resistor pad is connected with a battery power supply terminal, a second end of the third resistor pad is grounded, a second end of the fourth resistor pad is connected with a logic power supply terminal, a second end of the fifth resistor pad, a first end of the sixth resistor pad is connected with a first end of the seventh resistor pad, a second end of the sixth resistor pad is grounded to the second end of the seventh resistor pad, a second end of the third resistor pad is connected with a second end of the third resistor pad, a positive end of the third resistor pad is connected with a second end of the positive end of the third resistor pad, a second end of the third resistor pad is connected with a second end of the positive end of the third diode is connected with a power supply terminal of the third diode.
Optionally, the device further comprises a clock circuit, wherein the clock circuit comprises a passive crystal oscillator circuit and an active crystal oscillator circuit, the passive crystal oscillator circuit is connected with the controller chip through a clock output end and a clock input end of the controller chip, the active crystal oscillator circuit comprises an active crystal oscillator and an on-off selector, an output end of the active crystal oscillator is connected with a first end of the on-off selector, and a second end of the on-off selector is connected with the clock input end of the controller chip.
Optionally, the device further comprises a storage chip, wherein the storage chip is connected with the controller chip and is used for backing up data stored by the controller chip under preset conditions.
Optionally, the controller chip sends control information to the management chip through the serial bus, the management chip outputs a driving signal according to the control information, and the controller chip acquires the driving signal and judges whether the information carried by the driving signal is normal or not.
Optionally, the device further comprises a power switch chip, the controller chip outputs control information through an output end of the controller chip, the power switch chip outputs a driving signal according to the control information, the controller chip acquires the driving signal and judges whether information carried by the driving signal is normal or not.
In a second aspect, an embodiment of the present invention further provides a control system, including any one of the controllers described above.
In a third aspect, an embodiment of the present invention further provides a vehicle, including the control system described above.
The controller in the embodiment of the invention comprises: the controller comprises a first voltage transformation circuit, a second voltage transformation circuit, a power end, a first voltage input end and a second voltage input end, wherein the first voltage transformation circuit is used for providing a first voltage, and the second voltage transformation circuit is used for providing a second voltage; the management chip comprises a power supply end, and the power supply end is connected with the power supply end; the power supply comprises a first power supply chip, wherein the input end of the first power supply chip is connected with a power supply end, the output end of the first power supply chip is connected with a first voltage input end, and the output end of the first power supply chip outputs a first voltage; and the input end of the second power supply chip is connected with the power supply end, the output end of the second power supply chip is connected with the second voltage input end, and the output end of the second power supply chip outputs the second voltage. The embodiment of the invention can ensure that the controller normally supplies the first voltage and the second voltage when the controller chip has a problem. And further, the controller can be debugged and verified according to a normal development flow. The stability and the reliability of the automobile controller are guaranteed, and the safety of the automobile is guaranteed.
Drawings
Fig. 1 is a schematic structural diagram of a controller according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another controller according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another controller according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another controller according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of another controller according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another controller according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Fig. 1 is a schematic structural diagram of a controller according to an embodiment of the present invention, see fig. 1. The embodiment of the invention provides a controller, which comprises:
the controller chip U1 comprises a first voltage transformation circuit, a second voltage transformation circuit, a power end, a first voltage input end and a second voltage input end, wherein the first voltage transformation circuit is used for providing a first voltage, and the second voltage transformation circuit is used for providing a second voltage;
the management chip U2 comprises a power supply end, and the power supply end is connected with a power supply end;
the power supply circuit comprises a first power supply chip U3, wherein the input end of the first power supply chip U3 is connected with a power supply end, the output end of the first power supply chip U3 is connected with a first voltage input end, and the output end of the first power supply chip U3 outputs a first voltage;
and the input end of the second power supply chip U4 is connected with the power supply end, the U4 output end of the second power supply chip is connected with the second voltage input end, and the output end of the second power supply chip U4 outputs the second voltage.
The controller provided by the embodiment of the invention can be any controller in a vehicle, and the controller is taken as a whole Vehicle Controller (VCU) for illustration. The controller chip U1 may be a Microcontroller (MCU), and the management chip U2 may be a chip for automobile engine system management, such as an L9788 chip. The first power chip U3 and the second power chip U4 may be selected according to the first voltage and the second voltage actually required.
Because the VCU has the dormancy and awakening requirements, the VCU logic power supply is supplied by the VBD of the constant voltage battery terminal of the whole vehicle. The VBD of the constant-voltage battery terminal of the whole vehicle can supply power in a VCU dormant state to provide power for the VCU in real time. The management chip U2 is powered by the anti-reflection diode D1, the filter circuit and the filter capacitor C1. The anti-reverse diode D1 protects the VCU from accidental reverse connection of the battery, and the filter circuit is used for smoothing system noise and improving electromagnetic compatibility (EMC) of the VCU. The specific structure of the filter circuit can be determined according to actual requirements. For example, the filter circuit may comprise a pi-type filter.
The management chip U2 may be an L9788 chip. The chip also comprises the functions of power management, MCU monitoring, controller Area Network (CAN) communication/Local Interconnect Network (LIN) communication, driving and the like. In terms of power supply, the 5V voltage (the current supply capability 1A) provided by the chip can meet the logic power supply requirements of all chips in the VCU controller. Meanwhile, the L9788 chip generates 3 paths of sensor power supply, has diagnosis and protection functions, and can supply power to the external sensor of the VCU.
The MCU receives the L9788 power supply, and the MCU chip generates a first voltage of 3.3V through an internal low dropout linear voltage regulator (LDO) to supply power to the FLASH memory device, the clock module and the like; the core is powered by an internal BUCK circuit (BUCK) to generate a 1.1V core voltage, i.e., a second voltage. The power supply time sequence can be controlled according to MCU setting.
Considering the MCU fault condition, through setting up first power chip and second power chip in order to guarantee under the unusual circumstances of MCU inside LDO circuit and BUCK circuit work, supply power for MCU through external compatible circuit, first power chip and second power chip promptly. Whether the power supply mode is externally or internally powered by the MCU is confirmed through the mounting or non-mounting of the first 0ohm resistor R1 and the second 0ohm resistor R2 and the power supply selection pin configuration of the MCU.
The external power supply configuration mode may be: external power supply is selected and used by adjusting the configuration of 3.3V and 1.1V power supply selection pins on the MCU, 0ohm resistors are attached to the positions of the first 0ohm resistor R1 and the second 0ohm resistor R2, and 3.3V and 1.1V power supply of the MCU is provided by the first power supply chip and the second power supply chip. The internal power supply configuration mode may be: the 3.3V and 1.1V power supply selection pins on the MCU are configured to select internal power supply, the first 0ohm resistor R1 and the second 0ohm resistor R2 are not attached with resistors, and the MCU is reduced in voltage by using an internal LDO circuit and a BUCK circuit so as to provide a first voltage and a second voltage.
The power supply modes of the first voltage and the second voltage can be respectively configured, and whether the MCU is used for external power supply or internal power supply can be selected by configuring the MCU power supply mode. The power supply device can also be configured to supply power to the interior and the exterior of the MCU simultaneously so as to enhance the current supply capability and make up for the problem of insufficient current supply capability of the internal circuit of the MCU. If the MCU circuit works normally, the first power chip, the second power chip and related peripheral circuits can be not mounted, so that the number of devices on an electronic bill of materials (BOM) is saved, and the cost is reduced. The power-on time sequence of the first power chip and the second power chip can be configured by carrying out pull-up enabling of the front-stage voltage according to MCU time sequence requirements. The level of the first voltage (3.3V) power supply selection pin can be adjusted by adjusting the resistance relation between the first power supply selection resistor R3 and the second power supply selection resistor R4, and the level of the second voltage (1.1V) power supply selection pin can be adjusted by adjusting the resistance relation between the third power supply selection resistor R5 and the fourth power supply selection resistor R6, so that the power-on time sequence of the first power chip and the second power chip of the MCU is determined. The embodiment of the invention can ensure that the controller normally supplies the first voltage and the second voltage when the controller chip has a problem. And further, the controller can be debugged and verified according to a normal development flow. The stability and the reliability of the automobile controller are guaranteed, and the safety of the automobile is guaranteed.
Fig. 2 is a schematic structural diagram of another controller according to an embodiment of the present invention, see fig. 2. In other embodiments, the controller further includes a bus transceiver chip U5, the key door signal line IG is connected to the controller chip U1 and the management chip U2, the first communication bus CAN1 is connected to the management chip U2, the DC charging signal line DC and the AC charging signal line AC are both connected to the wake-up end of the bus transceiver chip U5, and the second communication bus CAN2 is connected to the bus transceiver chip U5;
the wake-up signals output by the key door signal line IG, the first communication bus CAN1, the second communication bus CAN2, the direct-current charging signal line DC and the alternating-current charging signal line AC CAN wake up the controller;
the key door signal line IG, the first communication bus CAN1, the second communication bus CAN2, the direct-current charging signal line DC and the alternating-current charging signal line AC all output sleep signals, and the controller goes to sleep.
The bus transceiver chip U5 may be any chip for assisting the MCU in performing bus transceiver, for example, may be a CAN bus transceiver chip, and the bus transceiver chip U5 may be a TJA1043 chip. The VCU may be awakened by an awakening source while in a sleep state. The VCU wakeup source may include five: a key door wake-up signal on a key door signal line IG, a first CAN message wake-up signal on a first communication bus CAN 1; a second CAN message wake-up signal on a second communication bus CAN 2; the alternating current charging gun on the alternating current charging signal line AC inserts the wake-up signal, and the direct current charging gun on the direct current charging signal line DC inserts the wake-up signal. The KEY door signal IG wakes up through a KEY entry pin KEY_IN of the triggering management chip, and the message of the first communication bus CAN1 wakes up through an internal wake-up module of the management chip; the second CAN message wake-up signal on the second communication bus CAN2 is realized by inserting the wake-up signal into the alternating current charging gun on the alternating current charging signal line AC and triggering the wake-up input pin WK_IN of the management chip through the pin of the bus transceiver chip by inserting the wake-up signal into the direct current charging gun on the direct current charging signal line DC. Any one of the five wake-up sources may trigger the controller to wake-up from the sleep state.
When the MCU detects that the key door signal IG is powered down through the input and output pins, other wake-up sources are confirmed to be in an inactive state, namely, sleep logic is started, data processing and state recording of the controller are carried out, and then the controller enters the sleep state.
Further, during power-on reset, the management chip sends a reset signal to a reset input pin of the controller chip, and after the controller chip resets, the management chip sends the reset signal to the bus transceiver chip through an input and output end of the controller chip;
when the brushing program is reset, the external writer sends a reset signal to a reset input pin of the controller chip, and the controller chip is reset;
when the fault is reset, the watchdog circuit of the management chip sends a reset signal to a reset input pin of the controller chip, and the controller chip resets; when the controller chip diagnoses the abnormal operation of the bus transceiver chip, the input and output ends of the controller chip send reset signals to the bus transceiver chip.
The internal circuit of the controller has three reset modes, namely power-on reset, program reset and fault reset. The following will describe the three resetting modes.
And (5) power-on reset: when the power is initially applied, the L9788 is powered on and after the self-checking is finished, a reset signal is sent to a reset input pin of the MCU, the MCU resets and enables other peripheral chips including the bus transceiver chip through the input and output pins, and then the VCU enters a normal working state.
And (5) resetting a brushing program: when the VCU writes the program, the writer can send a reset signal to a reset input pin of the MCU, and the MCU resets and prepares for programming.
Fault reset: after the MCU has a fault state (such as software running, etc.), the watchdog in the L9788 is triggered, and the L9788 sends a reset signal to a reset input pin of the MCU, so that the MCU resets. When the MCU diagnoses that the specific chip works abnormally, the specific chip (such as a bus transceiver chip or a power switch chip and the like) can be reset, so that the specific chip works again. The power switching chips may include a first power switching chip U6 and a second power switching chip U7. The first power switch chip U6 may be TLE8110 and the second power switch chip U7 may be TLE9104. The MCU can perform a reset operation on the TLE8110 and TLE9104 by controlling the reset terminal RST and the enable terminal EN.
Fig. 3 is a schematic structural diagram of another controller according to an embodiment of the present invention, see fig. 3. In other embodiments, the controller further includes an input processing circuit, a signal output terminal of the input processing circuit is connected to an input/output terminal of the controller chip, and a signal input terminal of the input processing circuit is used for receiving a signal, where the input processing circuit includes a transient diode D2 pad, a first capacitor C5 pad, a second capacitor C6 pad, a first diode D3 pad, a second diode D4 pad, a third diode D5 pad, a first resistor R7 pad, a second resistor R8 pad, a third resistor R9 pad, a fourth resistor R10 pad, a fifth resistor R11 pad, a sixth resistor R12 pad, and a seventh resistor R13 pad;
the signal input end is respectively connected with a first end of a transient diode D2 bonding pad, a first end of a first capacitor C5 bonding pad, a negative end of a first diode D3 bonding pad and a first end of a first resistor R7 bonding pad, a second end of the transient diode D2 bonding pad and a second end of the first capacitor C5 bonding pad are grounded, a positive end of the first diode D3 bonding pad, a second end of the first resistor R7 bonding pad, a first end of a second resistor R8 bonding pad, a first end of a third resistor R9, a first end of a fourth resistor R10 bonding pad and a first end of a fifth resistor R11 bonding pad, a second end of the second resistor R8 bonding pad is connected with a battery power supply end VBD, a second end of the third resistor R9 bonding pad is grounded, a second end of the fourth resistor R10 bonding pad is connected with a logic power supply end VDD, a second end of the fifth resistor R11 bonding pad, a first end of a sixth resistor R12 bonding pad and a first end of a seventh resistor R13 bonding pad are connected with a second end of a third resistor, a second end of a seventh resistor R12 bonding pad is grounded, a second end of the seventh resistor R13 bonding pad, a second end of the second resistor R13 bonding pad, a second end of the third resistor R13 bonding pad is connected with a positive end of a third diode D4 bonding pad and a second end of a third diode C5 bonding pad is connected with a positive end of a third diode D6, and a second end of a third end of a diode D is connected with a positive end of a third diode C5 bonding pad.
The logic power supply terminal VDD is used for supplying power to the logic circuit, and the battery power supply terminal VBD is used for continuously supplying voltage to the controller. The transient diode D2 and the first capacitor C5 play a role in electrostatic protection, and may be selected from one of them in the practical application process. When the rate of change of the signal rate is fast, the bidirectional transient diode D2 having a small parasitic capacitance is used, and when the rate of change of the signal rate is slow, the absorption capacitance, that is, the first capacitance C5 may be used.
The first diode D3 is used to prevent the current of other controllers from flowing backward into the VCU controller through the interface when the same input quantity is connected to multiple controllers. In the absence of this, a 0ohm (ohm) resistor is attached to the first resistor R7 pad to bypass the first diode D3, or a Printed Circuit Board (PCB) trace is directly used to short the first diode D3 at design time. The first diode D3 is typically selected not to be mounted in the analog type input signal so as not to affect the normal function of the circuit for the voltage type analog quantity or to affect the analog quantity accuracy for the resistance type analog quantity.
The third resistor R9 is used for diagnosing frequency quantity input and partial voltage type analog quantity input signals, can diagnose the condition that an interface is open or short-circuited to a power supply, and meanwhile, the third resistor R9 can provide a default state for a high-effective switching quantity input circuit, so that the high-effective switching quantity can be effectively identified. Low-efficiency switching values and resistive analog values are not typically mounted.
The second resistor R8 is pulled up to the voltage of the battery supply VBD, and the fourth resistor R10 is pulled up to the voltage of the logic supply terminal VDD. The voltage of the logic supply terminal VDD may be determined according to actual needs, for example, the voltage of the logic supply terminal VDD may be 5V for VCU. The voltage of the logic power supply terminal VDD may be selected according to different MCU chips, for example, may also be 3.3V or other voltage values. The second resistor R8 and the fourth resistor R10 are not mounted at the same time. The second resistor R8 is typically selected for mounting and the fourth resistor R10 is not. The second resistor R8 is selected not to be mounted and the fourth resistor R10 is selected to be mounted by inputting a resistive analog quantity. For the analog quantity of the high effective signal and the voltage to be input, neither the second resistor R8 nor the fourth resistor R10 is mounted. The second resistor R8 or the fourth resistor R10 can also be used as a diagnostic basis for whether the frequency and resistance analog signal interface states are in an open circuit or a short circuit to ground. Meanwhile, the fourth resistor R10 can input a high-level default state for the low-effective switching value, so that the low-effective switching value can be effectively identified.
The fifth resistor R11 and the sixth resistor R12 form a voltage dividing circuit, and are used for adjusting the signal level input to the MCU, so that when the MCU interface level design deviates, the high level and the low level which can be identified by the MCU can still be input.
The seventh resistor R13 and the second capacitor C6 form a resistor-capacitor (RC) filter circuit for filtering noise and adjusting the signal response time.
The fifth resistor R11 and the seventh resistor R13 can be used as current limiting resistors simultaneously to limit the current flowing into the MCU, and the resistance adjustment of the fifth resistor R11 and the seventh resistor R13 is carried out aiming at the signal voltage and the MCU current filling threshold, so that the MCU is prevented from being damaged by high current.
The second diode D4 and the third diode D5 form a clamping circuit, which is used for an MCU chip without internal clamping, and avoids unnecessary damage to the MCU caused by noise and short circuit conditions of real vehicle application. If the MCU has an internal clamping circuit, the external clamping circuit formed by the second diode D4 and the third diode D5 can not be pasted. The input processing circuit in the embodiment of the invention is connected with the input and output ends of the controller chip, so that the MCU interface requirement can be met by adjusting the element model on the premise of ensuring that the PCB is not adjusted to the maximum extent. The number of plate changing times is reduced, and the project time is shortened.
Fig. 4 is a schematic structural diagram of another controller according to an embodiment of the present invention, see fig. 4. In other embodiments, the controller further includes a clock circuit, the clock circuit includes a passive crystal oscillator circuit and an active crystal oscillator circuit, the passive crystal oscillator circuit is connected with the controller chip U1 through a clock output end and a clock input end of the controller chip, the active crystal oscillator circuit includes an active crystal oscillator and an on-off selector, an output end Clk of the active crystal oscillator is connected with a first end of the on-off selector, and a second end of the on-off selector is connected with a clock input end of the controller chip.
The passive crystal oscillator circuit may include a passive crystal oscillator X1, where two ends of the passive crystal oscillator X1 are respectively connected to a clock output end and a clock input end of the controller chip. In order to avoid the influence of electromagnetic interference on a clock circuit and improve the accuracy of a passive crystal oscillator X1 signal, a resonant circuit can be added, two ends of the passive crystal oscillator X1 can be respectively connected with a capacitor, and the other end of the capacitor is grounded. The resistors can be connected in parallel to the two ends of the passive crystal oscillator X1, so that the passive crystal oscillator X1 is in a linear state at the initial stage of oscillation. The active crystal oscillator circuit comprises an active crystal oscillator, an active crystal oscillator chip and an on-off selector used for controlling whether the active crystal oscillator chip is communicated with the clock input end. The on-off selector may be a resistive pad that determines whether the clock signal is provided by the active crystal oscillator circuit by selecting whether a 0ohm resistor is soldered. The active crystal oscillator circuit can also be a switch circuit, and whether the active crystal oscillator circuit provides a clock signal for the MCU is selected by selecting the on and off states of the switch. The active crystal oscillator circuit can also be a pair of jump pins, and whether the active crystal oscillator circuit provides a clock signal for the MCU is selected by whether a jumper cap is inserted or not. The active crystal oscillator chip comprises a power end and a grounding end GND, the logic power end VDD supplies voltage to the power end of the active crystal oscillator chip, and the grounding end GND is grounded. The clock circuit provided by the embodiment of the invention is compatible with the active crystal oscillator and the passive crystal oscillator, if the MCU vibration starting circuit works normally, the passive crystal oscillator X1 and the resonance circuit thereof provide clocks for the MCU, and if the vibration starting circuit does not work, the 0ohm resistor can be repair welded, and the active crystal oscillator is used for providing working clocks for the MCU. The influence of MCU starting circuit abnormality on development progress is reduced.
Fig. 5 is a schematic structural diagram of another controller according to an embodiment of the present invention, see fig. 5. In other embodiments, the controller further includes a memory chip U8, where the memory chip U8 is connected to the controller chip U1, and is used for backing up the data stored in the controller chip under a preset condition.
The memory chip U8 is used for backing up data stored in the controller chip U1, and the memory chip U8 may be any chip for storing data, for example, an Electrically Erasable Programmable Read Only Memory (EEPROM) chip. The EEPROM chip can perform data transmission with the MCU through a first Serial Peripheral Interface (SPI) bus.
Fig. 6 is a schematic structural diagram of another controller according to an embodiment of the present invention, see fig. 6. In other embodiments, the controller chip sends control information to the management chip through the serial bus, the management chip outputs a driving signal according to the control information, and the controller chip acquires the driving signal and judges whether the information carried by the driving signal is normal or not. The controller can also comprise a power switch chip, the controller chip outputs control information through the output end of the controller chip, the power switch chip outputs a driving signal according to the control information, the controller chip acquires the driving signal and judges whether the information carried by the driving signal is normal or not.
The serial bus may include a microsecond channel (MSC), among other things. The power switching chips may include a first power switching chip U6 and a second power switching chip U7. The first power switch chip U6 may be TLE8110 and the second power switch chip U7 may be TLE9104. Because L9788 is controlled by MCU through MSC bus, TLE8110 and TLE9104 are directly driven by MCU, the driving circuit combining the two can adapt to different driving modes of MCU in compatible mode. Preferably, the L9788 single chip drive scheme, where L9788 may be normally driven, the TLE8110 and TLE9104 and their associated circuitry may not be mounted. For the driving of the L9788 chip, the MCU sends control information through a microsecond channel, and the L9788 chip controls the control information through a 3-path low-side frequency type driving output channel PWM DRV and a 9-path low-side switch type driving output channel LS DRV. And when the TLE8110 and TLE9104 chips are adopted for driving, the MCU sends control information through a 3-path Pulse Width Modulation (PWM) output channel PWM OUT and a 9-path input/output end IO OUT, and the MCU also controls the TLE8110 and TLE9104 chips through a first SPI channel SPI1, a second SPI channel SPI2, an enable channel EN and a Reset channel Reset. The TLE8110 and TLE9104 chips control the control information through the 3-way low side frequency type drive output channel PWM DRV and the 9-way low side switch type drive output channel LS DRV. For each path of driving output channel, an input processing circuit is added to collect output signals, the MCU is used for signal collection, and the output signals are compared with the output signals, so that whether the output signals are normal or not is confirmed. Therefore, the acquired signal can be found out to be different from the output signal in time, and the abnormal information is reported.
The embodiment of the invention also provides a control system which comprises any one of the controllers.
The control system provided by the embodiment of the invention comprises the controller provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects.
The embodiment of the invention also provides a vehicle comprising the control system.
The vehicle provided by the embodiment of the invention comprises the control system provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, and that various obvious changes, rearrangements, combinations, and substitutions can be made by those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (10)
1. A controller, comprising:
the controller chip comprises a first voltage transformation circuit, a second voltage transformation circuit, a power end, a first voltage input end and a second voltage input end, wherein the first voltage transformation circuit is used for providing a first voltage, and the second voltage transformation circuit is used for providing a second voltage;
the management chip comprises a power supply end, and the power supply end is connected with the power supply end;
the input end of the first power supply chip is connected with the power supply end, the output end of the first power supply chip is connected with the first voltage input end, and the output end of the first power supply chip outputs the first voltage;
the input end of the second power supply chip is connected with the power supply end, the output end of the second power supply chip is connected with the second voltage input end, and the output end of the second power supply chip outputs the second voltage;
the controller chip receives the power supply of the management chip, and supplies power to the FLASH memory device and the clock module through the first voltage generated by the internal low-dropout linear voltage regulator; supplying power to the core through a second voltage generated by the internal voltage reducing circuit;
when the power supply mode is an external power supply configuration mode, external power supply is selected to be used by adjusting the configuration of a FLASH memory device and a clock module on a controller chip and a power supply selection pin of a kernel, and a 0ohm resistor is attached to the positions of a first 0ohm resistor and a second 0ohm resistor, and first voltage and second voltage required by the FLASH memory device and the clock module of the controller chip and the kernel are provided by a first power supply chip and a second power supply chip;
when the power supply mode is an internal power supply configuration mode, the FLASH memory device and the clock module on the controller chip and the power supply selection pins of the kernel are configured and selected to use internal power supply, the positions of the first 0ohm resistor and the second 0ohm resistor are not attached with the resistor, and the controller chip uses an internal low-dropout linear voltage regulator and an internal voltage reducing circuit to provide the first voltage and the second voltage.
2. The controller of claim 1, further comprising a bus transceiver chip, wherein the controller chip and the management chip are both connected to a key door signal line, wherein the management chip is connected to a first communication bus, wherein a wake-up end of the bus transceiver chip is connected to both a dc charging signal line and an ac charging signal line, and wherein the bus transceiver chip is connected to a second communication bus;
the wake-up signals output by the key door signal line, the first communication bus, the second communication bus, the direct-current charging signal line and the alternating-current charging signal line can wake up the controller;
the key door signal line, the first communication bus, the second communication bus, the direct-current charging signal line and the alternating-current charging signal line all output dormancy signals, and the controller enters dormancy.
3. The controller of claim 2, wherein the management chip sends a reset signal to a reset input pin of the controller chip during power-on reset, and the controller chip sends a reset signal to the bus transceiver chip through an input and output terminal of the controller chip after reset;
when the brushing program is reset, the external writer sends a reset signal to a reset input pin of the controller chip, and the controller chip is reset;
when in fault reset, the watchdog circuit of the management chip sends a reset signal to a reset input pin of the controller chip, and the controller chip is reset; when the controller chip diagnoses that the bus transceiver chip works abnormally, the input and output ends of the controller chip send reset signals to the bus transceiver chip.
4. The controller of claim 1, further comprising an input processing circuit, a signal output of the input processing circuit being coupled to an input output of the controller chip, a signal input of the input processing circuit being configured to receive a signal, the input processing circuit comprising a transient diode pad, a first capacitive pad, a second capacitive pad, a first diode pad, a second diode pad, a third diode pad, a first resistive pad, a second resistive pad, a third resistive pad, a fourth resistive pad, a fifth resistive pad, a sixth resistive pad, a seventh resistive pad;
the signal input terminal is respectively connected with a first end of the transient diode pad, a first end of the first capacitor pad, a negative end of the first diode pad and a first end of the first resistor pad, a second end of the transient diode pad is grounded to a second end of the first capacitor pad, a positive end of the first diode pad, a second end of the first resistor pad, a first end of the second resistor pad, a first end of the fourth resistor pad and a first end of the fifth resistor pad are connected, a second end of the second resistor pad is connected with a battery power supply terminal, a second end of the third resistor pad is grounded, a second end of the fourth resistor pad is connected with a logic power supply terminal, a second end of the fifth resistor pad, a first end of the sixth resistor pad is connected with a first end of the seventh resistor pad, a second end of the sixth resistor pad is grounded to the second end of the seventh resistor pad, a second end of the third resistor pad is connected with a second end of the third resistor pad, a positive end of the third resistor pad is connected with a second end of the positive end of the third resistor pad, a second end of the third resistor pad is connected with a second end of the positive end of the third diode is connected with a power supply terminal of the third diode.
5. The controller of claim 1, further comprising a clock circuit comprising a passive crystal oscillator circuit and an active crystal oscillator circuit, the passive crystal oscillator circuit being connected to the controller chip through a clock output and a clock input of the controller chip, the active crystal oscillator circuit comprising an active crystal oscillator and an on-off selector, an output of the active crystal oscillator being connected to a first end of the on-off selector, a second end of the on-off selector being connected to the clock input of the controller chip.
6. The controller of claim 1, further comprising a memory chip coupled to the controller chip for backing up data stored by the controller chip under preset conditions.
7. The controller according to claim 1, wherein the controller chip sends control information to the management chip through a serial bus, the management chip outputs a driving signal according to the control information, and the controller chip acquires the driving signal to determine whether information carried by the driving signal is normal.
8. The controller according to claim 1, further comprising a power switch chip, wherein the controller chip outputs control information through an output end of the controller chip, the power switch chip outputs a driving signal according to the control information, and the controller chip acquires the driving signal and judges whether information carried by the driving signal is normal or not.
9. A control system comprising a controller according to any one of claims 1-8.
10. A vehicle comprising the control system of claim 9.
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| US6115831A (en) * | 1996-03-26 | 2000-09-05 | Daimlerchrysler Ag | Integrated circuit for coupling a microcontrolled control apparatus to a two-wire bus |
| CN104859565A (en) * | 2014-07-28 | 2015-08-26 | 北汽福田汽车股份有限公司 | Power management circuit, method and system |
| CN109828506A (en) * | 2019-02-20 | 2019-05-31 | 普华基础软件股份有限公司 | A kind of new-energy automobile electronics full-vehicle control module quiescent dissipation control system |
| CN110936821A (en) * | 2019-11-26 | 2020-03-31 | 中国第一汽车股份有限公司 | Automobile motor controller, control system and automobile |
| CN212500003U (en) * | 2020-07-03 | 2021-02-09 | 北京奕为汽车科技有限公司 | Dormancy awakening circuit and system |
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2022
- 2022-03-30 CN CN202210330821.6A patent/CN114684037B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6115831A (en) * | 1996-03-26 | 2000-09-05 | Daimlerchrysler Ag | Integrated circuit for coupling a microcontrolled control apparatus to a two-wire bus |
| CN104859565A (en) * | 2014-07-28 | 2015-08-26 | 北汽福田汽车股份有限公司 | Power management circuit, method and system |
| CN109828506A (en) * | 2019-02-20 | 2019-05-31 | 普华基础软件股份有限公司 | A kind of new-energy automobile electronics full-vehicle control module quiescent dissipation control system |
| CN110936821A (en) * | 2019-11-26 | 2020-03-31 | 中国第一汽车股份有限公司 | Automobile motor controller, control system and automobile |
| CN212500003U (en) * | 2020-07-03 | 2021-02-09 | 北京奕为汽车科技有限公司 | Dormancy awakening circuit and system |
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| CN114684037A (en) | 2022-07-01 |
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