CN114678423A

CN114678423A - High voltage semiconductor device

Info

Publication number: CN114678423A
Application number: CN202110566453.0A
Authority: CN
Inventors: 郑允涵; 潘钦寒; 魏子乔
Original assignee: Nuvoton Technology Corp
Current assignee: Nuvoton Technology Corp
Priority date: 2020-12-24
Filing date: 2021-05-24
Publication date: 2022-06-28
Also published as: TW202226382A; TWI812909B

Abstract

A high voltage semiconductor device includes a substrate, a first high voltage well, a second high voltage well, a third high voltage well, a drain region, a source region, a gate structure, and a doped region. The substrate has a first conductivity type. The first high voltage well is disposed over the substrate and has a second conductivity type opposite the first conductivity type. The second high voltage well is disposed adjacent to and in contact with the first high voltage well and has the first conductivity type. The third high voltage well is disposed adjacent to and in contact with the first high voltage well and has the second conductivity type. The drain region is disposed within the first high voltage well. The gate structure is disposed between the source region and the drain region. The doped region is disposed within the third high-voltage well and has the second conductivity type.

Description

High voltage semiconductor device

Technical Field

The present invention relates to a high voltage semiconductor device, and more particularly, to a high voltage semiconductor device having a doped region in an external high voltage well.

Background

Semiconductor Integrated Circuit (IC) technology has been rapidly developed, wherein high voltage semiconductor device technology is developed for high voltage and high power applications. The high voltage semiconductor device includes a Vertical Diffused Metal Oxide Semiconductor (VDMOS) transistor and a Lateral Diffused Metal Oxide Semiconductor (LDMOS) transistor, and has advantages of cost effectiveness, and is easily compatible with other processes, and has been widely applied to the fields of display driving IC devices, power supplies, power management, communications, automotive electronics, or industrial control, etc.

While the prior art of high voltage semiconductor devices has been generally adequate for their intended purposes, they have not been satisfactory in every aspect. As high voltage semiconductor device technology advances, it is expected that high voltage semiconductor devices may have a greater operating voltage and, therefore, require a greater breakdown voltage. Therefore, there is a need for a high voltage semiconductor device having a greater breakdown voltage.

Disclosure of Invention

The invention provides a high-voltage semiconductor device. The high-voltage semiconductor device comprises a substrate, a first high-voltage well, a second high-voltage well, a third high-voltage well, a drain region, a source region, a gate structure and a doped region. The substrate has a first conductivity type. The first high voltage well is disposed over the substrate and has a second conductivity type opposite the first conductivity type. The second high voltage well is disposed adjacent to and in contact with the first high voltage well and has the first conductivity type. The third high voltage well is disposed adjacent to and in contact with the first high voltage well and has the second conductivity type. The drain region is disposed within the first high-voltage well. The gate structure is disposed between the source region and the drain region. The doped region is disposed within the third high voltage well and has a second conductivity type.

In some embodiments, the high voltage semiconductor device further includes a buried layer disposed under the second and third high voltage wells and having the second conductive type.

In some embodiments, a boundary of the buried layer is spaced apart from a boundary between the first high voltage well and the second high voltage well by a predetermined distance.

In some embodiments, the high voltage semiconductor device further comprises a dielectric layer, a metal contact, and a metal layer. The dielectric layer is disposed over the substrate. A metal contact is disposed in the dielectric layer and contacts the doped region. The metal layer is disposed over the dielectric layer and contacts the metal contact.

In some embodiments, a ratio of a depth of the doped region to a depth of the third high voltage well is in a range of 0.006 to 0.01.

The invention provides a high-voltage semiconductor device. The high-voltage semiconductor device comprises a substrate, a high-voltage well, a first annular well, a second annular well, a drain region, an annular gate structure, an annular source region and an annular doped region. The high voltage well is disposed over the substrate and has a first conductivity type dopant. A first ring-shaped well is disposed around and contacting the high voltage well and has a second conductivity type dopant opposite the first conductivity type dopant. The second ring-shaped well is disposed around the first ring-shaped well and has the first conductive type dopant. The drain region is disposed in the high voltage well. An annular gate structure is disposed over the high voltage well and surrounds the drain region. An annular source region is disposed in the first annular well and surrounds the annular gate structure. The ring-shaped doped region is disposed in the second ring-shaped well and has a first conductive type dopant.

In some embodiments, the high voltage semiconductor device further includes an annular buried layer disposed below the first and second ring wells and having the first conductive type dopant.

In some embodiments, the inner boundary of the annular buried layer is a predetermined distance from the outer boundary of the high voltage well.

In some embodiments, the high voltage semiconductor device further comprises a dielectric layer, a metal contact, and a metal layer. The dielectric layer is disposed over the substrate. A metal contact is disposed in the dielectric layer and contacts the annular doped region. The metal layer is disposed over the dielectric layer and contacts the metal contact.

In some embodiments, a ratio of a depth of the ring-shaped doped region to a depth of the second ring-shaped well is in a range of 0.006 to 0.01.

As the technology of high voltage semiconductor devices advances, it is expected that the high voltage semiconductor devices may have a larger operating voltage. Therefore, the high voltage well as the isolation region needs to be improved to have a larger breakdown voltage to prevent the high voltage semiconductor device from affecting the adjacent devices in the operation of larger operation voltage.

Drawings

In order that the manner in which the present invention is described is to cover the examples provided above, together with other advantages and features thereof, a more particular description of the principles briefly described above will be rendered by reference to specific examples thereof which are illustrated in the appended drawings. It is to be understood that the drawings described herein are illustrative of the invention and are not to be considered as limiting the scope of the invention. The principles of the present invention are described and explained with additional specificity and detail through the use of the accompanying drawings in which:

Fig. 1A is a top view of a high voltage semiconductor device with doped regions in an isolated high voltage well according to an embodiment of the present invention.

Fig. 1B is a cross-sectional view of a high voltage semiconductor device having doped regions in an isolated high voltage well according to an embodiment of the present invention.

Fig. 2 is a graph comparing breakdown voltages of the high voltage semiconductor device according to the embodiment of the present invention and a known high voltage semiconductor device.

Fig. 3 is a cross-sectional view of a high voltage semiconductor device having doped regions in an isolated high voltage well, wherein additional vias and metal layers are formed over the doped regions, in accordance with an embodiment of the present invention.

Reference numerals

100 high voltage semiconductor device

102 substrate

104 doped region

106 doped region

108 epitaxial layer

110 high voltage trap

112 high-voltage trap

114 high voltage trap

116 high voltage trap

118 drift zone

120 well

122 drain region

124 body region

126 doped region

128 doped region

130 source region

132-1: oxide structures

132-2 oxide structure

132-3 oxide structure

132-4 oxide structure

134 gate structure

136 doped region

138 doped region

140 dielectric layer

142 through hole

144 dielectric layer

146, conducting wire

148 through hole

150: conducting wire

H1 depth

H2 depth

D1 distance

202 curve line

204 curve of

152 through hole

154 conducting wire

302 circuit

304 resistance

Detailed Description

The following summary provides many different embodiments or examples for implementing different features of the disclosure. The following summary describes specific examples of components and arrangements thereof to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if the present invention recites a first feature formed on or above a second feature, that is, embodiments that may include the first feature in direct contact with the second feature may also include embodiments that include additional features formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the same reference numbers and/or designations may be reused in different examples described below. These iterations are for simplicity and clarity and are not intended to limit the particular relationship between the various embodiments and/or configurations discussed.

For purposes of this detailed description, unless specifically stated otherwise, singular words include plural words and vice versa. And the word "comprising" means "including without limitation". Furthermore, analogous (approximate) terms, such as "about", "nearly", "equivalent", "approximately", etc., may be used in connection with embodiments of the invention, in the sense of "at, near, or near" or "within 3 to 5% or" within acceptable manufacturing tolerances ", or any logical combination.

Furthermore, it is used in terms of spatial correlation. Such as "below" …, below "," lower "," over "," upper ", and the like, are used for ease of describing the relationship of one device or feature to another device or feature in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is inverted, devices described as "below" or "under …" other devices or features would then also become "above" the other devices or features. As such, the exemplary term "below" is intended to encompass both an upward and a downward interpretation. In addition, the device may be turned to a different orientation (rotated 90 degrees or at other orientations), and the spatially relative terms used herein should be interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "includes," including, "" has, "" having, "" contains, "or variants thereof are used in either the detailed description and/or the claims, such terms are intended to be inclusive in a manner similar to the term" comprising.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The present invention generally relates to high voltage semiconductor devices. In a general high voltage semiconductor device, a high voltage well is used as an isolation region at an outer periphery of the high voltage semiconductor device so that the high voltage semiconductor device does not affect adjacent devices during operation. However, as the technology of high voltage semiconductor devices advances, it is expected that the high voltage semiconductor devices may have a larger operating voltage. Therefore, the high voltage well as the isolation region needs to be improved to have a larger breakdown voltage to prevent the high voltage semiconductor device from affecting the adjacent devices in the operation of larger operation voltage.

Fig. 1A is a top view of a high voltage semiconductor device 100 according to an embodiment of the present invention, and fig. 1B is a cross-sectional view of the high voltage semiconductor device 100 according to an embodiment of the present invention. According to some embodiments, the high voltage semiconductor device 100 is formed on a substrate 102. The substrate 102 may be substantially comprised of silicon. In some embodiments, the substrate 102 may include another elemental semiconductor, such as germanium; compound semiconductors such as silicon carbide, gallium phosphide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors such as silicon germanium (SiGe), silicon carbon phosphide (SiPC), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and/or gallium indium phosphide (GaInAsP); or a combination thereof.

Alternatively, the substrate 102 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates may be fabricated by separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods.

In some embodiments, the substrate 102 may have a first conductivity type, such as a P-type conductivity type or an N-type conductivity type. Specifically, the substrate 102 may have dopants of a first conductivity type, such as P-type dopants or N-type dopants. The N-type dopant may include phosphorus (P), arsenic (As), other N-type dopants, or combinations thereof. The P-type dopant may include boron (B), indium (In), other P-type dopants, or a combination thereof.

Doped regions

104 and 106 are disposed in substrate 102. In some embodiments, the doped region 104 may have a second conductivity type (e.g., N-type conductivity type or P-type conductivity type) opposite the first conductivity type (e.g., P-type conductivity type or N-type conductivity type) of the substrate, and the doped region 106 may have the same first conductivity type as the substrate. Specifically, the doped regions 104 may have dopants of the second conductivity type (e.g., N-type dopants or P-type dopants), and the doped regions 106 may have dopants of the first conductivity type (e.g., P-type dopants or N-type dopants). The doped

regions

104 and 106 may be formed in the substrate 102 by one or more doping processes, such as a diffusion process or an ion implantation process. In some embodiments, the doping concentration of the doped region 104 may be 5 × 10 ¹²Atom/cubic centimeter (atoms/cm)³) To about 1x10¹³Atom/cubic centimeter (atoms/cm)³) And the doping concentration of the doped region 106 may be 3x10¹²atoms/cm³To about 8x10¹²atoms/cm³Within the range of (1). Furthermore, in some embodiments, the thickness of

doped regions

104 and 106 perpendicular to the top surface of substrate 102 is about 8 microns. In some embodiments,

doped regions

104 and 106 may be referred to as buried layers. In addition, as shown in fig. 1A, the doped

regions

104 and 106 are ring-shaped or have a ring-shaped layout (indicated by dashed lines) in a top view, and thus the doped

regions

104 and 106 can also be referred to as ring-shaped doped regions.

Referring to fig. 1B, an epitaxial layer 108 is disposed over the substrate 102. The epitaxial layer 108 may be an epitaxial semiconductor material (e.g., epitaxially grown silicon (Si) or other suitable material) having a first conductivity type or a second conductivity type. In some embodiments, epitaxial layer 108 may be formed by Metal Organic Chemical Vapor Deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), Molecular Beam Epitaxy (MBE), Hydride Vapor Phase Epitaxy (HVPE), Liquid Phase Epitaxy (LPE), chloride vapor phase epitaxy (Cl-VPE), other processes, or combinations thereof.

Still referring to fig. 1B,

high voltage wells

110, 112, 114, 116 are disposed in epitaxial layer 108. In some embodiments, the

high voltage wells

112, 116 may be of a first conductivity type (i.e., have first conductivity type dopants) and the

high voltage wells

110, 114 may be of a second conductivity type (i.e., have second conductivity type dopants). Similar to the doped

regions

104 and 106, the

high voltage wells

110, 112, 114, 116 may be formed in the epitaxial layer 108 by one or more doping processes. Notably, the

high voltage wells

110, 112 are adjacent to and in contact with each other, while the

high voltage wells

112, 114, 116 are spaced apart from each other. In addition, as shown in fig. 1A, the

high voltage wells

112, 114, 116 are ring-shaped or have a ring-shaped layout in a top view, and thus the

high voltage wells

112, 114, 116 may also be referred to as ring-shaped wells or ring-shaped high voltage wells, wherein the high voltage well 112 surrounds the high voltage well 110, the high voltage well 114 surrounds the high voltage well 112, and the high voltage well 116 surrounds the high voltage well 114.

Referring again to fig. 1B, the drift region 118 is disposed in the high voltage well 110, the well 120 is disposed in the drift region 118, and the drain region 122 is disposed in the well 120, wherein the drift region 118, the well 120, and the drain region 122 all have the second conductivity type (i.e., have the second conductivity type dopant). In some embodiments, the doping concentration of the drain region 122 is greater than the doping concentration of the well 120, the doping concentration of the well 120 is greater than the doping concentration of the drift region 118, and the doping concentration of the drift region 118 is greater than the doping concentration of the high voltage well 110. In some embodiments, the doping concentration of the high voltage well 110 may be 1x10 ¹²atoms/cm³To about 5x10¹²atoms/cm³In the range of (1), the doping concentration of the drift region 118 may be 6x10¹²atoms/cm³To about 9x10¹³atoms/cm³In the range of (1), the doping concentration of the well 120 may be 1 × 10¹³atoms/cm³To about 5x10¹³atoms/cm³And drain region 122 may be in the range of 1x10¹⁵atoms/cm³To about 5x10¹⁵atoms/cm³Within the range of (1).

A body region 124 is formed in the high-voltage well 112, and a source region 130 is formed in the body region 124, wherein the source region 130 includes doped

regions

126, 128. Body regions 124 and doped regions 126 are of a first conductivity type (i.e., have first conductivity type dopants) and doped regions 128 are of a second conductivity type (i.e., have second conductivity type dopants). In some embodiments, the doping concentration of the doped

regions

126, 128 is greater than the doping concentration of the body region 124, and the doping concentration of the body region 124 is greater than the doping concentration of the high voltage well 112. In some embodiments, the doping concentration of the doped

regions

126, 128 may be 1 × 10¹⁵atoms/cm³To about 5x10¹⁵atoms/cm³And the doping concentration of body region 124 may be 1x10¹³atoms/cm³To about 5x10¹³atoms/cm³Within the range of (1). As described above, similar to the

hvw wells

110, 112, 114, 116, the drift region 118, the well 120, the drain region 122, the body region 124, and the doped

regions

126 and 128 may each be formed by one or more doping processes.

A plurality of oxide structures 132-1, 132-2, 132-3, 132-4 are disposed on the epitaxial layer 108 and are partially embedded in the epitaxial layer 108. In some embodiments, the oxide structures 132-1, 132-2, 132-3, 132-4 may be composed of silicon oxide, silicon nitride, or silicon oxynitride, and may be local oxidation of silicon (LOCOS) formed by thermal oxidation. In other embodiments, the oxide structures 132-1, 132-2, 132-3, 132-4 may be Shallow Trench Isolation (STI) structures formed by an etch and deposition process.

Gate structure 134 is disposed on epitaxial layer 108 and may include a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include silicon oxide, silicon oxynitride, aluminum silicon oxide, high-k dielectric materials (e.g., hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, yttrium oxide, strontium titanate), other suitable dielectric materials, or combinations thereof, and may be formed by Chemical Vapor Deposition (CVD), spin coating (spin coating), or other suitable processes. The gate electrode layer may include amorphous silicon, polysilicon, one or more metals, metal nitrides, conductive metal oxides, other suitable materials, or combinations thereof, and may be formed by CVD, sputtering, resistive heating evaporation, e-beam evaporation, or other suitable deposition processes. Notably, as shown in fig. 1B, a portion of gate structure 134 is disposed on oxide structure 132-1. In this embodiment, the oxide structure 132-1 may be referred to as a field oxide to increase the drain to gate breakdown voltage (punch through voltage).

In some embodiments, the gate structure 134 may further include one or more work function metal layers to adjust the work function of the gate structure 134. The material of the work function metal layer may include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), aluminum (Al), tungsten nitride (WN), zirconium disilicide (ZrSi2), molybdenum disilicide (MoSi2), tantalum disilicide (TaSi2), nickel disilicide (NiSi2), titanium (Ti), silver (Ag), titanium aluminum (TiAl), titanium aluminum carbide (TiAl C), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), other suitable work function materials, or combinations thereof, and the work function metal layer may be deposited by Atomic Layer Deposition (ALD), CVD, and/or other suitable processes.

As shown in fig. 1A, the source region 130 is ring-shaped or has a ring-shaped layout in a top view, and therefore the source region 130 may also be referred to as a ring-shaped source region and surrounds the high voltage well 110 and the drain region 122. In addition, although not shown in fig. 1A, in the present embodiment, the gate structure 134 may also be a ring or have a ring layout, and therefore the gate structure 134 may also be referred to as a ring gate structure and surrounds the drain region 122. Thus, source region 130 also surrounds gate structure 134, or gate structure 134 is disposed between drain region 122 and source region 130.

The doped

regions

136, 138 may be disposed in the

high voltage wells

114 and 116, respectively, by one or more doping processes. Doped region 138 has a first conductivity type (i.e., has first conductivity type dopants) and doped region 136 has a second conductivity type (i.e., has second conductivity type dopants). In some embodiments, the doping concentration of the doped

regions

136, 138 are individually greater than the doping concentration of the

high voltage wells

114 and 116. In thatIn some embodiments, the doping concentration of the doped

regions

136, 138 may be 1 × 10¹⁵atoms/cm³To about 5x10¹⁵atoms/cm³Within the range of (1). In addition, as shown in fig. 1A, the doped

regions

136 and 138 are ring-shaped or have a ring-shaped layout in a top view, and therefore the

doped regions

136 and 138 may also be referred to as ring-shaped doped regions, in which the doped region 136 surrounds the hvw 110, the drain region 122, the gate structure 134, the hvw 112, and the source region 130, and the doped region 138 surrounds the hvw 110, the drain region 122, the gate structure 134, the hvw 112, the source region 130, the hvw 114, and the doped region 136.

Referring again to fig. 1B, an interconnect structure is disposed over epitaxial layer 108. The interconnect structure may include a plurality of conductive features configured to interconnect the high voltage semiconductor device 100 with additional devices, components, voltage sources, etc. to ensure proper function of the high voltage semiconductor device 100. The interconnect structure includes various conductive and dielectric layers. The conductive layers are configured to form vertical interconnect features, such as vertical interconnect structures (e.g., vias 142, 148) and/or horizontal interconnect structures (e.g., conductive lines 146, 150). Each horizontal interconnect feature disposed in a dielectric layer may be referred to as a "metal layer," and two different metal layers may be electrically coupled by one or more vertical interconnect structures. Various conductive layers are embedded in dielectric layers, such as

dielectric layers

140 and 144. As shown in fig. 1B, source region 130 and doped region 138 each connect via 142 and line 146, and drain region 122 connects via 142, line 146, via 148, line 150. Each conductive layer (e.g., vias 142, 148 and wires 146, 150) may comprise copper (Cu), tungsten (W), ruthenium (Ru), cobalt (Co), aluminum (Al), other suitable metals, or combinations thereof, and may further comprise a barrier layer comprising titanium (Ti), tantalum (Ta), titanium nitride (TiN), and/or tantalum nitride (TaN) in some embodiments. The

dielectric layers

140 and 144 may be referred to as interlayer dielectric (ILD) layers. In some embodiments,

dielectric layers

140 and 144 may comprise silicon oxide, Tetraethoxysilane (TEOS), undoped silicate glass or doped silicon oxide, such as borophosphosilicate glass (BPSG), Fused Silica Glass (FSG), phosphosilicate glass (PSG), boron doped silica glass (BSG), other suitable dielectric materials, or combinations thereof. In some embodiments,

dielectric layers

140 and 144 may be formed using CVD, Flow CVD (FCVD), or spin-on-glass.

As described above, in the embodiment of the present invention, the high voltage well 114 is used as an isolation region at the outer periphery of the high voltage semiconductor apparatus 100 so that the high voltage semiconductor apparatus does not affect adjacent devices during operation. In order that the high voltage semiconductor apparatus 100 may operate in a larger operation voltage without affecting neighboring devices, it is necessary to increase a lateral breakdown voltage (lateral breakdown voltage) of the high voltage semiconductor apparatus 100. In an embodiment of the present invention, doped region 136 is disposed in high voltage well 114 to further increase the lateral breakdown voltage. As described above, the doping concentration of doped region 136 is greater than the doping concentration of high voltage well 114. As a result, since the dopant of the doped region 136 may partially diffuse into the high-voltage well 114, the doping concentration of the high-voltage well 114 is increased, and thus the depletion region is reduced to have a larger lateral breakdown voltage. Notably, doped region 136 is disposed in an upper portion of high voltage well 114. Specifically, the ratio of the depth H1 of doped region 136 to the depth H2 of high voltage well 114 is in the range of about 0.006 to about 0.01. If the depth H1 of doped region 136 is too small, the lateral breakdown voltage cannot be effectively increased. If the depth of the doped region 136, H1, is too great, this will result in a reduced Junction Breakdown voltage (Junction Breakdown) of the device (which will result in Breakdown of the high voltage well 114 to the high voltage well 116).

Fig. 2 is a graph comparing breakdown voltages of the high voltage semiconductor device 100 according to the embodiment of the present invention and a known high voltage semiconductor device. The peripheral high voltage well of the high voltage semiconductor device 100, such as high voltage well 114, has no doped region, whereas the peripheral high voltage well of the known high voltage semiconductor device has a doped region, such as doped region 136. As shown in fig. 2, in the drain current-drain voltage characteristic diagram (Id-Vd characteristic diagram), curves 202 and 204 individually represent the Id-Vd characteristics of the known high-voltage semiconductor device and the high-voltage semiconductor device 100. When the drain voltage of the known high voltage semiconductor device increases to about 90V, lateral breakdown occurs and the drain current rises sharply. In contrast, since the peripheral high voltage well of the high voltage semiconductor device 100 has a doped region, lateral breakdown occurs when the drain voltage increases to about 167V and the drain current rises sharply. Therefore, the doping region is arranged on the peripheral high-voltage well of the high-voltage semiconductor device, so that the transverse breakdown voltage can be effectively increased.

Referring again to fig. 1A and 1B, doped region 104 is disposed below

high voltage wells

112 and 114. It is noted that in the embodiment of the present invention, the doped region 104 does not extend below the high voltage well 110. Specifically, the boundary of doped region 104 (i.e., the inner boundary of doped region 104 as shown in fig. 1A) is a predetermined distance D1 from the boundary of high-voltage well 110 (i.e., the outer boundary of high-voltage well 110 as shown in fig. 1A) to prevent leakage from drain region 122 to doped region 104. In addition, if the distance D1 is too large, the doped region 104 may not effectively prevent vertical leakage of the high voltage well 112 to the substrate 102.

Fig. 3 is a cross-sectional view of another embodiment of the high voltage semiconductor device 100, wherein a via 152 and a conductive line 154 are additionally formed above the doped region 136. In this case, doped region 136, high voltage well 114, doped region 104, drain region 122 may constitute circuit 302. As described above, the boundary of doped region 104 is a distance D1 from the boundary of high voltage well 110, which constitutes resistor 304 in circuit 302. In this embodiment, the resistance of the resistor 304 in the measuring circuit 302 can be used to monitor whether the distance D1 meets the design. Specifically, a series of processes for forming the high voltage semiconductor device 100 may affect the profile of the doped region 104. For example, the processing of the high voltage semiconductor device 100 may cause the doped region 104 to extend below the extended high voltage well 110 (i.e., the distance D1 is reduced), and thus result in a reduction in the resistance value of the resistor 304 in the circuit 302. As a result, leakage from the drain region 122 to the doped region 104 occurs in the resulting high-voltage semiconductor device 100 during operation. Therefore, through the resistance value of the resistor 304 in the measurement circuit 302, it can be determined whether the high voltage semiconductor device 100 meets the design requirements or has defects.

Embodiments of the invention provide a number of advantages over the prior art, and it is to be understood that other embodiments may provide different advantages, all of which need not be discussed herein, and no specific advantages are provided by all embodiments.

The foregoing outlines features of many embodiments so that those skilled in the art may better understand the present disclosure in various aspects. It should be appreciated by those skilled in the art that the present invention may be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention. Various changes, substitutions, and alterations can be made hereto without departing from the spirit and scope of the invention.

Claims

1. A high voltage semiconductor device, comprising:

a substrate having a first conductivity type;

a first high voltage well disposed above the substrate and having a second conductivity type opposite to the first conductivity type;

a second high voltage well disposed adjacent to and in contact with the first high voltage well and having the first conductivity type;

a third high voltage well disposed adjacent to and in contact with the first high voltage well and having the second conductivity type;

a drain region disposed in the first high-voltage well;

A source region disposed in the second high voltage well;

a gate structure disposed between the source region and the drain region; and

and a doped region disposed in the third high-voltage well and having the second conductivity type.

2. The high voltage semiconductor device of claim 1, further comprising:

and a buried layer disposed under the second high voltage well and the third high voltage well and having the second conductive type.

3. The high voltage semiconductor device of claim 2, wherein a boundary of said buried layer is spaced apart from a boundary between said first high voltage well and said second high voltage well by a predetermined distance.

4. The high voltage semiconductor device of claim 2, further comprising:

a dielectric layer disposed above the substrate;

a metal contact disposed in the dielectric layer and contacting the doped region; and

a metal layer disposed above the dielectric layer and contacting the metal contact.

5. The high voltage semiconductor device of claim 2, wherein a ratio of a depth of the doped region to a depth of the third high voltage well is in a range of 0.006 to 0.01.

6. A high voltage semiconductor device, comprising:

a substrate;

a high voltage well disposed above the substrate and having a first conductive type dopant;

a first ring-shaped well surrounding and contacting the high-voltage well and having a second conductive type dopant opposite to the first conductive type dopant;

a second ring-shaped well which is arranged around the first ring-shaped well and has the first conductive type dopant;

a drain region disposed in the high voltage well;

a ring-shaped gate structure disposed above the high-voltage well and surrounding the drain region;

an annular source region disposed in the first annular well and surrounding the annular gate structure; and

and an annular doped region disposed in the second annular well and having the first conductive type dopant.

7. The high voltage semiconductor device of claim 6, further comprising:

an annular buried layer disposed under the first and second ring wells and having the first conductive type dopant.

8. The high voltage semiconductor device of claim 7, wherein an inner boundary of said annular buried layer is spaced a predetermined distance from an outer boundary of said high voltage well.

9. The high voltage semiconductor device of claim 7, further comprising:

a dielectric layer disposed above the substrate;

a metal contact disposed in the dielectric layer and contacting the annular doped region; and

10. The high voltage semiconductor device of claim 6, wherein a ratio of a depth of the ring-shaped doped region to a depth of the second ring-shaped well is in a range of 0.006 to 0.01.