CN114678046B

CN114678046B - Drive circuit and memory device

Info

Publication number: CN114678046B
Application number: CN202210583912.0A
Authority: CN
Inventors: 戴佼容
Original assignee: Xinyaohui Technology Co ltd
Current assignee: Xinyaohui Technology Co ltd
Priority date: 2022-05-27
Filing date: 2022-05-27
Publication date: 2022-10-14
Anticipated expiration: 2042-05-27
Also published as: CN114678046A

Abstract

The application provides a driving circuit and a storage device, wherein the driving circuit comprises a plurality of pull-up sub-circuits, an output end and at least one enhancement sub-circuit, one end of each pull-up sub-circuit is used for receiving a voltage signal, the other end of each pull-up sub-circuit is electrically connected with the output end, and each pull-up sub-circuit is used for generating a first driving current according to the voltage signal and transmitting the first driving current to the output end; the enhancer circuit is connected in parallel with the pull-up sub-circuit and used for generating a second driving current according to the voltage signal and transmitting the second driving current to the output end, and the output end is used for outputting a pull-up electric signal according to the first driving current and the second driving current. The second driving current generated by the enhancer circuit increases the pull-up driving current when the pull-up signal is output by the output terminal, so that the waveform rise time of the output terminal is shortened.

Description

Drive circuit and memory device

Technical Field

The present disclosure relates to circuit control technologies, and particularly to a driving circuit and a storage device.

Background

With the development of the information age, it is more and more important to be able to conveniently store and transfer information, so that various storage devices are on the market.

The drive circuit of the storage device in the prior art can ensure that the storage device has ideal waveform rise time when the storage device works in a 1.8V voltage mode, and the storage device cannot be well driven to store due to long waveform rise time when the storage device works in a 3.3V voltage mode.

Disclosure of Invention

The application discloses drive circuit can solve the technical problem that when different voltage modes work, the output waveform rise time is long.

In a first aspect, the present application provides a driving circuit, which includes a plurality of pull-up sub-circuits, an output terminal, and at least one enhancer circuit, where one end of the pull-up sub-circuit is configured to receive a voltage signal, and the other end of the pull-up sub-circuit is electrically connected to the output terminal, and the pull-up sub-circuit is configured to generate a first driving current according to the voltage signal and transmit the first driving current to the output terminal; the enhancer circuit is connected in parallel with the pull-up sub-circuit and used for generating a second driving current according to the voltage signal and transmitting the second driving current to the output end, and the output end is used for outputting a pull-up electric signal according to the first driving current and the second driving current.

The second driving current generated by the enhancer circuit increases the pull-up driving current when the pull-up signal is output by the output terminal, so that the waveform rise time of the output terminal is shortened.

Optionally, the pull-up sub-circuit includes a first transistor, a second transistor and a third transistor that are arranged in series, a source of the first transistor is used for receiving the voltage signal, a drain of the first transistor is electrically connected to a source of the second transistor, and a drain of the third transistor is electrically connected to the output terminal; the grid electrode of the first transistor is used for receiving a first control signal, and the first control signal is used for controlling the on-off of the first transistor; the drain electrode of the second transistor is electrically connected with the source electrode of the third transistor, the grid electrode of the second transistor is used for receiving a second control signal, and the second control signal is used for controlling the on-off of the second transistor; the grid electrode of the third transistor is used for receiving a third control signal, and the third control signal is used for controlling the on-off of the third transistor.

Optionally, the enhancer circuit includes a fourth transistor, a fifth transistor and a sixth transistor arranged in series, a source of the fourth transistor is configured to receive the voltage signal, a drain of the fourth transistor is electrically connected to a source of the fifth transistor, and a drain of the sixth transistor is electrically connected to the output terminal; the grid electrode of the fourth transistor is used for receiving the first control signal, and the first control signal is used for controlling the on-off of the fourth transistor; the drain electrode of the fifth transistor is electrically connected with the source electrode of the sixth transistor, the gate electrode of the fifth transistor is used for receiving the fourth control signal, and the fourth control signal is used for controlling the on-off of the fifth transistor; the grid electrode of the sixth transistor is used for receiving the third control signal, and the third control signal is used for controlling the on-off of the sixth transistor.

Optionally, the voltage signal includes a first voltage sub-signal and a second voltage sub-signal, a voltage value of the first voltage sub-signal is greater than a voltage value of the second voltage sub-signal, and when the first voltage sub-signal is transmitted to the pull-up sub-circuit and the enhancer circuit, a voltage value of the second control signal transmitted to the pull-up sub-circuit and a voltage value of the fourth control signal transmitted to the enhancer circuit are equal to a voltage value of the second voltage sub-signal; when the second voltage sub-signal is transmitted to the pull-up sub-circuit and the enhancer circuit, a voltage value of the fourth control signal transmitted to the enhancer circuit is equal to a voltage value of the second voltage sub-signal, and the voltage value of the second control signal transmitted to the pull-up sub-circuit is smaller than the voltage value of the second voltage sub-signal.

Optionally, the enhancer circuit includes a fourth transistor and a fifth transistor arranged in series, a source of the fourth transistor is used for receiving the voltage signal, and a drain of the fifth transistor is electrically connected to a source of one of the third transistors; the grid electrode of the fourth transistor is used for receiving the first control signal, and the first control signal is used for controlling the on-off of the fourth transistor; the grid electrode of the fifth transistor is used for receiving the fourth control signal, and the fourth control signal is used for controlling the on-off of the fifth transistor.

Optionally, the number of the enhancement sub-circuits is the same as that of the pull-up sub-circuits, and the enhancement sub-circuits are connected in parallel to the pull-up sub-circuits in a one-to-one correspondence.

Optionally, the driving circuit further includes a plurality of pull-down sub-circuits, one end of each of the pull-down sub-circuits is configured to receive a ground signal, the other end of each of the pull-down sub-circuits is electrically connected to the output end, and the pull-down sub-circuits are configured to drive the output end to output a pull-down signal according to the ground signal.

Optionally, the pull-up sub-circuit and the enhancer circuit include at least one PMOS, and the pull-down sub-circuit includes at least one NMOS.

Optionally, the pull-down sub-circuit includes a seventh transistor, an eighth transistor, and a ninth transistor that are connected in series, a source of the seventh transistor is configured to receive the ground signal, a drain of the seventh transistor is electrically connected to the source of the eighth transistor, and a drain of the ninth transistor is electrically connected to the output terminal; the grid electrode of the seventh transistor is used for receiving a fifth control signal, and the fifth control signal is used for controlling the on-off of the seventh transistor; the drain of the eighth transistor is electrically connected with the source of the ninth transistor, the gate of the eighth transistor is used for receiving a sixth control signal, and the sixth control signal is used for controlling the on-off of the eighth transistor; the grid electrode of the ninth transistor is used for receiving a seventh control signal, and the seventh control signal is used for controlling the on-off of the ninth transistor.

In a second aspect, the present application further provides a storage device, which includes a memory and the driving circuit according to the first aspect, wherein the memory is used for storing the electrical signal output by the output terminal.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for a person skilled in the art to obtain other drawings based on the drawings without any inventive exercise.

Fig. 1 is a schematic diagram of a driving circuit framework according to an embodiment of the present disclosure.

Fig. 2 is a schematic diagram of a driving circuit according to an embodiment of the present disclosure.

Fig. 3 is a schematic diagram of a possible waveform of an output terminal in the prior art.

Fig. 4 is a schematic diagram of waveforms at an output end according to an embodiment of the present application.

Fig. 5 is a schematic diagram of a driving circuit according to another embodiment of the present disclosure.

Fig. 6 is a schematic cross-sectional view of a PMOS device according to an embodiment of the present disclosure.

Fig. 7 is a schematic cross-sectional view of an NMOS provided in an embodiment of the present application.

Fig. 8 is a schematic diagram of a storage device frame according to an embodiment of the present disclosure.

The reference numbers indicate: the driving circuit-1, the pull-up sub-circuit-11, the first transistor-T1, the second transistor-T2, the third transistor-T3, the output terminal-PAD, the enhancer circuit-12, the fourth transistor-T4, the fifth transistor-T5, the sixth transistor-T6, the pull-down sub-circuit-13, the seventh transistor-T7, the eighth transistor-T8, the ninth transistor-T9, the storage device-2, the memory-21, the gate-G, the source-s, the drain-d, the voltage signal-VDD, the ground signal-VSS, the first control signal-G1, the second control signal-G2, the third control signal-G3, the fourth control signal-G4, the fifth control signal-G5, the sixth control signal-G6, and the seventh control signal-G7.

Detailed Description

The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.

Referring to fig. 1, fig. 1 is a schematic diagram of a driving circuit frame according to an embodiment of the present disclosure. The driving circuit 1 comprises a plurality of pull-up sub-circuits 11, an output terminal PAD and at least one enhancement sub-circuit 12, wherein one end of each pull-up sub-circuit 11 is used for receiving a voltage signal VDD, the other end of each pull-up sub-circuit is electrically connected with the output terminal PAD, and the pull-up sub-circuits 11 are used for generating a first driving current according to the voltage signal VDD and transmitting the first driving current to the output terminal PAD; the enhancer circuit 12 is connected in parallel to the pull-up sub-circuit 11, and is configured to generate a second driving current according to the voltage signal VDD, and transmit the second driving current to the output terminal PAD, where the output terminal PAD is configured to output a pull-up electrical signal according to the first driving current and the second driving current.

It should be noted that the output PAD is usually connected to an input interface inside the chip, or serves as an output of the chip. When the pull-up sub-circuit 11 is turned on, the voltage signal VDD is applied to the pull-up sub-circuit 11, and the generated pull-up driving current is transmitted to the output terminal PAD, so that the waveform of the output terminal PAD rises. Generally, the driving circuit further includes a pull-down sub-circuit 13 for generating a pull-down driving current to be transmitted to the output terminal PAD, so that the waveform of the output terminal PAD is decreased, and finally the output terminal PAD outputs a complete pulse signal waveform. The duty ratio is the proportion of the waveform rising time relative to the total waveform time in a pulse signal period cycle, and the duty ratio is used for measuring the quality of the pulse signal waveform output by the output end PAD. It can be understood that the larger the duty cycle, the better the pulse signal waveform output by the output terminal PAD.

Specifically, the enhancer circuit 12 is connected in parallel to the pull-up sub-circuit 11, that is, one end of the enhancer circuit 12 is used for receiving the voltage signal VDD, and the other end is electrically connected to the output PAD. When the enhancer circuit 12 is turned on, the voltage signal VDD is applied to the enhancer circuit 12, so that an additional pull-up driving current can be generated and flows to the output PAD, thereby increasing the pull-up driving current of the output PAD.

It is understood that, in the present embodiment, the second driving current generated by the enhancer circuit 12 increases the pull-up driving current when the pull-up signal is output from the output terminal PAD, so that the waveform rise time of the output terminal PAD is shortened.

In one possible implementation, please refer to fig. 2, and fig. 2 is a schematic diagram of a driving circuit according to an embodiment of the present disclosure. The pull-up sub-circuit 11 includes a first transistor T1, a second transistor T2 and a third transistor T3, which are serially connected, a source s of the first transistor T1 is used for receiving the voltage signal VDD, a drain d of the first transistor T1 is electrically connected to the source s of the second transistor T2, and a drain d of the third transistor T3 is electrically connected to the output terminal PAD; the grid G of the first transistor T1 is used for receiving a first control signal G1, and the first control signal G1 is used for controlling the on-off of the first transistor T1; the drain d of the second transistor T2 is electrically connected to the source s of the third transistor T3, the gate G of the second transistor T2 is used for receiving a second control signal G2, and the second control signal G2 is used for controlling the on/off of the second transistor T2; the gate G of the third transistor T3 is configured to receive a third control signal G3, and the third control signal G3 is configured to control on/off of the third transistor T3.

Specifically, the first transistor T1, the second transistor T2, and the third transistor T3 each include a gate G, a source s, and a drain d, and since a P-type Metal Oxide Semiconductor (NMOS) is usually used to control the output terminal PAD of the driving circuit 1 to output a pull-up signal, and an NMOS controls the output terminal PAD of the driving circuit 1 to output a pull-down signal, that is, the first transistor T1, the second transistor T2, and the third transistor T3 are PMOS, when a voltage between the gate G and the source s is less than or equal to a threshold voltage of the transistor, that is, by controlling voltage values of the first control signal G1, the second control signal G2, and the third control signal G3, the transistors are turned on, that is, by controlling voltages between the gate G and the source s of the first transistor T1, the second transistor T2, and the third transistor T3, on/off of the first transistor T1, the second transistor T2, and the third transistor T3 is controlled.

It can be understood that, in this embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 are connected in series to perform a voltage dividing and current limiting function, so as to prevent the electronic component or the integrated circuit in the circuit from being damaged due to an excessively large voltage value of the voltage signal VDD. In other possible embodiments, the number of transistors included in the pull-up sub-circuit 11 may also be other numbers according to the voltage value of the voltage signal VDD, which is not limited in this application.

In one possible implementation, referring again to fig. 2, the enhancer circuit 12 includes a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6 arranged in series, a source s of the fourth transistor T4 is used for receiving the voltage signal VDD, a drain d of the fourth transistor T4 is electrically connected to the source s of the fifth transistor T5, and a drain d of the sixth transistor T6 is electrically connected to the output terminal PAD; the gate G of the fourth transistor T4 is configured to receive the first control signal G1, and the first control signal G1 is configured to control on/off of the fourth transistor T4; the drain d of the fifth transistor T5 is electrically connected to the source s of the sixth transistor T6, the gate G of the fifth transistor T5 is configured to receive the fourth control signal G4, and the fourth control signal G4 is configured to control on/off of the fifth transistor T5; the gate G of the sixth transistor T6 is configured to receive the third control signal G3, and the third control signal G3 is configured to control on/off of the sixth transistor T6.

Similarly, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 all include a gate g, a source s, and a drain d, and the working principle of the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 refers to the above description, and is not described herein again.

It should be noted that the driving circuit 1 has two different operation modes, i.e. a 1.8V operation mode or a 3.3V operation mode. In the prior art, the waveform of the PAD at the output terminal of the driving circuit 1 in the 1.8V operating mode is ideal, but is poor in the 3.3V operating mode.

In this embodiment, the enhancer circuit 12 is connected in parallel with the pull-up sub-circuit 11, and the first control signal G1, the second control signal G2, the third control signal G3, or the fourth control signal G4 transmitted to the enhancer circuit 12 and the pull-up sub-circuit 11 are controlled to have different voltage values according to the different voltage values of the voltage signal VDD, so that the pull-up sub-circuit 11 and the enhancer circuit 12 can be controlled to be turned on or off respectively in different voltage value operating modes, and the source of the voltage signal VDD can be directly supplied from an external 3.3V or 1.8V power supply. The arrangement mode avoids the need of generating intermediate levels by means of an internal circuit to realize different voltage working modes, thereby reducing the complexity of the circuit and the cost of additional electronic components. It is understood that, in other possible embodiments, the voltage value of the voltage signal VDD may also be other values, which is not limited in this application.

Next, the present application will be exemplified with the driving circuit 1 in a 3.3V operation mode. When the driving circuit 1 is in a 3.3V operating mode, the voltage value of the voltage signal VDD needs to be 2.7V at the lowest, in other words, the voltage value of the source s of the first transistor T1 or the fourth transistor T4 needs to be 2.7V at the lowest, and meanwhile, the maximum voltage value of the gate g of the transistor is usually set to 1.98V in an emulation manner in consideration of the deviation of an external power supply and the influence of the chip interior and a packaging part. Since the voltage between the gate g and the source s of the PMOS is small compared to the voltage between the gate g and the source s of the NMOS, the current calculation formula of the transistor is as follows:

wherein, the first and the second end of the pipe are connected with each other,

is a current value of the driving current,

in order to be the rate of electron transfer,

is the capacitance of the gate g oxide layer per unit area,

is the ratio of the width to the length of the gate g oxide layer,

is the value of the voltage between the gate g and the source s of the transistor,

is the value of the threshold voltage of the transistor,

is the value of the voltage between the drain d and the source s of the transistor.

Referring to fig. 3 together, fig. 3 is a schematic diagram of a possible waveform of an output terminal in the prior art. According to the current calculation formula of the transistor, the driving current of the output terminal PAD when outputting the pull-up signal is smaller than the driving current when outputting the pull-down signal, as shown in fig. 3, so that the waveform rise time of the output terminal PAD is slower than the fall time, that is, the duty ratio of the output terminal PAD is poorer, and the application requirement of the peripheral electronic component or the integrated circuit cannot be met.

It is to be understood that, in this embodiment, please refer to fig. 4 together, and fig. 4 is a schematic waveform diagram of an output terminal according to an embodiment of the present application. The enhancer circuit 12 is disposed in parallel with the pull-up sub-circuit 11, and the enhancer circuit 12 includes the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6, that is, when the driving circuit 1 is in the 3.3V operating mode, the number of pull-up transistors is increased, so that the pull-up driving current of the output terminal PAD is increased, as shown in fig. 4, the waveform rise time of the output terminal PAD is shortened, and a better duty ratio is obtained.

It should be noted that the driving circuit 1 has different operating ranges, and the number of the pull-up sub-circuits 11 corresponds to the number of the operating ranges of the driving circuit 1. It can be understood that when the operating positions of the driving circuit 1 are different, the output waveform of the output PAD is also different.

In the present embodiment, by controlling the output of the first control signal G1, different drive positions of the drive circuit 1 can be realized. Specifically, please refer to fig. 2 again, and be combined with the following table 1, wherein Drive represents different driving gears of the driving circuit 1, which are realized under different outputs of the first control signal G1; it should be noted that, when the first transistor T1 and the fourth transistor T4 in fig. 2 are sorted by columns, 1-5 column numbers sorted from left to right can be obtained, as shown in table 1 below, the numbers in parentheses represent the conducting states of the first transistor T1 or the fourth transistor T4 with the same numbers in fig. 2; "√" represents that the first transistor T1 or the fourth transistor T4 is in the ON state, and "X" represents that the first transistor T1 or the fourth transistor T4 is in the OFF state.

TABLE 1 ON-OFF STATE TABLE OF THE FIRST TRANSISTOR T1 AND THE FOUR TRANSISTOR T4 AT DIFFERENT DRIVING GEAR

Drive	T1（1）	T4（2）	T1（3）	T1（4）	T1（5）
						000	√	√	X	X	X
001	√	√	√	X	X
						010	√	√	X	√	X
011	√	√	√	√	X
						100	√	√	X	X	√
101	√	√	√	X	√
						110	√	√	X	√	√
111	√	√	√	√	√

As can be seen from the on/off states of the first transistor T1 in table 1, in different driving ranges, a certain column of the first transistor T1 is always in an on state, and in this embodiment, when the first transistor T1 is turned on, the second transistor T2 and the third transistor T3 are always in an on state, that is, the pull-up sub-circuit 11 in the column is always turned on. Specifically, the enhancer circuit 12 is connected in parallel to the pull-up sub-circuit 11 where the first transistor T1 that is always turned on is located, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are also always turned on in different driving gears, that is, the enhancer circuit 12 is always turned on to correspond to the pull-up sub-circuit 11 that is always turned on.

It will be appreciated that in this embodiment, the enhancer circuit 12 increases the pull-up drive current to a different extent for different drive positions, so that the rise time of the waveform at the output PAD is shortened to a different extent for each drive position.

In a possible embodiment, the voltage signal VDD comprises a first voltage sub-signal and a second voltage sub-signal, the voltage value of the first voltage sub-signal is greater than the voltage value of the second voltage sub-signal, and when the first voltage sub-signal is transmitted to the pull-up sub-circuit 11 and the enhancer circuit 12, the voltage values of the second control signal G2 transmitted to the pull-up sub-circuit 11 and the fourth control signal G4 transmitted to the enhancer circuit 12 are equal to the voltage value of the second voltage sub-signal; when the second voltage sub-signal is transmitted to the pull-up sub-circuit 11 and the enhancer circuit 12, the voltage value of the fourth control signal G4 transmitted to the enhancer circuit 12 is equal to the voltage value of the second voltage sub-signal, and the voltage value of the second control signal G2 transmitted to the pull-up sub-circuit 11 is smaller than the voltage value of the second voltage sub-signal.

Specifically, the voltage value of the first voltage sub-signal is 3.3V, and the voltage value of the second voltage sub-signal is 1.8V. When the first voltage sub-signal is transmitted to the pull-up sub-circuit 11 and the enhancer circuit 12, the voltage value of the second control signal G2 transmitted to the pull-up sub-circuit 11 is 1.8V, and the voltage value of the fourth control signal G4 transmitted to the enhancer circuit 12 is also 1.8V, it can be understood that, at this time, the voltage value between the gate G and the source s of the second transistor T2 and the fifth transistor T5 is smaller than the threshold voltage, and is in the on state; when the second voltage sub-signal is transmitted to the pull-up sub-circuit 11 and the enhancer circuit 12, the voltage value of the second control signal G2 transmitted to the pull-up sub-circuit 11 is 0V, and the voltage value of the fourth control signal G4 transmitted to the enhancer circuit 12 is 1.8V, it can be understood that, at this time, the voltage value between the gate G and the source s of the second transistor T2 is smaller than the threshold voltage and is in the on state, and the voltage value between the gate G and the source s of the fifth transistor T5 is greater than the threshold voltage and is in the off state.

That is, when the driving circuit 1 is in the 1.8V voltage operation mode, the enhancer circuit 12 does not affect the circuit performance. It can be understood that, in the present embodiment, even if the enhancer circuit 12 is provided, the duty ratio of the output PAD in other different voltage operation modes is not affected.

In one possible implementation, please refer to fig. 5, in which fig. 5 is a schematic diagram of a driving circuit according to another implementation of the present application. The enhancer circuit 12 includes a fourth transistor T4 and a fifth transistor T5 connected in series, a source s of the fourth transistor T4 is used for receiving the voltage signal VDD, and a drain d of the fifth transistor T5 is electrically connected to a source s of one of the third transistors T3; the gate G of the fourth transistor T4 is configured to receive the first control signal G1, and the first control signal G1 is configured to control on/off of the fourth transistor T4; the gate G of the fifth transistor T5 is configured to receive the fourth control signal G4, and the fourth control signal G4 is configured to control on/off of the fifth transistor T5.

Specifically, each of the enhancer circuits 12 in this embodiment reduces the sixth transistor T6 relative to the previous embodiment. Since the gate g, the source s and the drain d of the third transistor T3 and the sixth transistor T6 are used for receiving the same potential, the additional driving current generated by the enhancer circuit 12 can be directly merged at the source s end of the third transistor T3, so that the sixth transistor T6 is reduced, and the material cost is saved.

In a possible embodiment, the number of the enhancer circuits 12 is the same as the number of the pull-up sub-circuits 11, and the enhancer circuits 12 are connected in parallel to the pull-up sub-circuits 11 in a one-to-one correspondence.

In the present embodiment, the enhancer circuits 12 are connected in parallel to the pull-up sub-circuits 11 in a one-to-one correspondence, that is, the pull-up sub-circuits 11 are connected in parallel to the enhancer circuits 12 in each column according to the different driving current of each driving position of the driving circuit 1, so that the driving current of the output PAD in each driving position is relatively unchanged, that is, the driving current of the output PAD in each driving position is increased to the same extent. Specifically, please refer to fig. 5 again in conjunction with table 2 below. It should be noted that, the first transistor T1 and the fourth transistor T4 in fig. 5 are sorted by columns, and 1-8 column numbers sorted from left to right can be obtained, as shown in table 2 below, where the numbers in parentheses represent the conducting states of the first transistor T1 or the fourth transistor T4 with the same numbers in fig. 5.

Table 2 on-off state table of the first transistor T1 and the fourth transistor T4 in different driving gears

Drive

T1（1）

T4（2）

T1（3）

T4（4）

T1（5）

T4（6）

T1（7）

T4（8）

000

√

X

001

√

X

010

√

X

√

X

011

√

X

100

√

X

√

101

√

X

√

110

√

X

√

111

√

Specifically, please refer to the above description for the detailed meanings of the letters, symbols, etc. in table 2, which are not repeated herein. It will be appreciated that in this embodiment, for different drive positions, there is a corresponding boost of the drive current by the boost circuit 12, so that the rise time of the waveform at the output PAD is reduced to the same extent for each drive position.

In one possible implementation, referring to fig. 1 again, the driving circuit 1 further includes a plurality of pull-down sub-circuits 13, one end of each pull-down sub-circuit 13 is configured to receive a ground signal VSS, the other end of each pull-down sub-circuit is electrically connected to the output terminal PAD, and the pull-down sub-circuits 13 are configured to drive the output terminal PAD to output a pull-down electrical signal according to the ground signal VSS.

Specifically, the pull-up sub-circuit 11 controls the output of the output PAD to output a pull-up signal, so that the waveform output by the output PAD rises; the pull-down sub-circuit 13 controls the output of the output terminal PAD to output a pull-down electrical signal, so that the waveform output by the output terminal PAD is lowered, and the waveform of the output terminal PAD is periodically output.

In this embodiment, the number of the pull-down sub-circuits 13 is equal to the number of the pull-up sub-circuits 11, and the pull-down sub-circuits are arranged in a one-to-one correspondence, so that the waveform output by the output terminal PAD can fall to be level with the initial position after rising, and the waveform of the output terminal PAD is periodically output.

In one possible implementation, please refer to fig. 6 and 7 together, in which fig. 6 is a schematic cross-sectional view of a PMOS according to an embodiment of the present application; fig. 7 is a schematic cross-sectional view of an NMOS provided in an embodiment of the present application. The pull-up sub-circuit 11 and the enhancer circuit 12 comprise at least one PMOS, and the pull-down sub-circuit 13 comprises at least one NMOS.

Specifically, as shown in fig. 6, the PMOS includes a gate g and an N-type semiconductor covering two P-type semiconductors, where one P-type semiconductor is a source s and the other is a drain d. The gate g is a metal electrode, and an insulating layer J is further disposed between the gate g and the source s and the drain d. As trivalent element impurities are doped in the P-type semiconductor material, most carriers in the P-type semiconductor are holes, and the holes are positively charged. When the transistor is a PMOS, a low potential is loaded on the grid g, and the two P-type semiconductors form a channel to conduct the source s and the drain d.

As shown in fig. 7, the NMOS is formed by a gate g and a P-type semiconductor encapsulating two N-type semiconductors, one of which is a source s and the other is a drain d. The gate g is a metal electrode, and an insulating layer J is further disposed between the gate g and the source s and the drain d. Since pentavalent element impurities are doped in the N-type semiconductor material, most carriers in the N-type semiconductor are electrons, and the electrons are negatively charged. When the transistor is an NMOS, a high voltage is applied to the gate g, and the two N-type semiconductors form a channel to turn on the source s and the drain d.

It can be understood that, due to the characteristics of the particles, PMOS has a fast turn-on speed and low power consumption relative to NMOS, and therefore PMOS is used to control the output terminal PAD of the driving circuit 1 to output a pull-up electric signal, and NMOS is used to control the output terminal PAD of the driving circuit 1 to output a pull-down electric signal.

In one possible embodiment, please refer to fig. 2 or fig. 5 again. The pull-down sub-circuit 13 includes a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9, which are serially connected, a source s of the seventh transistor T7 is configured to receive the ground signal VSS, a drain d of the seventh transistor T7 is electrically connected to the source s of the eighth transistor T8, and a drain d of the ninth transistor T9 is electrically connected to the output terminal PAD; a gate G of the seventh transistor T7 is configured to receive the fifth control signal G5, and the fifth control signal G5 is configured to control on/off of the seventh transistor T7; the drain d of the eighth transistor T8 is electrically connected to the source s of the ninth transistor T9, the gate G of the eighth transistor T8 is configured to receive the sixth control signal G6, and the sixth control signal G6 is configured to control on/off of the eighth transistor T8; the gate G of the ninth transistor T9 is configured to receive the seventh control signal G7, and the seventh control signal G7 is configured to control on/off of the ninth transistor T9.

Similarly, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 each include a gate g, a source s and a drain d. Specifically, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 also function to divide voltage and limit current. In other possible embodiments, the number of transistors included in the pull-down sub-circuit 13 may also be other numbers, which is not limited in this application. The working principles of the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are similar to the working principles of the third transistor T3, the second transistor T2, and the first transistor T1, and are not repeated herein.

Note that, since the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are NMOS, the transistors are turned on when the voltage between the gate g and the source s is equal to or higher than the threshold voltage of the transistors, which is contrary to PMOS.

Fig. 8 is a schematic view of a storage device 2 according to an embodiment of the present application, and fig. 8 is a schematic view of a storage device frame according to an embodiment of the present application. The storage device 2 comprises a memory 21 and the driving circuit 1 as described above, the memory 21 is used for storing the electric signal outputted from the output terminal PAD.

Claims

1. A drive circuit is characterized by comprising a plurality of pull-up sub-circuits, an output end and at least one enhancement sub-circuit, wherein one end of each pull-up sub-circuit is used for receiving a voltage signal, the other end of each pull-up sub-circuit is electrically connected with the output end, and each pull-up sub-circuit is used for generating a first drive current according to the voltage signal and transmitting the first drive current to the output end; the enhancer circuit is connected in parallel with the pull-up sub-circuit and used for generating a second driving current according to the voltage signal and transmitting the second driving current to the output end, and the output end is used for outputting a pull-up electric signal according to the first driving current and the second driving current; the pull-up sub-circuit comprises a first transistor, a second transistor and a third transistor which are arranged in series, wherein the source electrode of the first transistor is used for receiving the voltage signal, the drain electrode of the first transistor is electrically connected with the source electrode of the second transistor, and the drain electrode of the third transistor is electrically connected with the output end; the grid electrode of the first transistor is used for receiving a first control signal, and the first control signal is used for controlling the on-off of the first transistor; the drain electrode of the second transistor is electrically connected with the source electrode of the third transistor, the grid electrode of the second transistor is used for receiving a second control signal, and the second control signal is used for controlling the on-off of the second transistor; the grid electrode of the third transistor is used for receiving a third control signal, and the third control signal is used for controlling the on-off of the third transistor;

the enhancer circuit comprises a fourth transistor and a fifth transistor which are arranged in series, wherein the source electrode of the fourth transistor is used for receiving the voltage signal, and the drain electrode of the fifth transistor is electrically connected with the source electrode of one of the third transistors; the grid electrode of the fourth transistor is used for receiving the first control signal, and the first control signal is used for controlling the on-off of the fourth transistor; the grid electrode of the fifth transistor is used for receiving a fourth control signal, and the fourth control signal is used for controlling the on-off of the fifth transistor; alternatively, the first and second liquid crystal display panels may be,

the enhancer circuit comprises a fourth transistor, a fifth transistor and a sixth transistor which are arranged in series, wherein the source electrode of the fourth transistor is used for receiving the voltage signal, the drain electrode of the fourth transistor is electrically connected with the source electrode of the fifth transistor, and the drain electrode of the sixth transistor is electrically connected with the output end; the grid electrode of the fourth transistor is used for receiving the first control signal, and the first control signal is used for controlling the on-off of the fourth transistor; the drain of the fifth transistor is electrically connected with the source of the sixth transistor, the gate of the fifth transistor is used for receiving the fourth control signal, and the fourth control signal is used for controlling the on-off of the fifth transistor; the grid electrode of the sixth transistor is used for receiving the third control signal, and the third control signal is used for controlling the connection and disconnection of the sixth transistor;

the voltage signal includes a first voltage sub-signal and a second voltage sub-signal, a voltage value of the first voltage sub-signal is greater than a voltage value of the second voltage sub-signal, and a voltage value of the second control signal transmitted to the pull-up sub-circuit and a voltage value of the fourth control signal transmitted to the enhancer circuit are equal to a voltage value of the second voltage sub-signal when the first voltage sub-signal is transmitted to the pull-up sub-circuit and the enhancer circuit; when the second voltage sub-signal is transmitted to the pull-up sub-circuit and the enhancer circuit, a voltage value of the fourth control signal transmitted to the enhancer circuit is equal to a voltage value of the second voltage sub-signal, and a voltage value of the second control signal transmitted to the pull-up sub-circuit is smaller than a voltage value of the second voltage sub-signal.

2. The driving circuit of claim 1, wherein the number of the enhancer circuits is the same as the number of the pull-up sub-circuits, and the enhancer circuits are connected in parallel to the pull-up sub-circuits in a one-to-one correspondence.

3. The driving circuit according to claim 1 or 2, wherein the driving circuit further comprises a plurality of pull-down sub-circuits, one end of each of the pull-down sub-circuits is configured to receive a ground signal, and the other end of each of the pull-down sub-circuits is electrically connected to the output terminal, and the pull-down sub-circuits are configured to drive the output terminal to output a pull-down electrical signal according to the ground signal.

4. The driver circuit of claim 3, wherein the pull-up sub-circuit and the enhancer circuit comprise at least one PMOS and the pull-down sub-circuit comprises at least one NMOS.

5. The driving circuit as claimed in claim 3, wherein the pull-down sub-circuit comprises a seventh transistor, an eighth transistor and a ninth transistor arranged in series, a source of the seventh transistor is used for receiving the ground signal, a drain of the seventh transistor is electrically connected to a source of the eighth transistor, and a drain of the ninth transistor is electrically connected to the output terminal; the grid electrode of the seventh transistor is used for receiving a fifth control signal, and the fifth control signal is used for controlling the on-off of the seventh transistor; the drain of the eighth transistor is electrically connected with the source of the ninth transistor, the gate of the eighth transistor is used for receiving a sixth control signal, and the sixth control signal is used for controlling the on-off of the eighth transistor; the grid electrode of the ninth transistor is used for receiving a seventh control signal, and the seventh control signal is used for controlling the on-off of the ninth transistor.

6. A memory device, characterized in that the memory device comprises a memory and a driving circuit according to any one of claims 1-5, wherein the memory is used for storing electric signals output by the output terminal.