CN114675504A

CN114675504A - Photoetching method

Info

Publication number: CN114675504A
Application number: CN202210336655.0A
Authority: CN
Inventors: 董俊; 张其学; 陈骆; 王雷
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp; Hua Hong Semiconductor Wuxi Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp; Hua Hong Semiconductor Wuxi Co Ltd
Priority date: 2022-03-31
Filing date: 2022-03-31
Publication date: 2022-06-28

Abstract

The invention relates to a photoetching method, which comprises the following steps: determining whether the defocusing defect position on the surface of the wafer is fixed or not according to the defocusing defect pattern; if the defocusing defect position is fixed, determining a segmentation layout corresponding to the defocusing defect position according to the initial mask layout and the defocusing defect pattern; adjusting exposure parameters of the segmentation layout corresponding to the defocused defect position; and exposing the wafer in sequence by using all the segmentation layouts. According to the method, the defocusing defect position is fixed, the initial mask layout and the defocusing defect graph are used for determining the segmentation layout corresponding to the defocusing defect position, so that the exposure parameter of the segmentation layout corresponding to the defocusing defect position is adjusted, the position of the mask graph transferred to the wafer is adjusted in advance in the photoetching process, the problem that when the surface of the wafer is ground by chemical machinery, the partial area on the wafer is ground excessively or is not ground sufficiently due to the load effect generated on the surface of the wafer is solved, and the yield of devices is improved.

Description

Photoetching method

Technical Field

The application relates to the technical field of semiconductor photoetching, in particular to a photoetching method.

Background

Currently, Chemical Mechanical Polishing (CMP) processes are widely used in various stages for improving wafer (wafer) flatness.

In the early stage of the manufacturing process of the integrated circuit chip, the patterns of the integrated circuit chip need to be designed, different patterns can be designed through the wiring (lay out), and the pattern density of the different patterns is different. In the post-manufacturing process, due to the characteristics of the CMP process, loading effects (loading effects) are easily generated in regions with different pattern densities (pattern densities) on the wafer, so that the local regions on the surface of the wafer are over-ground or under-ground, thereby affecting the performance of the finally prepared rf chip (semiconductor chip).

Disclosure of Invention

The application provides a photoetching method which can solve the problem that when the surface of a wafer is subjected to chemical mechanical polishing, a load effect is generated on the surface of the wafer, so that a part of area on the wafer is over-polished or not fully polished.

In one aspect, an embodiment of the present application provides a photolithography method, where an initial mask layout is composed of a plurality of divided layouts arranged in an array, and is used to completely transfer a designed pattern onto a wafer, and the photolithography method includes:

determining whether the defocusing defect position of the wafer surface is fixed or not according to the defocusing defect patterns of at least two batches of exposed wafers;

if the defocusing defect position is fixed, determining the segmentation layout corresponding to the defocusing defect position according to the initial mask layout and the defocusing defect pattern;

adjusting exposure parameters of the segmentation layout corresponding to the defocused defect position;

and exposing the wafers to be exposed in sequence by utilizing all the segmentation layouts.

Optionally, in the lithography method, the step of adjusting the exposure parameter of the split layout corresponding to the defocus defect position includes:

and adjusting the exposure offset of the segmentation layout corresponding to the defocused defect position.

Optionally, in the photolithography method, the exposure offset is-800 μm to-1200 μm.

Optionally, in the photolithography method, the exposure offset is +800 μm to +1200 μm.

Optionally, in the photolithography method, if the defocus defect position is fixed, the step of determining the split layout corresponding to the defocus defect position according to the initial mask layout and the defocus defect pattern includes:

and if the defocusing defect position is fixed, overlapping the initial mask layout and the defocusing defect pattern to determine the segmentation layout corresponding to the defocusing defect position.

Optionally, in the photolithography method, each defocused defect position corresponds to at least two of the divided layouts.

Optionally, in the photolithography method, the segmentation layout corresponding to the defocus defect position is a design pattern of a shallow trench isolation structure.

The technical scheme at least comprises the following advantages:

according to the method, the defocusing defect position is fixed, the initial mask layout and the defocusing defect graph are used for determining the segmentation layout corresponding to the defocusing defect position, so that the exposure parameter of the segmentation layout corresponding to the defocusing defect position is adjusted, the position of the mask graph transferred to the wafer is adjusted in advance in the photoetching process, the problem that when the surface of the wafer is ground by chemical machinery, a part of area on the wafer is ground excessively or is not ground sufficiently due to the load effect generated on the surface of the wafer is solved, and the yield of finally prepared semiconductor chips is improved.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a flow chart of a lithographic method according to an embodiment of the invention.

Detailed Description

The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in this application will be understood to be a specific case for those of ordinary skill in the art.

In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.

An initial mask layout is composed of a plurality of partitioned layouts arranged in an array manner and used for completely transferring a designed graph onto a wafer, please refer to fig. 1, fig. 1 is a flowchart of a photolithography method according to an embodiment of the present invention, and the photolithography method includes:

s10: and comparing and analyzing the defocusing defect patterns of the at least two batches of exposed wafers to determine whether the defocusing defect positions on the surfaces of the wafers are fixed. Specifically, in this embodiment, the defocus defect position is located at the edge of the wafer, and the split layout corresponding to the defocus defect position may be a design pattern of the shallow trench isolation structure.

S20: and if the defocusing defect position is fixed, determining the segmentation layout corresponding to the defocusing defect position according to the initial mask layout and the defocusing defect pattern. Specifically, if the defocus defect position is fixed, the initial mask layout and the defocus defect pattern are overlapped to determine the segmentation layout corresponding to the defocus defect position. In this embodiment, each defocused defect position corresponds to at least two of the divided layouts.

S30: and adjusting exposure parameters of the segmentation layout corresponding to the defocused defect position. Specifically, the exposure offset of the divided layout corresponding to the defocus defect position is adjusted. The exposure offset is-800 mu m to-1200 mu m. The exposure offset is +800 mu m to +1200 mu m.

S40: and exposing the wafers to be exposed in sequence by utilizing all the segmentation layouts.

According to the method, the fixed defocusing defect position is determined by comparing and analyzing defocusing defect graphs of a plurality of previous batches of exposed wafers, the segmentation layout corresponding to the defocusing defect position is determined by overlapping the defocusing defect graphs and the initial mask layout, so that the exposure offset of the segmentation layout corresponding to the defocusing defect position is adjusted, the position of the mask pattern transferred onto the wafer is adjusted in advance in a photoetching process, the problem that when the surface of the wafer is subjected to chemical mechanical polishing in a subsequent manufacturing process, a part of a region on the wafer is over-polished or insufficiently polished due to a load effect generated on the surface of the wafer is solved, and the yield of finally prepared semiconductor chips is improved.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.

Claims

1. A photoetching method is characterized in that an initial mask layout is composed of a plurality of divided layouts arranged in an array mode and used for completely transferring a designed graph to a wafer, and the photoetching method comprises the following steps:

and exposing the wafers to be exposed in sequence by using all the segmentation layouts.

2. The lithography method according to claim 1, wherein the step of adjusting the exposure parameters of the divided layout corresponding to the defocus defect position comprises:

3. The lithographic method of claim 2, wherein the exposure offset is in the range of-800 μm to-1200 μm.

4. The lithography method according to claim 2, wherein the exposure shift amount is +800 μm to +1200 μm.

5. The lithography method according to claim 1, wherein if said defocus defect position is fixed, the step of determining said split layout corresponding to said defocus defect position according to said initial mask layout and said defocus defect pattern comprises:

6. The lithography method according to claim 1, wherein each of said defocused defect locations corresponds to at least two of said split layouts.

7. The lithography method according to claim 1, wherein the segmentation layout corresponding to the defocused defect position is a design pattern of a shallow trench isolation structure.