CN114675504A - A photolithography method - Google Patents

Abstract

A lithography method of the present invention includes: determining whether the position of the defocus defect on the wafer surface is fixed according to the defocus defect pattern; if the position of the defocus defect is fixed, then according to the initial mask layout and the defocus defect pattern , determine the division layout corresponding to the position of the defocus defect; adjust the exposure parameters of the division layout corresponding to the position of the defocus defect; and use all the division layouts to sequentially expose the wafer. In the present application, the position of the defocus defect is fixed, and the initial mask layout and the defocus defect pattern are used to determine the divided layout corresponding to the defocus defect position, so as to adjust the size of the divided layout corresponding to the defocus defect position. Exposure parameters, so that the position of the mask pattern transferred to the wafer can be adjusted in advance during the lithography process, avoiding the loading effect on the wafer surface when chemical mechanical polishing the wafer surface. The problem of being over-polished or under-polished increases the yield of the device.

Description

A photolithography method

technical field

The present application relates to the technical field of semiconductor lithography, and in particular, to a lithography method.

Background technique

Currently, chemical mechanical polishing (CMP) processes are widely used in various stages of improving wafer flatness.

In the early stage of the manufacturing process of the integrated circuit chip, it is necessary to design the graphics of the integrated circuit chip. Different graphics can be designed through the layout, and the graphics density of different graphics will be different. In the later manufacturing process, due to the characteristics of the CMP process, areas with different pattern densities on the wafer are prone to loading effects, resulting in over-grinding or under-grinding in local areas of the wafer surface, thus affecting the final preparation. performance of radio frequency chips (semiconductor chips).

SUMMARY OF THE INVENTION

The present application provides a photolithography method, which can solve the problem of over-grinding or insufficient grinding of some areas on the wafer due to a load effect on the wafer surface during chemical mechanical grinding of the wafer surface.

On the one hand, an embodiment of the present application provides a lithography method. The initial mask layout is composed of several divided layouts arranged in an array, and is used to completely transfer the designed pattern to the wafer. The lithography Methods include:

Determine whether the position of the defocus defect on the wafer surface is fixed according to the defocus defect patterns of at least two batches of exposed wafers;

If the position of the defocus defect is fixed, determining the divided layout corresponding to the position of the defocus defect according to the initial mask layout and the defocus defect pattern;

adjusting the exposure parameters of the segmented layout corresponding to the defocus defect position;

The wafers to be exposed are exposed sequentially using all the division layouts.

Optionally, in the lithography method, the step of adjusting the exposure parameters of the divided layout corresponding to the defocus defect positions includes:

Adjust the exposure offset of the divided layout corresponding to the defocus defect position.

Optionally, in the lithography method, the exposure offset is -800 μm to -1200 μm.

Optionally, in the lithography method, the exposure offset is +800 μm˜+1200 μm.

Optionally, in the lithography method, if the position of the defocus defect is fixed, confirm the corresponding position of the defocus defect according to the initial mask layout and the defocus defect pattern. The steps of dividing the layout include:

If the position of the defocus defect is fixed, the initial mask layout and the defocus defect pattern are superimposed to determine the divided layout corresponding to the position of the defocus defect.

Optionally, in the lithography method, each of the defocus defect positions corresponds to at least two of the divided layouts.

Optionally, in the lithography method, the divided layout corresponding to the defocus defect position is a design pattern of a shallow trench isolation structure.

The technical solution of the present application includes at least the following advantages:

In the present application, the position of the defocus defect is fixed, and the initial mask layout and the defocus defect graph are used to determine the divided layout corresponding to the defocus defect position, so as to adjust the size of the divided layout corresponding to the defocus defect position. Exposure parameters, so that the position of the mask pattern transferred to the wafer can be adjusted in advance during the lithography process, avoiding the loading effect on the wafer surface when chemical mechanical polishing the wafer surface. The problem of over-grinding or insufficient grinding increases the yield of the final fabricated semiconductor chip.

Description of drawings

In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the accompanying drawings that need to be used in the description of the specific embodiments or the prior art will be briefly introduced below. The drawings are some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

FIG. 1 is a flowchart of a lithography method according to an embodiment of the present invention.

Detailed ways

The technical solutions in the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the indicated device or element must have a specific orientation or a specific orientation. construction and operation, and therefore should not be construed as limitations on this application. Furthermore, the terms "first", "second", and "third" are used for descriptive purposes only and should not be construed to indicate or imply relative importance.

In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal connection of two components, which can be a wireless connection or a wired connection connect. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood in specific situations.

In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict with each other.

The embodiment of the present application provides a lithography method. The initial mask layout is composed of several divided layouts arranged in an array, which is used to completely transfer the designed pattern to the wafer. Please refer to FIG. 1 , FIG. 1 It is a flowchart of a lithography method according to an embodiment of the present invention, and the lithography method includes:

S10: Compare and analyze the defocus defect patterns of at least two batches of exposed wafers, and determine whether the position of the defocus defect on the wafer surface is fixed. Specifically, in this embodiment, the position of the defocus defect is at the edge of the wafer, and the division layout corresponding to the position of the defocus defect may be a design pattern of a shallow trench isolation structure.

S20: If the position of the defocus defect is fixed, determine the divided layout corresponding to the position of the defocus defect according to the initial mask layout and the defocus defect pattern. Specifically, if the position of the defocus defect is fixed, the initial mask layout and the defocus defect pattern are superimposed to determine the divided layout corresponding to the position of the defocus defect. In this embodiment, each of the defocus defect positions corresponds to at least two of the divided layouts.

S30: Adjust the exposure parameter of the divided layout corresponding to the position of the defocus defect. Specifically, the exposure offset of the divided layout corresponding to the defocus defect position is adjusted. The exposure offset is -800 μm to -1200 μm. The exposure offset is +800 μm to +1200 μm.

S40 : sequentially exposing the wafers to be exposed by using all the divided layouts.

In this application, the fixed defocus defect position is first determined by comparing and analyzing the defocus defect patterns of several previous batches of exposed wafers, and then by comparing the defocus defect patterns with the initial reticle The images are stacked to determine the divided layout corresponding to the defocus defect position, so as to adjust the exposure offset of the divided layout corresponding to the defocus defect position, so as to adjust the transfer in advance in the lithography process To the position of the mask pattern on the wafer, it avoids the problem that some areas on the wafer are over-ground or insufficiently ground due to the load effect on the wafer surface when the chemical mechanical polishing of the wafer surface is performed in the subsequent manufacturing process. The yield of the final fabricated semiconductor chip is improved.

Obviously, the above-mentioned embodiments are only examples for clear description, and are not intended to limit the implementation manner. For those of ordinary skill in the art, changes or modifications in other different forms can also be made on the basis of the above description. There is no need and cannot be exhaustive of all implementations here. And the obvious changes or changes derived from this are still within the scope of protection created by the present application.

Claims (7)

1. a lithography method, it is characterized in that, initial mask layout is made up of several divided layouts arranged in an array, and is used to completely transfer the pattern of design to wafer, and described lithography method comprises: Determine whether the position of the defocus defect on the wafer surface is fixed according to the defocus defect patterns of at least two batches of exposed wafers; If the position of the defocus defect is fixed, determining the divided layout corresponding to the position of the defocus defect according to the initial mask layout and the defocus defect pattern; adjusting the exposure parameters of the segmented layout corresponding to the defocus defect position; The wafers to be exposed are exposed sequentially using all the division layouts. 2 . The lithography method according to claim 1 , wherein the step of adjusting the exposure parameters of the divided layout corresponding to the defocus defect positions comprises: 3 . Adjust the exposure offset of the divided layout corresponding to the defocus defect position. 3 . The lithography method according to claim 2 , wherein the exposure offset is -800 μm˜-1200 μm. 4 . 4 . The lithography method according to claim 2 , wherein the exposure offset is +800 μm˜+1200 μm. 5 . 5 . The lithography method according to claim 1 , wherein if the position of the defocus defect is fixed, the defocus defect is confirmed according to the initial mask layout and the defocus defect pattern. 6 . The step of dividing the layout corresponding to the position includes: If the position of the defocus defect is fixed, the initial mask layout and the defocus defect pattern are superimposed to determine the divided layout corresponding to the position of the defocus defect. 6 . The lithography method according to claim 1 , wherein each of the defocus defect positions corresponds to at least two of the divided layouts. 7 . 7 . The lithography method according to claim 1 , wherein the divided layout corresponding to the position of the defocus defect is a design pattern of a shallow trench isolation structure. 8 .

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