CN114665820A

CN114665820A - Oscillator circuit

Info

Publication number: CN114665820A
Application number: CN202111537641.7A
Authority: CN
Inventors: 过伟; 何满杰
Original assignee: Shenzhen Siruida Microelectronics Co ltd
Current assignee: Shenzhen Siruida Microelectronics Co ltd
Priority date: 2021-12-15
Filing date: 2021-12-15
Publication date: 2022-06-24

Abstract

The invention discloses an oscillator circuit, comprising: a bias circuit for providing a bias voltage; the switch control circuit is used for generating a first switch control signal and a second switch control signal according to the first control signal; the ramp voltage generating circuit is used for generating a ramp voltage under the control of the second switch control signal; the first comparison circuit is used for searching a corresponding first comparison result which enables the voltages of the first input point and the second input point to be equal according to the bias voltage and the ramp voltage under the control of the first switch control signal; the first input point and the second input point are two input points which are arranged in the first comparison circuit in advance; the second comparison circuit is used for comparing the reference voltage with the ramp voltage according to a second control signal to generate a second comparison result; and the clock signal output circuit is used for generating a clock signal according to the first comparison result and the second comparison result. The invention can accurately control the end point of the generation of the ramp voltage and solve the problem of charge and discharge which is easy to occur in the traditional oscillator circuit.

Description

Oscillator circuit

Technical Field

The invention belongs to the technical field of electronic circuits, and particularly relates to an oscillator circuit.

Background

In recent society, people are increasingly unable to keep away from various electronic products in their lives, and the electronic products need to supply power, so that the market demand for high-quality switching power supplies is increasing, and meanwhile, research on various technologies applied to the switching power supplies is becoming more and more important. As a product widely applied to the fields of computers, aerospace, communication, consumer electronics and the like, the switching power supply has a great deal of technical and variety development with social progress and further development in the field of power electronics. In a switching power supply chip, based on the principle of Pulse Width Modulation (PWM), an oscillator is an indispensable component, and the chip needs the oscillator to generate an accurate clock signal. The oscillator has a great influence on the performance of the circuit signal processing.

At present, a conventional oscillator circuit is proposed as shown in fig. 1, in which a capacitor C is provided₀For charging and discharging the capacitor, I_BiasFor bias current (a and b are bias coefficients), voltage V_H、V_LThe set high and low threshold voltages are inputted to the comparators CMP1 and CMP2, respectively. Capacitor C₀At a high threshold voltage V_HAnd a low threshold voltage V_LPeriodically changing the state of the latch and controlling the switches K respectively₁And switch K₂Finally, an oscillation output clock signal is formed. From fig. 1, it can be seen that: the frequency of the square wave signal output by the oscillator circuit is inversely proportional to the capacitance C₀Is proportional to the bias current I_BiasThe value of (c). However, the conventional oscillator circuit shown in fig. 1 needs two comparators, which increases the area and power consumption of the system, and thus another conventional oscillator circuit shown in fig. 2 has been proposed, which only needs one comparator CMP and controls the switch K by sampling the state of the output of the comparator CMP through a monostable flip-flop₁And finally, oscillating and outputting a clock signal. From fig. 2, it can be seen that: the square wave signal frequency output by the oscillator is inversely proportional to the capacitance C₀Is proportional to the bias current I_BiasThe value of (c).

However, in the conventional oscillator circuit shown in FIG. 2, the ramp voltage V in the circuit of FIG. 2 is caused by the delay relationship between the comparator CMP and the one-shot flip-flop_TriThere are overcharge and overdischarge problems that affect the accuracy with which the oscillator circuit ultimately outputs a clock signal.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides an oscillator circuit. The technical problem to be solved by the invention is realized by the following technical scheme:

an embodiment of the present invention provides an oscillator circuit, including: a bias circuit, a switch control circuit, a ramp voltage generating circuit, a first comparing circuit, a second comparing circuit and a clock signal output circuit, wherein,

the bias circuit is used for providing a bias voltage;

the switch control circuit is used for generating a first switch control signal and a second switch control signal according to the first control signal;

the ramp voltage generating circuit is connected with the switch control circuit and is used for generating a ramp voltage under the control of the second switch control signal;

the first comparison circuit is connected with the bias circuit, the switch control circuit and the ramp voltage generation circuit and used for searching corresponding output voltages which enable voltages of a first input point and a second input point to be equal according to the bias voltage and the ramp voltage under the control of the first switch control signal to serve as a first comparison result; the first input point and the second input point are two input points which are arranged in the first comparison circuit in advance;

the second comparison circuit is connected with the ramp voltage generation circuit and used for comparing a reference voltage with the ramp voltage according to the second control signal to generate a second comparison result; wherein the second control signal and the first control signal are opposite-phase signals;

the clock signal output circuit is connected with the first comparison circuit and the second comparison circuit and is used for generating a final clock signal according to the first comparison result and the second comparison result;

the switch control circuit is connected with the clock signal output circuit and is also used for updating a first switch control signal and a second switch control signal according to the first control signal and the clock signal.

In the bookIn one embodiment of the invention, the switch control circuit comprises a NOT gate₁And NAND gate NAND₁Wherein, in the process,

the NOT₁Is connected to the input of the first control signal and the first comparison circuit, and the NOT gate NOT₁And the NAND gate₁The first input end of the NAND gate is connected with₁The second input end of the NAND gate is connected with the clock signal output circuit₁Is connected to the ramp voltage generating circuit.

In one embodiment of the present invention, the ramp voltage generating circuit includes a transistor N₃Transistor N₄Capacitor C₀And a current generating circuit, wherein,

the transistor N₃Gate of (1), the transistor N₄Is connected with the switch control circuit, the transistor N₃Is connected to the first comparison circuit, the transistor N₃And the transistor N₄Drain electrode of (1), the capacitor C₀Is connected to the current generating circuit and the second comparing circuit, the transistor N₄Source electrode of, the capacitor C₀And the other end thereof is connected to the ground GND.

In one embodiment of the present invention, the current generation circuit includes: a trimming switch generating circuit, a band gap reference circuit, a voltage-current converting circuit, a trimming circuit and a trimming current output circuit,

the trimming switch generating circuit is used for generating M +1 first trimming switch signals and N +1 second trimming switch signals, and M, N are integers which are larger than 0;

the band-gap reference circuit is connected with the trimming switch generating circuit and is used for generating reference voltage under the control of the M +1 first trimming switch signals;

the voltage-current conversion circuit is connected with the band-gap reference circuit and is used for converting the reference voltage into reference current;

the trimming circuit is connected with the voltage-current conversion circuit and the trimming switch generating circuit and is used for trimming the reference current under the control of the N +1 second trimming switch signals;

and the trimming current output circuit is connected with the trimming circuit and used for outputting the trimmed reference current by using the current mirror image to obtain the trimming current.

In one embodiment of the invention, the bandgap reference circuit comprises a reference circuit with trim function and M +1 first trim switches, wherein,

one end of each of the M +1 first trimming switches is correspondingly connected with the output end of the reference circuit with the trim trimming function and the output end of the trimming switch generating circuit, and the other end of each of the M +1 first trimming switches is connected with the voltage-current conversion circuit.

In one embodiment of the present invention, the trimming circuit includes an N +1 current mirror circuit and N +1 second trimming switches, wherein,

one end of each of the N +1 second trimming switches is connected with a corresponding current mirror circuit in the N +1 current mirror circuits, and the other end of each of the N +1 second trimming switches is connected with the trimming current output circuit; wherein, the ratio of the output currents of the adjacent current mirror circuits is 2.

In one embodiment of the invention, the first comparison circuit comprises a transistor P₁～P₆Transistor N₁Transistor N₂Resistance R₀And a schmitt trigger SMT, in which,

the transistor P₁Source electrode of, the transistor P₂Are all connected with a power supply VDD, and the transistors P₁Of the transistor P₂Of the transistor P₃Of the transistor P₄Is connected to the bias circuit, the transistor P₁And the transistor P₃The source of the transistor P₂And the transistor P₄The source of the transistor P₃And the transistorP₅The source of the transistor P₄And the transistor P₆Of said transistor P, said transistor P₅Of the transistor P₆Is connected to the switch control circuit, the transistor P₅And the transistor N₁Drain electrode of (1), the transistor N₁Gate of (1), the transistor N₂The gate of the transistor P₆And the transistor N₂Is connected with one end of the Schmitt trigger SMT, the transistor N₁Source electrode of and the resistor R₀Is connected to one terminal of the transistor N₂Is connected with the ramp voltage generating circuit, the resistor R₀The other end of the Schmitt trigger SMT is connected with the ground GND, and the other end of the Schmitt trigger SMT is connected with the clock signal output circuit.

In one embodiment of the present invention, the first input point and the second input point are two input points which are previously set in the first comparison circuit, and include:

the first input point is preset in the first comparison circuit and the transistor N₁Source electrode of and the resistor R₀To (c) to (d);

the second input point is preset in the first comparison circuit and the transistor N₂And the ramp voltage generating circuit.

In one embodiment of the present invention, the second comparing circuit is a comparator.

In one embodiment of the present invention, the clock signal output circuit is a D flip-flop.

The invention has the beneficial effects that:

the oscillator circuit provided by the invention can accurately control the end point of ramp voltage generation, and solves the charge and discharge problem easily occurring in the traditional oscillator circuit, and the embodiment of the invention introduces a ramp voltage generation circuit and a first comparison circuit in the oscillator circuit, the ramp voltage generation circuit generates ramp voltage, searches corresponding first comparison results when the voltages of a first input point and a second input point are equal in the first comparison circuit through the ramp voltage, outputs a second comparison result under the action of the ramp voltage, and finally outputs a clock signal under the combined action of the first comparison result and the second comparison result, the clock signal controls the ramp voltage generation circuit to generate the ramp voltage again, the ramp voltage controls the first comparison circuit and the second comparison circuit to output the first comparison result and the second comparison result respectively, and the process of outputting the clock signal under the combined action of the first comparison result and the second comparison result is repeated, the end point of the generation of the slope voltage is accurately controlled, so that the problem of charge and discharge of a traditional oscillator circuit, which is easy to occur, is solved, and the accuracy of the clock signal output by the oscillator circuit is improved.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a schematic circuit diagram of a conventional oscillator circuit;

FIG. 2 is a schematic diagram of another conventional oscillator circuit;

FIG. 3 is a schematic diagram of an operating waveform of the corresponding conventional oscillator circuit of FIG. 2;

fig. 4 is a schematic structural diagram of an oscillator circuit according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a specific circuit structure of an oscillator circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of an operating waveform of an oscillator circuit according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a current generation circuit in an oscillator circuit according to an embodiment of the present invention;

fig. 8 is a schematic circuit diagram of a specific circuit structure of a current generating circuit according to an embodiment of the present invention.

Description of reference numerals:

10-a bias circuit; 20-a switch control circuit; 30-a ramp voltage generating circuit; 40-a first comparison circuit; 50-a second comparison circuit; 60-a clock signal output circuit; 301-a current generating circuit; 3011-trimming switch generating circuit; 3012-bandgap reference circuit; 3013-a voltage to current converter circuit; 3014-a trimming circuit; 3015-trimming current output circuit.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Example one

From the above, the ramp voltage V in the conventional oscillator circuit shown in fig. 2_TriThere are problems of overcharge and overdischarge, and for the reason, see fig. 3. As shown in fig. 3, resulting in a ramp voltage V_TriThere are two cases of overcharge and overdischarge correspondence:

in one case, see the left hand side of FIG. 3, at t₁Time of day, ramp voltage V_TriIs charged to a reference voltage V_RefAt this time, the comparator CMP is inverted, the monostable flip-flop samples the rising edge of the output of the comparator CMP, inverts its output CLKN to a high level, and the switch K is turned on₁On, ramp voltage V_TriThe discharge is started. At t₂Time of day, ramp voltage V_TriDischarge to zero, but due to delay of the monostable flip-flop, until t₃At that time, the output CLKN of the monostable flip-flop is only flipped to a low level, i.e., the ramp voltage V_TriAt t₃Charging is started at that moment.

Alternatively, referring to the right-hand diagram of FIG. 3, the ramp voltage V is caused to flip-flop first_TriThe charge is started again when the charge is not discharged to zero, and the original ramp voltage V_TriShould be at t₅The moment discharges to zero, but because the monostable trigger firstly turns over, the discharge is at t₆Switch K is turned off at any moment₁Resulting in frequency error.

From the above analysis, it can be seen that the conventional oscillator circuit shown in FIG. 2 is not controllable due to the off-time of the switch in the oscillator circuit, and the ramp voltage V_TriThe problems of overcharge and overdischarge exist, so that the performance of the oscillator circuit is unstable, and the output clock signal of the oscillator circuit has large errors.

To avoid the above problem, referring to fig. 4, an embodiment of the present invention provides an oscillator circuit, including: a bias circuit 10, a switch control circuit 20, a ramp voltage generating circuit 30, a first comparing circuit 40, a second comparing circuit 50, and a clock signal output circuit 60, wherein,

a bias circuit 10 for providing a bias voltage;

a switch control circuit 20 for generating a first switch control signal SW according to a first control signal ENP₁And a second switch control signal SW₂；

A ramp voltage generating circuit 30 connected to the switch control circuit 20 for generating the second switch control signal SW₂Under the control of (3), generating a ramp voltage V_Tri；

A first comparison circuit 40 connected to the bias circuit 10, the switch control circuit 20 and the ramp voltage generation circuit 30 for generating a first switch control signal SW₁According to the bias voltage and the ramp voltage V_TriSearching an output voltage corresponding to the first input point and the second input point when the voltages are equal to each other as a first comparison result; wherein, the first input point and the second input point are two input points which are set in the first comparison circuit 40 in advance;

a second comparison circuit 50 connected to the ramp voltage generation circuit 30 for comparing the reference voltage V according to the second control signal ENN_RefAnd a ramp voltage V_TriGenerating a second comparison result; the second control signal ENN and the first control signal ENP are mutually opposite signals;

a clock signal output circuit 60 connected to the first comparison circuit 40 and the second comparison circuit 50, for generating a final clock signal according to the first comparison result and the second comparison result;

the switch control circuit 20 is connected to the clock signal output circuit 60, and further configured to update the first switch control signal and the second switch control signal according to the first control signal and the clock signal.

Next, the embodiments of the present invention will describe each part of the circuit in detail.

The embodiment of the invention provides an offsetAlternative to the circuit 10, see fig. 5, the bias circuit 10 comprises a transistor P₇Transistor P₈A bias current source I_BiasWherein the transistor P₇Is connected with a power supply VDD and a transistor P₇Gate of and transistor P₈Is connected to the first comparison circuit 40, transistor P₈Gate of and transistor P₈Drain electrode of (1), bias current source I_BiasIs connected to a first comparison circuit 40, a bias current source I_BiasThe output terminal of (2) is grounded GND. At a bias current source I_BiasThe bias circuit 10 generates a bias voltage.

Preferably, the transistor P₇Transistor P₈Are all PMOS tubes.

Further, an alternative to the switch control circuit 20 is provided by the embodiment of the present invention, and referring back to fig. 5, the switch control circuit 20 includes a NOT gate NOT₁And NAND gate NAND₁Wherein, NOT is NOT₁Is connected to the input of the first control signal, to the first comparison circuit 40, and is NOT-gated₁And NAND gate₁Is connected with the first input terminal of NAND gate₁Is connected to the clock signal output circuit 60, NAND gate NAND₁Is connected to the ramp voltage generating circuit 30. In the initial working stage of the oscillator circuit, the switch control circuit 20 generates the first switch control signal SW according to the first control signal ENP₁And a second switch control signal SW₂At this time, the clock signal output circuit 60 sets an initial value according to actual needs, for example, the initial value is 0; in the operating stage of the oscillator circuit, the first switch control signal SW is updated according to the real-time output of the clock signal output circuit 60 and the first control signal ENP₁And a second switch control signal SW₂. Subsequently controlling the signal SW through the first switch₁And a second switch control signal SW₂The operating states of the first comparison circuit 40 and the ramp voltage generation circuit 30 are controlled separately. Wherein the first switch control signal SW₁Is the first control signal ENP.

In the embodiment of the present invention, the first control signal ENP determines the working state of the entire oscillator circuit, when the first control signal ENP is at a high level, the entire oscillator circuit outputs a constant clock signal CLK, and when the first control signal ENP is at a low level, the entire oscillator circuit enables the first comparison circuit 40, the second comparison circuit 50 and the ramp voltage generation circuit 30, so as to accurately control the end point of ramp voltage generation, and solve the charge and discharge problems that occur easily in the conventional oscillator circuit.

Further, the embodiment of the present invention provides an alternative to the ramp voltage generating circuit 30, and referring to fig. 5 again, the ramp voltage generating circuit 30 includes a transistor N₃Transistor N₄Capacitor C₀And a current generation circuit 301, in which a transistor N₃Gate of (1), transistor N₄NAND gate NAND in the gate-and-switch control circuit 20₁Is connected to the output terminal of transistor N₃Is connected to a first comparison circuit 40, a transistor N₃Source of and transistor N₄Drain electrode of (1), capacitor C₀Is connected to the current generation circuit 301 and the second comparison circuit 50, and the transistor N₄Source electrode and capacitor C₀And the other end thereof is connected to the ground GND. The ramp voltage generating circuit 30 of the embodiment of the invention outputs the second switch control signal SW in the switch control circuit 20₂Under control, the transistor N is switched₃Transistor N₄And the current generation circuit 301 is used to realize the pair of capacitors C₀Charging and discharging of (3), finally outputting a ramp voltage V_Tri。

Preferably, the transistor N₃Transistor N₄Are all NMOS tubes.

Further, an alternative to the first comparison circuit 40 is provided in the embodiment of the present invention, and referring back to fig. 5, the first comparison circuit 40 includes a transistor P₁～P₆Transistor N₁Transistor N₂Resistance R₀And Schmitt trigger SMT, in which a transistor P₁Source electrode of (1), transistor P₂The source electrodes of the transistors are all connected with a power supply VDD and a transistor P₁Gate of (1), transistor P₂Gate and bias circuit of10 transistor P₇Of the transistor P₃Gate of (1), transistor P₄Gate of and bias circuit 10₈Of the transistor P₁And the drain of the transistor P₃Of the transistor P₂And the drain of the transistor P₄Of the transistor P₃And the drain of the transistor P₅Of the transistor P₄And a transistor P₆Of the transistor P₅Gate of (1), transistor P₆And NOT gate NOT in the switch control circuit 20₁Is connected to the input terminal of a transistor P₅And transistor N₁Drain electrode of (1), transistor N₁Gate of (1), transistor N₂Of the transistor P₆And transistor N₂Is connected with one end of the Schmitt trigger SMT, and a transistor N₁Source and resistor R of₀Is connected to a transistor N₂And the transistor N in the ramp voltage generating circuit 30₃Is connected to the drain of the resistor R₀The other end of the schmitt trigger SMT is connected to the ground GND, and the other end of the schmitt trigger SMT is connected to the clock signal output circuit 60. In the embodiment of the present invention, the first comparison circuit 40 controls the signal SW at the first switch₁Under control, according to the bias voltage and the ramp voltage V_TriFinding the output voltage corresponding to the voltage equality of the first input point and the second input point as a first comparison result V_O1. Wherein, the first input point and the second input point are two input points preset in the first comparison circuit 40, and the embodiment of the present invention specifically includes: the first input point is preset in the first comparison circuit 40 by the transistor N₁Source and resistor R of₀Point a as shown in fig. 5; the second input point is preset in the first comparison circuit 40 by the transistor N₂And the ramp voltage generating circuit 30, as shown at point B in fig. 5.

Preferably, the transistor P₁～P₆Are all PMOS tubes; transistor N₁Transistor N₂Are all NMOS tubes.

Further, embodiments of the present inventionThe second comparator circuit 50 is a comparator, and referring to fig. 5, the positive input terminal of the comparator is connected to the reference voltage V_RefIs connected to the input terminal of the comparator, and the inverting input terminal of the comparator is connected to the current generating circuit 301 and the capacitor C in the ramp voltage generating circuit 30₀One terminal of (1), transistor N₃And transistor N₄The control terminal of the comparator is connected to the input terminal of the second control signal ENN, and the output terminal of the comparator is connected to the clock signal output circuit 60. In the embodiment of the present invention, the second control signal ENN and the first control signal ENP are opposite phase signals, and the second comparison circuit 50 compares the reference voltage V under the control of the second control signal ENN_RefAnd a ramp voltage V_TriFinally, the second comparison result V is output_O2。

Further, the clock signal output circuit 60 according to the embodiment of the present invention may be a D flip-flop, as shown in fig. 5, where the D flip-flop includes a NOT gate₂NAND gate₂NAND gate₃NOT and AND gate₃Wherein, NOT is NOT₂Is connected to one end of the schmitt trigger SMT in the first comparison circuit 40, and is NOT-gated₂And NAND gate NAND₂Is connected with the first input end of the NAND gate₂And NAND gate NAND₃Output terminal of, NOT gate₃Is connected with NAND gate₂And NAND gate NAND₃Is connected with the first input terminal of NAND gate₃Is connected to the output of the second comparison circuit 50, NOT-gate NOT₃Is the output of the final clock signal. The clock signal output circuit 60 of the embodiment of the present invention finally outputs the clock signal CLK.

Based on the above circuit design, the operating waveform of the oscillator circuit provided in the embodiment of the present invention is as shown in fig. 6, specifically:

in the initial working phase of the oscillator circuit, the first control signal ENP is set to be at a low level, and the corresponding second control signal ENN is set to be at a high level, at this time, the entire oscillator circuit is in a working state, including the first comparison circuit 40 and the second comparison circuit 50, which are both in an enabled state.

In the operating phase of the oscillator circuit, at t₁Time of day, ramp voltage V_TriRising to a reference voltage V_RefAt this time, the second comparison result V outputted from the comparator CMP in the second comparison circuit 50_O2Is turned over to low level, and the second comparison result V_O2The final clock signal CLK of the clock signal output circuit 60 is forced to also flip to the low level. At this time, the clock signal CLK of low level acts on the switch control circuit 20, and also forces the second switch control signal SW output from the switch control circuit 20₂Is inverted to a high level when the transistor N of the ramp voltage generating circuit 30 is turned over₃And transistor N₄On, the capacitance C₀The discharge is started so that the voltage at the point B of the second input point in the first comparison circuit 40 starts to drop, and when the voltage at the point B of the second input point drops to be equal to the voltage at the point A of the first input point, the voltage V output by the point C in the first comparison circuit 40 is started_O3And turning over and beginning to slowly descend. Since the time for the voltage to drop from the second input point B to the first input point a is about several ns, such a change is not shown in fig. 6.

At t₂At the moment, V is outputted from point C in the first comparison circuit 40_O3Falls to make the Schmitt trigger SMT flip, the first comparison circuit 40 outputs a first comparison result V_O1First comparison result V_O1After the clock signal CLK is inverted to a high level by the clock signal output circuit 60, the second switch control signal SW is turned on by the clock signal CLK being inputted to the switch control circuit 20₂Inverted to low level, transistor N₃And transistor N₄Turn off, at which time the current I is trimmed_OSCStart to supply the capacitor C₀Charging, ramp voltage V_TriStarts to rise gradually, corresponding to V outputted from point C of the first comparison circuit 40_O3It also begins to rise slowly.

At t₃V output at time, C_O3Rises to a level that causes the Schmitt trigger SMT output to flip, corresponding to V output at point D in clock signal output circuit 60_O4Toggling to a high level.

At t₄At the time of day, the user may,the voltages at the first input point a and the second input point B of the first comparing circuit 40 are equal, and the reference voltage V is the same in the embodiment of the present invention_Ref0Can take the voltage value of the first input point A, and the ramp voltage V is at the moment_TriRises again until the reference voltage V_RefRepeating the above t₁～t₃In the process, the time sequence is controlled to pass through the capacitor C₀Ramp voltage V generated by charging and discharging_TriThe problems of overcharge and overdischarge are avoided, so that the stability of the output clock signal of the oscillator circuit is ensured, and the generation of frequency errors is avoided.

To overcome Process, Voltage and temperature (PVT) vs. capacitance C₀In the ramp voltage generating circuit 30 according to the embodiment of the present invention, the current generating circuit 301 with the trimming function is selected so as to cover the process, voltage and PVT pair capacitor C₀The influence of (c). Specifically, the embodiment of the present invention provides an alternative solution for the current generating circuit 301, referring to fig. 7, the current generating circuit 301 includes: a trimming switch generating circuit 3011, a bandgap reference circuit 3012, a voltage-to-current converting circuit 3013, a trimming circuit 3014, and a trimming current output circuit 3015, wherein,

a trimming switch generating circuit 3011, configured to generate M +1 first trimming switch signals and N +1 second trimming switch signals, M, N being integers greater than 0;

the band-gap reference circuit 3012 is connected to the trimming switch generating circuit 3011 and configured to generate a reference voltage under the control of the M +1 first trimming switch signals;

a voltage-current conversion circuit 3013 connected to the bandgap reference circuit 3012 and configured to convert the reference voltage into a reference current;

the trimming circuit 3014 is connected to the voltage-to-current conversion circuit 3013 and the trimming switch generation circuit 3011, and configured to trim the reference current under the control of the N +1 second trimming switch signals;

and the trimming current output circuit 3015 is connected to the trimming circuit 3014 and configured to output the trimmed reference current by using a current mirror image to obtain a trimming current.

Next, each circuit in the current generation circuit 301 will be described in detail.

Referring to fig. 8, the trimming switch generating circuit 3011 may be implemented by using an existing circuit as long as M +1 first trimming switch signals and N +1 second trimming switch signals can be generated, and a specific circuit structure is not limited, for example, M +1 first trimming switch signals and N +1 second trimming switch signals may be formed by outputting high and low electrical signals according to actual requirements.

Further, an alternative of the voltage-current conversion circuit 3013 is provided in the embodiments of the present invention, please refer to fig. 8, in which the voltage-current conversion circuit 3013 includes an amplifier AMP and a transistor Q₀Resistance R₁Transistor M₁～M₄Wherein the non-inverting input terminal of the amplifier AMP is connected to the output terminal of the bandgap reference circuit 3012, and the inverting input terminal of the amplifier AMP is connected to the transistor Q₀Source electrode, resistance R₁Is connected to the output terminal of the amplifier AMP and the transistor Q₀Is connected to the gate of, and a resistor R₁Is grounded to GND, a transistor Q₀And the transistor M₁Drain electrode of (1), transistor M₁Gate of (1), transistor M₂Is connected to the gate of transistor M₁Source and transistor M₃Drain electrode of (1), transistor M₃Gate of (1), transistor M₄Is connected to the gate of transistor M₂Is connected with the trimming circuit 3014, and the transistor M₂Source and transistor M₄Of the transistor M₃Source electrode of (1), transistor M₄The sources of the first and second transistors are all connected with a power supply VDD.

Preferably, the transistor Q₀Is an NMOS tube; transistor M₁～M₄Are all PMOS tubes.

The embodiment of the invention can know that the reference current I is based on the basic principle of a V (voltage) -I (current) conversion circuit_TrimCan be expressed as:

as can be seen, the reference current I_TrimBy resistance R₀Has a large influence on the resistance R in order to overcome the process₀Based on the voltage-to-current conversion circuit 3013, the embodiment of the present invention proposes to use a bandgap reference circuit 3012 with a trimming function, specifically:

referring to fig. 8 again, the bandgap reference circuit 3012 includes a reference circuit with trim function and M +1 first trimming switches S₀～S_MOne end of each of the M +1 first trimming switches is correspondingly connected to an output end of the reference circuit with the trim trimming function and an output end of the trimming switch generating circuit 3011, and the other end of each of the M +1 first trimming switches is connected to the voltage-to-current conversion circuit 3013. The reference circuit with trim function can be realized by adopting the existing circuit, can output M +1 different reference voltages, and is provided with M +1 first trim switches S₀～S_MUnder the control of the control circuit, a plurality of reference voltages are extracted to form the reference voltage V finally generated by the embodiment of the invention_Trim. Extracting different reference voltages under different processes to generate final reference voltage V_TrimEquivalent to overcoming the process pair resistance R₀The influence caused by the current I is further obtained_Trim。

Further, the capacitance C is aimed at₀The embodiment of the present invention proposes to design the trimming circuit 3014 to trim the current before outputting the current. Referring to fig. 8 again, the trimming circuit 3014 mainly includes an N +1 current mirror circuit and N +1 second trimming switches F₀～F_NWherein, one end of the N +1 second trimming switches is connected with the corresponding current mirror circuit in the N +1 current mirror circuits, the other end of the N +1 second trimming switches is connected with the trimming current output circuit 3015, and each current mirror circuit includes a transistor Q₃Transistor Q₄All transistors Q₃Are interconnected, all transistors Q₄Are interconnected, all transistors Q₃The drain electrode of the second trimming switch is connected with one end of the corresponding second trimming switch, and all the crystalsTube Q₃And corresponding transistor Q₄Drain electrode of (2), all transistors Q₄The source of the second trimming switch is grounded, and the other ends of all the second trimming switches are connected with the trimming current output circuit 3015; the trimming circuit 3014 further includes a transistor Q₁Transistor Q₂Transistor Q₅Transistor Q₆Wherein the transistor Q₁Gate of and transistor Q₁Drain electrode of (1), and transistor Q₃Gate of (3), transistor M in voltage circuit conversion circuit₂Of the transistor Q₁Source and transistor Q of₂Drain electrode of (1), and transistor Q₂Gate of (2), transistor Q₄Of the transistor Q₂Source of (1) is grounded GND, transistor Q₅Gate of and transistor Q₃Of the transistor Q₅Source and transistor Q of₆Of the transistor Q₅Is connected with the trimming current output circuit 3015, and a transistor Q₆Gate of and transistor Q₄Of the transistor Q₆Is connected to ground GND. The output current ratio of adjacent current mirror circuits is 2, and the difference of the trimming current of each current mirror circuit is doubled. Reference current I in the embodiments of the present invention_TrimAfter trimming, the process can be overcome for the capacitor C₀While the trimming circuit 3014 can overcome the problem of the transistor M in the voltage circuit switching circuit₁～M₄The error possibly brought by the formed current mirror image can be obtained, and then the reference current I of the high-precision oscillator required by the system can be obtained_Trim。

Preferably, the transistor Q₁Transistor Q₂Transistor Q₅Transistor Q₆Are all NMOS tubes; transistor Q in each current mirror circuit₃Transistor Q₄Are all NMOS tubes.

Further, an alternative of the trimming current output circuit 3015 is provided in the embodiments of the present invention, in which the trimming current is outputted by using a current mirror image, referring to fig. 8 again, the trimming current output circuit 3015 includes a transistor M₅～M₈Wherein the transistor M₅Source electrode of (1), transistor M₆The source electrodes of the transistors M are all connected with a power supply VDD₅Gate of and transistor M₅Drain electrode of (1), transistor M₆Gate of (1), transistor M₇Of transistor M₆And the transistor M₈Of transistor M₇Gate of and transistor M₇Drain electrode of (1), transistor M₈And a second trimming switch F in the trimming circuit 3014₀～F_NTransistor Q₅Of the transistor M₈And the transistor N in the ramp voltage generating circuit 30₃Source electrode of (1), transistor N₄Drain electrode of (1), capacitor C₀And the inverting input of the second comparison circuit 50. Similarly, the current mirror error can be adjusted by the trimming circuit 3014, so as to output the high-precision oscillator trimming current I required by the system_OSC。

Preferably, the transistor M₅～M₈Are all PMOS tubes.

In summary, the oscillator circuit provided in the embodiments of the present invention can precisely control the ramp voltage V_TriThe generated end point solves the charge and discharge problem of the traditional oscillator circuit, and specifically, in the embodiment of the invention, the ramp voltage generating circuit 30 and the first comparison circuit 40 are introduced into the oscillator circuit, and the ramp voltage generating circuit 30 generates the ramp voltage V_TriBy a ramp voltage V_TriFinding a corresponding first comparison result V when the voltages of the first input point A and the second input point B are equal in the first comparison circuit 40_O1And the second comparison circuit 50 is at the ramp voltage V_TriUnder the action of the first comparison result V, outputting a second comparison result V_O2Finally, from the first comparison result V_O1And a second comparison result V_O2The clock signal CLK is outputted in cooperation, and the ramp voltage generating circuit 30 is controlled again by the clock signal CLK to generate the ramp voltage V_TriFrom a voltage ramp V_TriRespectively controlling the first comparison circuit 40 and the second comparison circuit 50 to output a first comparison result V_O1And a second comparison result V_O2Repeating such a comparison from the first comparison result V_O1And a secondComparison result V_O2The process of outputting the clock signal CLK under the combined action realizes the accurate control of the ramp voltage V_TriThe generated end point is used for solving the charge and discharge problem which is easy to occur in the traditional oscillator circuit, thereby improving the accuracy of the clock signal CLK output by the oscillator circuit.

Meanwhile, for the influence caused by the process, the temperature and the like, the current generating circuit 301 adopted in the ramp voltage generating circuit 30 according to the embodiment of the present invention has the trimming function, and the specific bandgap reference circuit 3012 and the trimming circuit 3014 respectively control different trimming switch combinations, so that the current generating circuit 301 generates the high-precision trimming current I required by the system_OSCFor a ramp voltage V_TriThereby improving the accuracy of the oscillator circuit outputting the clock signal CLK.

In the description of the present invention, it is to be understood that the terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.

While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. An oscillator circuit, comprising: a bias circuit, a switch control circuit, a ramp voltage generating circuit, a first comparing circuit, a second comparing circuit and a clock signal output circuit, wherein,

the bias circuit is used for providing a bias voltage;

2. The oscillator circuit of claim 1, wherein the switch control circuit comprises a NOT gate NOT₁And NAND gate NAND₁Wherein, in the step (A),

3. The oscillator circuit of claim 1, wherein the ramp voltage generation circuit comprises a transistor N₃Transistor N₄Capacitor C₀And a current generating circuit, wherein,

the transistor N₃Gate of (1), the transistor N₄Is connected with the switch control circuit, the transistor N₃Is connected to the first comparison circuit, the transistor N₃And the transistor N₄Drain electrode of (1), the capacitor C₀One end of, theThe current generating circuit is connected with the second comparison circuit, and the transistor N₄Source electrode of, the capacitor C₀And the other end thereof is connected to the ground GND.

4. The oscillator circuit of claim 3, wherein the current generation circuit comprises: a trimming switch generating circuit, a band gap reference circuit, a voltage current converting circuit, a trimming circuit and a trimming current output circuit, wherein,

the trimming switch generating circuit is used for generating M +1 first trimming switch signals and N +1 second trimming switch signals, M, N are integers which are larger than 0;

5. The oscillator circuit of claim 4, wherein the bandgap reference circuit comprises a reference circuit with trim function and M +1 first trim switches, wherein,

6. The oscillator circuit of claim 4, wherein the trimming circuit comprises an N +1 circuit current mirror circuit and N +1 second trimming switches, wherein,

7. The oscillator circuit of claim 1, wherein the first comparison circuit comprises a transistor P₁～P₆Transistor N₁Transistor N₂Resistance R₀And a schmitt trigger SMT, wherein,

the transistor P₁Source electrode of, the transistor P₂Are all connected with a power supply VDD, and the transistors P₁Of the transistor P₂Of the transistor P₃Of the transistor P₄Is connected to the bias circuit, the transistor P₁And the transistor P₃The source of the transistor P₂And the transistor P₄The source of the transistor P₃And the transistor P₅The source of the transistor P₄And the transistor P₆The source of the transistor P₅Of the transistor P₆Is connected to the switch control circuit, the transistor P₅And the transistor N₁Drain electrode of (1), the transistor N₁Gate of (1), the transistor N₂Of the transistor P, the transistor P₆And the transistor N₂Is connected to one end of the Schmitt trigger SMT, the transistor N₁Source electrode of and the resistor R₀Is connected to one terminal of the transistor N₂Is connected with the ramp voltage generating circuit, the resistor R₀Is connected to the ground GND, and the other end of the schmitt trigger SMT is connected to the clock signal inputAnd (4) outputting the circuit connection.

8. The oscillator circuit according to claim 7, wherein the first input point and the second input point are two input points previously set in the first comparison circuit, and include:

9. The oscillator circuit of claim 1, wherein the second comparison circuit is a comparator.

10. The oscillator circuit of claim 1, wherein the clock signal output circuit is a D flip-flop.