CN114665575B

CN114665575B - Voltage reduction circuit, circuit integrated chip, charging circuit and terminal equipment

Info

Publication number: CN114665575B
Application number: CN202210546865.2A
Authority: CN
Inventors: 陈佳; 刘小勇
Original assignee: Meizu Technology Co Ltd
Current assignee: Meizu Technology Co Ltd
Priority date: 2022-05-20
Filing date: 2022-05-20
Publication date: 2022-08-23
Anticipated expiration: 2042-05-20
Also published as: CN114665575A

Abstract

The present disclosure relates to the field of charging technologies, and in particular, to a voltage reduction circuit, a circuit integrated chip, a charging circuit, and a terminal device. Wherein, step-down circuit includes: the energy storage device comprises a first energy storage unit, a second energy storage unit, a third energy storage unit, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a seventh switch unit and an eighth switch unit; the energy storage units are subjected to charge and discharge combined control through the switch units, and specific parameter setting of the energy storage units is combined, so that high-power charging is realized, the charging efficiency is improved, the cost is reduced, the use space of a circuit board is optimized, and the complexity of software control logic is reduced.

Description

Voltage reduction circuit, circuit integrated chip, charging circuit and terminal equipment

Technical Field

The present disclosure relates to the field of charging technologies, and in particular, to a voltage reduction circuit, a circuit integrated chip, a charging circuit, and a terminal device.

Background

The charging scheme of the traditional wireless receiving end adopts a Buck Converter (Buck) circuit, and because the conduction and closing loss exists in a Metal Oxide Semiconductor (MOS) tube, and the loss of a coil and a magnetic core exists in an inductor, the charging efficiency of the Buck circuit is reduced. The energy lost by the power device is basically converted into heat energy, so that the heating of the charging scheme adopting the Buck circuit is serious, and the charging current cannot be increased by the charging scheme.

In order to solve the technical problems, in the charging scheme of the wireless receiving end, two 1/2 voltage reduction charge pumps are connected in series for use, namely, voltage reduction is carried out twice, and high-power charging can be realized while input current and coil heating are reduced. However, this design increases the footprint on the circuit board, increases the cost and increases the complexity of the software control logic by adding a charge pump.

Disclosure of Invention

In order to solve the technical problem, the present disclosure provides a voltage reduction circuit, a circuit integrated chip, a charging circuit and a terminal device, which can reduce cost, optimize a use space of a circuit board and reduce complexity of a software control logic while realizing high-power charging and improving charging efficiency.

In a first aspect, an embodiment of the present disclosure provides a voltage reduction circuit, which includes a first energy storage unit, a second energy storage unit, a third energy storage unit, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a seventh switch unit, and an eighth switch unit;

the first switch unit, the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit and the sixth switch unit are connected in series, and the first switch unit is connected with a voltage input end; the seventh switching unit is connected in series with the eighth switching unit, and the seventh switching unit is connected with a voltage output end and connected between the fourth switching unit and the fifth switching unit; one end of the first energy storage unit is connected between the first switch unit and the second switch unit, the other end of the first energy storage unit is connected with one end of the third energy storage unit, and the first energy storage unit is connected between the seventh switch unit and the eighth switch unit; the other end of the third energy storage unit is connected between the third switching unit and the fourth switching unit, one end of the second energy storage unit is connected between the second switching unit and the third switching unit, and the other end of the second energy storage unit is connected between the fifth switching unit and the sixth switching unit; the sixth switching unit and the eighth switching unit are respectively grounded;

the voltage reduction circuit periodically operates, and

in each working cycle, in the first half cycle, the first switch unit, the third switch unit, the sixth switch unit and the seventh switch unit are turned on, the second switch unit, the fourth switch unit, the fifth switch unit and the eighth switch unit are turned off, and in the second half cycle, the second switch unit, the fourth switch unit, the fifth switch unit and the eighth switch unit are turned on, and the first switch unit, the third switch unit, the sixth switch unit and the seventh switch unit are turned off;

the first energy storage unit, the second energy storage unit and the third energy storage unit are respectively configured to store preset electric quantity, so that the output voltage of the voltage output end is 1/4 of the input voltage of the voltage input end.

In some embodiments, the first energy storage unit includes a first capacitor, and a voltage difference between an upper plate and a lower plate of the first capacitor is 3/4 Vin;

the second energy storage unit comprises a second capacitor, and the voltage difference between an upper plate and a lower plate of the second capacitor is 2/4 Vin;

the third energy storage unit comprises a third capacitor, and the voltage difference between an upper plate and a lower plate of the third capacitor is 1/4 Vin;

wherein Vin represents the input voltage of the voltage input terminal.

In some embodiments, the first switch unit, the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit, the sixth switch unit, the seventh switch unit, and the eighth switch unit are MOS transistors.

In some embodiments, the voltage reduction circuit further comprises an output capacitor;

one end of the output capacitor is connected to the voltage output end, and the other end of the output capacitor is grounded.

In some embodiments, two of the voltage reduction circuits are connected in parallel to form a two-phase voltage reduction circuit.

In a second aspect, an embodiment of the present disclosure further provides a circuit integrated chip, including any one of the voltage dropping circuits provided in the first aspect.

In some embodiments, the circuit integrated chip further integrates a receiving chip rectifier bridge circuit and a receiving chip voltage stabilizing circuit; the receiving chip rectifier bridge circuit, the receiving chip voltage stabilizing circuit and the voltage reducing circuit are sequentially connected;

the receiving chip rectifier bridge circuit is used for receiving an alternating current signal and outputting a direct current signal;

the receiving chip voltage stabilizing circuit is used for receiving the direct current signal and outputting the input voltage of the voltage reducing circuit.

In a third aspect, an embodiment of the present disclosure further provides a charging circuit, including any one of the circuit integrated chips provided in the second aspect.

In some embodiments, the charging circuit further comprises a receiving coil;

the receiving coil is arranged to receive a current signal transmitted by an external power supply and transmit the current signal to the circuit integrated chip.

In a fourth aspect, the disclosed embodiments also provide a terminal device, including any one of the charging circuits provided in the third aspect.

Compared with the prior art, the technical scheme provided by the disclosure has the following advantages:

the voltage reduction circuit provided by the embodiment of the disclosure comprises a first energy storage unit, a second energy storage unit, a third energy storage unit, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a seventh switch unit and an eighth switch unit. Therefore, in the voltage reduction circuit, the first energy storage unit, the second energy storage unit and the third energy storage unit are arranged to store preset electric quantity respectively, each switch unit performs charging and discharging combined control on the energy storage units to realize that the voltage reduction circuit performs periodic work, the 1/4 with the output voltage as the input voltage can be realized through the voltage reduction circuit, the charging efficiency is improved, and meanwhile, the input current can be reduced, the coil heating is reduced, and the high-power charging is realized. In addition, 1/4 with the output voltage being the input voltage can be realized by arranging one voltage reduction circuit, two 1/2 voltage reduction circuits can be avoided, and therefore, cost reduction, optimization of the use space of a circuit board and reduction of the complexity of software control logic are facilitated by arranging one 1/4 voltage reduction circuit to replace two 1/2 voltage reduction circuits.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a schematic structural diagram of a first voltage-reducing circuit according to an embodiment of the disclosure;

fig. 2 is a schematic structural diagram of a second voltage reduction circuit provided in the embodiment of the present disclosure;

fig. 3 is an equivalent circuit schematic diagram of a first voltage-reducing circuit provided in the embodiment of the present disclosure;

fig. 4 is an equivalent circuit schematic diagram of a second voltage-reducing circuit provided in the embodiment of the present disclosure;

fig. 5 is an equivalent circuit schematic diagram of a third voltage-reducing circuit provided in the embodiment of the disclosure;

fig. 6 is an equivalent circuit schematic diagram of a fourth voltage reduction circuit provided in the embodiment of the present disclosure;

fig. 7 is an equivalent circuit schematic diagram of a fifth voltage reduction circuit provided in the embodiment of the present disclosure;

fig. 8 is an equivalent circuit schematic diagram of a sixth voltage-reducing circuit provided in the embodiment of the present disclosure;

fig. 9 is an equivalent circuit schematic diagram of a seventh voltage-reducing circuit provided in the embodiment of the disclosure;

fig. 10 is a schematic structural diagram of a third voltage reduction circuit provided in the embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of a circuit integrated chip according to an embodiment of the disclosure;

fig. 12 is a schematic structural diagram of a charging circuit according to an embodiment of the disclosure.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.

The voltage reduction circuit provided by the embodiment of the disclosure can realize that the output voltage of the voltage output end is 1/4 of the input voltage of the voltage input end, and can reduce the input current, reduce the coil heating and realize high-power charging while realizing the improvement of the charging efficiency. In addition, 1/4 with the output voltage as the input voltage can be realized by arranging one voltage reduction circuit, two 1/2 voltage reduction circuits can be avoided, and thus, cost reduction, optimization of the use space of a circuit board and reduction of the complexity of software control logic are facilitated by arranging one 1/4 voltage reduction circuit to replace two 1/2 voltage reduction circuits.

The voltage reduction circuit, the circuit integrated chip, the charging circuit and the terminal device provided by the embodiment of the disclosure are exemplarily described below with reference to the drawings.

Fig. 1 is a schematic structural diagram of a first voltage reduction circuit provided in the embodiment of the present disclosure. As shown in fig. 1, the voltage-reducing circuit includes a first energy storage unit 21, a second energy storage unit 22, a third energy storage unit 23, a first switching unit 01, a second switching unit 02, a third switching unit 03, a fourth switching unit 04, a fifth switching unit 05, a sixth switching unit 06, a seventh switching unit 07, and an eighth switching unit 08;

the first switch unit 01, the second switch unit 02, the third switch unit 03, the fourth switch unit 04, the fifth switch unit 05 and the sixth switch unit 06 are connected in series, and the first switch unit 01 is connected with a voltage input end; the seventh switching unit 07 and the eighth switching unit 08 are connected in series, and the seventh switching unit 07 is connected to the voltage output terminal and between the fourth switching unit 04 and the fifth switching unit 05; one end of the first energy storage unit 21 is connected between the first switch unit 01 and the second switch unit 02, the other end is connected with one end of the third energy storage unit 23, and the seventh switch unit 07 and the eighth switch unit 08 are connected; the other end of the third energy storage unit 23 is connected between the third switching unit 03 and the fourth switching unit 04, one end of the second energy storage unit 22 is connected between the second switching unit 02 and the third switching unit 03, and the other end is connected between the fifth switching unit 05 and the sixth switching unit 06; the sixth switching unit 06 and the eighth switching unit 08 are grounded, respectively;

the voltage-reducing circuit periodically operates, and

in each working cycle, in the first half cycle, the first switching unit 01, the third switching unit 03, the sixth switching unit 06 and the seventh switching unit 07 are turned on, the second switching unit 02, the fourth switching unit 04, the fifth switching unit 05 and the eighth switching unit 08 are turned off, in the second half cycle, the second switching unit 02, the fourth switching unit 04, the fifth switching unit 05 and the eighth switching unit 08 are turned on, and the first switching unit 01, the third switching unit 03, the sixth switching unit 06 and the seventh switching unit 07 are turned off;

the first energy storage unit 21, the second energy storage unit 22 and the third energy storage unit 23 are respectively configured to store a predetermined amount of electricity, so that the output voltage VOUT of the voltage output terminal is 1/4 of the input voltage Vin of the voltage input terminal.

Specifically, before the voltage-reducing circuit periodically operates, a control unit (not shown in the figure) in the voltage-reducing circuit starts soft start, wherein the soft start comprises three stages (a first stage, a second stage and a third stage).

Specifically, fig. 2 is a schematic structural diagram of a second voltage reduction circuit provided in the embodiment of the present disclosure. With reference to fig. 1 and fig. 2, in the first stage of soft start, the fourth switching unit 04 and the eighth switching unit 08 are turned on, and can charge the third energy storage unit 23 to the voltage across them as the output voltage Vout, and the equivalent circuit diagram is shown in fig. 3; the third switching unit 03, the fourth switching unit 04, and the sixth switching unit 06 are turned on, and can charge the second energy storage unit 22 to the voltage at both ends, which is the output voltage Vout, and the equivalent circuit diagram is shown in fig. 4; the second switching unit 02, the third switching unit 03, the fourth switching unit 04, and the eighth switching unit 08 are turned on, and the first energy storage unit 21 can be charged to have a voltage across them as an output voltage Vout, and an equivalent circuit diagram is shown in fig. 5.

With continuing reference to fig. 1 and fig. 2, when the second stage of the soft start is performed, the second switching unit 02, the third switching unit 03, the seventh switching unit 07 and the eighth switching unit 08 are turned on, and since the third energy storage unit 23 is charged to the voltage at two ends being the output voltage Vout in the first stage, the first energy storage unit 21 can be charged to the voltage at two ends being twice the output voltage Vout, that is, 2Vout, and the equivalent circuit diagram is shown in fig. 6; the third switching unit 03, the sixth switching unit 06, and the seventh switching unit 07 are turned on, and at this time, the second energy storage unit 22 can be charged to a voltage 2Vout, which is twice the output voltage Vout, at both ends, and the equivalent circuit diagram is shown in fig. 7.

With reference to fig. 1 and fig. 2, during the third stage of the soft start, the second switching unit 02, the fifth switching unit 05 and the eighth switching unit 08 are turned on, and since the second energy storage unit 22 is charged to have a voltage at two ends of 2Vout in the second stage, the first energy storage unit 21 can be charged to have a voltage at two ends of 3Vout, which is three times the voltage of the output voltage Vout, and the equivalent circuit diagram is shown in fig. 8.

Therefore, before the voltage reduction circuit works periodically, the first energy storage unit 21, the second energy storage unit 22 and the third energy storage unit 23 can be stored according to the preset electric quantity.

Specifically, after the voltage-reducing circuit completes the soft start, the voltage-reducing circuit starts the periodic operation, each period may be divided into the first half period T1 and the second half period T2, and the duty ratio of the first half period T1 and the second half period T2 is 50%, i.e., T1= T2.

When the step-down circuit operates in the first half period T1, the first switching unit 01, the third switching unit 03, the sixth switching unit 06, and the seventh switching unit 07 are turned on, and the second switching unit 02, the fourth switching unit 04, the fifth switching unit 05, and the eighth switching unit 08 are turned off.

With reference to fig. 1 and fig. 2, when the first switching unit 01 and the seventh switching unit are turned on, the input voltage Vin charges the first energy storage unit 21 and the battery, and the equivalent circuit diagram is shown in fig. 9; when the third switching unit 03, the sixth switching unit 06 and the seventh switching unit 07 are turned on, the second energy storage unit 22 charges the third energy storage unit 23 and the battery, and the equivalent circuit diagram can refer to fig. 7, and at this time, the equivalent circuit diagram of fig. 7 can be understood that the voltage reduction circuit is in the working cycle, and the second energy storage unit 22 charges the third energy storage unit 23 and the battery.

When the step-down circuit operates in the second half period T2, the second, fourth, fifth, and

eighth switching units

02, 04, 05, and 08 are turned on, and the first, third, sixth, and

seventh switching units

01, 03, 06, and 07 are turned off.

Referring to fig. 1 and 2, when the second switching unit 02, the fifth switching unit 05 and the eighth switching unit 08 are turned on, the first energy storage unit 21 charges the second energy storage unit 22 and the battery, and the equivalent circuit diagram of fig. 8 can be referred to, where the equivalent circuit diagram of fig. 8 can be understood that the voltage reduction circuit is in a working cycle, and the first energy storage unit 21 charges the second energy storage unit 22 and the battery. When the fourth switching unit 04 and the eighth switching unit 08 are turned on, the third energy storage unit 23 charges the battery, and the equivalent circuit diagram can refer to fig. 3, where the equivalent circuit diagram of fig. 3 can be understood that the voltage reduction circuit is in the working cycle, and the third energy storage unit 23 charges the battery.

Specifically, when the step-down circuit is in the first half period T1, referring to fig. 7, Vfly2= Vfly3+ Vout may be obtained, where Vfly1 is the voltage across the first energy storage unit 21, and Vfly3 is the voltage across the third energy storage unit 23; referring to fig. 9, Vin = Vfly1+ Vout is available. In the second half of the period T2 of the step-down circuit, with reference to fig. 3, Vfly3= Vout may be obtained; referring to fig. 8, Vfly1= Vfly2+ Vout may be obtained, where Vfly2 is the voltage across the second energy storage unit 22. In combination with the above, the voltage across the first energy storage unit 21 is 3Vout, i.e. Vfly1=3 Vout; the voltage across the second energy storing unit 22 is 2Vout, i.e. Vfly2=2 Vout; the voltage across the third energy storage unit 23 is Vout, i.e. Vfly3= Vout. In combination with Vin = Vfly1+ Vout, Vout = Vin/4 is obtained, i.e. the output voltage Vout is 1/4 of the input voltage Vin.

The voltage reduction circuit provided by the embodiment of the disclosure comprises a first energy storage unit, a second energy storage unit, a third energy storage unit, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a seventh switch unit and an eighth switch unit. Therefore, in the voltage reduction circuit, the first energy storage unit, the second energy storage unit and the third energy storage unit are respectively set to store preset electric quantity, each switch unit performs charge-discharge combined control on the energy storage units to realize that the voltage reduction circuit performs periodic work, 1/4 with output voltage as input voltage can be realized through the voltage reduction circuit, the charging efficiency is improved, and meanwhile, the input current can be reduced, the coil is reduced to generate heat and high-power charging is realized. In addition, 1/4 with the output voltage being the input voltage can be realized by arranging one voltage reduction circuit, two 1/2 voltage reduction circuits can be avoided, and therefore, cost reduction, optimization of the use space of a circuit board and reduction of the complexity of software control logic are facilitated by arranging one 1/4 voltage reduction circuit to replace two 1/2 voltage reduction circuits.

In some embodiments, with reference to fig. 1 and fig. 2, the first energy storage unit 21 includes a first capacitor CFLY1, and a voltage difference between upper and lower plates of the first capacitor CFLY1 is 3 Vin/4; the second energy storage unit 22 comprises a second capacitor CFLY2, and the voltage difference between the upper and lower plates of the second capacitor CFLY2 is 2 Vin/4; the third energy storage unit 23 includes a third capacitor CFLY3, and a voltage difference between upper and lower plates of the third capacitor CFLY3 is Vin/4.

Specifically, when the voltage reduction circuit operates in the first half period T1, with reference to fig. 2 and 9, the voltage of the upper plate of the first capacitor CFLY1 is the input voltage Vin, the voltage of the lower plate of the first capacitor CFLY1 is Vin/4, and the voltage difference between the upper and lower plates of the first capacitor CFLY1 is 3Vin/4, that is, the voltage across the first capacitor CFLY1 is 3 Vin/4. With reference to fig. 2 and fig. 7, the voltage of the upper plate of the second capacitor CFLY2 is 2Vin/4, the voltage of the lower plate of the second capacitor CFLY2 is 0, and the voltage difference between the upper plate and the lower plate of the second capacitor CFLY2 is 2Vin/4, that is, the voltage across the second capacitor CFLY2 is 2 Vin/4; the voltage of the upper plate of the third capacitor CFLY3 is 2Vin/4, the voltage of the lower plate of the third capacitor CFLY3 is Vin/4, the voltage difference between the upper and lower plates of the third capacitor CFLY3 is Vin/4, i.e. the voltage across the third capacitor CFLY2 is Vin/4.

Specifically, when the voltage reduction circuit operates in the second half period T2, with reference to fig. 2 and 8, the voltage of the upper plate of the first capacitor CFLY1 is 3Vin/4, the voltage of the lower plate of the first capacitor CFLY1 is 0, and the voltage difference between the upper and lower plates of the first capacitor CFLY1 is 3Vin/4, that is, the voltage across the first capacitor CFLY1 is 3 Vin/4; the voltage of the upper plate of the second capacitor CFLY2 is 3Vin/4, the voltage of the lower plate of the second capacitor CFLY2 is Vin/4, and the voltage difference between the upper and lower plates of the second capacitor CFLY2 is 2Vin/4, that is, the voltage across the second capacitor CFLY2 is 2 Vin/4. With reference to fig. 2 and fig. 3, the voltage of the upper plate of the third capacitor CFLY3 is Vin/4, the voltage of the lower plate of the third capacitor CFLY3 is 0, and the voltage difference between the upper and lower plates of the third capacitor CFLY3 is Vin/4, i.e. the voltage across the third capacitor CFLY2 is Vin/4.

Therefore, the voltage reduction circuit provided by the embodiment of the disclosure can realize that the output voltage Vout of the voltage reduction circuit is 1/4 of the input voltage Vin by setting the voltage difference between the upper and lower polar plates of the first capacitor to be 3Vin/4, the voltage difference between the upper and lower polar plates of the second capacitor to be 2Vin/4, and the voltage difference between the upper and lower polar plates of the third capacitor to be Vin/4.

In some embodiments, with continued reference to fig. 1 and 2, the first switch unit 01 includes a first switch Q1, the second switch unit 02 includes a second switch Q2, the third switch unit 03 includes a third switch Q3, the fourth switch unit 04 includes a fourth switch Q4, the fifth switch unit 05 includes a fifth switch Q5, the sixth switch unit 06 includes a sixth switch Q6, the seventh switch unit 07 includes a seventh switch Q7, and the eighth switch unit 08 includes an eighth switch Q8, and each of the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, the seventh switch Q7, and the eighth switch Q8 is a MOS transistor.

Specifically, the first switch Q1, the second switch Q2, the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6, the seventh switch Q7, and the eighth switch Q8 may be implemented by providing an N-channel Metal Oxide Semiconductor (NMOS) transistor or a P-channel Metal Oxide Semiconductor (PMOS) transistor.

In other embodiments, the switching unit may be configured as a switching device known to those skilled in the art, and is not limited and will not be described herein.

In some embodiments, referring to fig. 2, the voltage-reducing circuit further includes an output capacitor Cout; one end of the output capacitor Cout is connected to the voltage output terminal Vout, and the other end is grounded. Therefore, the output capacitor Cout is arranged, so that voltage ripples are reduced.

On the basis of the foregoing embodiments, fig. 10 is a schematic structural diagram of a third voltage reduction circuit provided in the embodiments of the present disclosure. As shown in fig. 10, by connecting the power input terminals of the two step-down circuits and connecting the power output terminals, a two-phase step-down circuit is formed, which is advantageous for reducing voltage ripples and loop loss, and can improve the charging efficiency of the step-down circuit.

In some embodiments, fig. 11 is a schematic structural diagram of a circuit integrated chip provided in an embodiment of the present disclosure, and the circuit integrated chip 30 includes any one of the voltage dropping circuits 33 provided in the foregoing embodiments, which has the same or similar beneficial effects, and is not repeated herein.

In some embodiments, with continued reference to fig. 11, the circuit integrated chip 30 further integrates a receive chip rectifier bridge circuit 31 and a receive chip voltage regulator circuit 32; the receiving chip rectifier bridge circuit 31, the receiving chip voltage stabilizing circuit 32 and the voltage reducing circuit 33 are connected in sequence; the receiving chip rectifier bridge circuit 31 receives the alternating current signal and outputs a direct current signal; the receiving chip voltage stabilizing circuit 32 receives the dc signal and outputs the input voltage of the voltage step-down circuit 33.

Specifically, the receiving-chip rectifier bridge circuit 31, the receiving-chip voltage-stabilizing circuit 32, and the voltage-reducing circuit 33 may be integrally provided as one chip, i.e., the circuit integrated chip 30. The receiving chip rectifier bridge circuit 31 can receive the alternating current signal and output a direct current signal to the receiving chip voltage stabilizing circuit 32; accordingly, the receiving chip voltage regulator circuit 32 receives the dc signal and outputs a voltage to the voltage step-down circuit 33; accordingly, the voltage-decreasing circuit 33 receives the output voltage and serves as an input voltage of the voltage-decreasing circuit 33. The voltage regulator circuit 32 of the receiving chip can improve the stability of the output voltage, and further improve the stability of the input voltage of the voltage reduction circuit 33.

Therefore, the receiving chip rectifier bridge circuit, the receiving chip voltage stabilizing circuit and the voltage reducing circuit are integrated into one chip, the rectifier bridge circuit chip, the voltage stabilizing circuit chip and the voltage reducing circuit chip are prevented from being separately designed, cost reduction is facilitated, the use space of the circuit board is optimized, and the complexity of software control logic is reduced.

On the basis of the above embodiment, the embodiment of the present disclosure further provides a charging circuit.

Fig. 12 is a schematic structural diagram of a charging circuit according to an embodiment of the disclosure, and as shown in fig. 12, the charging circuit 40 includes any one of the circuit integrated chips 30 provided in the foregoing embodiments, and has the same or similar beneficial effects, which are not repeated herein.

In some embodiments, with continued reference to fig. 12, the charging circuit 40 further includes a receiving coil 41; the receiving coil 41 is configured to receive a current signal transmitted from an external power source and transmit the current signal to the circuit integrated chip, so as to provide a charging power source for the charging circuit.

On the basis of the foregoing embodiments, an embodiment of the present disclosure further provides a terminal device, which includes any one of the charging circuits provided in the foregoing embodiments, and has the same or similar beneficial effects, which are not described in detail herein.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A voltage reduction circuit is characterized by comprising a first energy storage unit, a second energy storage unit, a third energy storage unit, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a seventh switch unit and an eighth switch unit;

the first switch unit, the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit and the sixth switch unit are connected in series, and one end of the first switch unit, which is far away from the second switch unit, is connected with a voltage input end; the seventh switching unit is connected in series with the eighth switching unit, and one end of the seventh switching unit, which is far away from the eighth switching unit, is connected with a voltage output end and is connected between the fourth switching unit and the fifth switching unit; one end of the first energy storage unit is connected between the first switch unit and the second switch unit, the other end of the first energy storage unit is connected with one end of the third energy storage unit, and the first energy storage unit is connected between the seventh switch unit and the eighth switch unit; the other end of the third energy storage unit is connected between the third switching unit and the fourth switching unit, one end of the second energy storage unit is connected between the second switching unit and the third switching unit, and the other end of the second energy storage unit is connected between the fifth switching unit and the sixth switching unit; the sixth switching unit and the eighth switching unit are respectively grounded;

the voltage-reducing circuit operates periodically, and

2. The voltage reduction circuit according to claim 1, wherein the first energy storage unit comprises a first capacitor, and a voltage difference between an upper plate and a lower plate of the first capacitor is 3 Vin/4;

the second energy storage unit comprises a second capacitor, and the voltage difference between an upper plate and a lower plate of the second capacitor is 2 Vin/4;

the third energy storage unit comprises a third capacitor, and the voltage difference between an upper plate and a lower plate of the third capacitor is Vin/4;

wherein Vin represents the input voltage of the voltage input terminal.

3. The buck circuit according to claim 1, wherein the first switch unit, the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit, the sixth switch unit, the seventh switch unit, and the eighth switch unit are all MOS transistors.

4. The voltage-reducing circuit according to any one of claims 1 to 3, further comprising an output capacitor;

5. The buck circuit according to claim 4, wherein two of the buck circuits are connected in parallel to form a two-phase buck circuit.

6. A circuit integrated chip comprising the voltage step-down circuit of any one of claims 1 to 5.

7. The circuit integrated chip of claim 6, further integrated with a receiving chip rectifier bridge circuit and a receiving chip voltage regulator circuit; the receiving chip rectifier bridge circuit, the receiving chip voltage stabilizing circuit and the voltage reducing circuit are sequentially connected;

8. A charging circuit comprising the circuit integrated chip of claim 6 or 7.

9. The charging circuit of claim 8, further comprising a receiving coil;

10. A terminal device, characterized in that it comprises a charging circuit according to claim 8 or 9.