CN114664945A - FET device and method for forming FET device - Google Patents

FET device and method for forming FET device Download PDF

Info

Publication number
CN114664945A
CN114664945A CN202111525961.0A CN202111525961A CN114664945A CN 114664945 A CN114664945 A CN 114664945A CN 202111525961 A CN202111525961 A CN 202111525961A CN 114664945 A CN114664945 A CN 114664945A
Authority
CN
China
Prior art keywords
drain
source
layer
gate
tines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111525961.0A
Other languages
Chinese (zh)
Inventor
朱利安·瑞克特
直人堀口
曾文德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Interuniversitair Microelektronica Centrum vzw IMEC
Original Assignee
Interuniversitair Microelektronica Centrum vzw IMEC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Interuniversitair Microelektronica Centrum vzw IMEC filed Critical Interuniversitair Microelektronica Centrum vzw IMEC
Publication of CN114664945A publication Critical patent/CN114664945A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

According to one aspect, a FET device is provided. The FET device includes a common source body portion and a set of source layer tines protruding therefrom in a first lateral direction. A first dielectric layer portion is disposed in the space between the source layer tines. The device also includes a common drain body portion and a set of drain layer tines projecting in a first lateral direction. A second dielectric layer portion is disposed in the space between the drain layer tines. The device also includes a gate body including a common gate body portion and a set of gate tines projecting therefrom in a second lateral direction opposite the first lateral direction. Each gate tine is formed between a respective pair of first and second dielectric layer portions. The device further includes a channel region including a set of channel layer portions. Each channel layer portion extends between a respective pair of source and drain layer tines. These channel layer portions are disposed in the spaces between the gate tines. A method for forming a FET device is also provided.

Description

FET device and method for forming FET device
Technical Field
The present inventive concept relates to a Field Effect Transistor (FET) device and a method for forming a FET device.
Background
Moore's law states that the footprint of a transistor scales 2 times every 2 years, i.e., the gate length L of the transistor scales √ 2 times, which has been the impetus of the electronics industry to scale the length of the transistor to the limit. Today, the minimum distance between the gates of two subsequent transistors, a measure known as Contact Poly Pitch (CPP) or gate pitch (CGP), has been scaled to about 50 nm. Device parameters that limit further CPP scaling include gate length, source/drain contact area, and gate spacer width.
Disclosure of Invention
It is an object of the present inventive concept to enable further CPP scaling. Additional and alternative objects will be understood from the following.
According to an aspect of the inventive concept, there is provided a Field Effect Transistor (FET) device. The FET device includes a source region including a common source body portion and a set of vertically spaced apart source layer tines (prong) projecting from the common source body portion in a first lateral direction. A first dielectric layer portion is disposed in the space between the source layer tines. The device further includes a drain region including a common drain body portion and a set of vertically spaced apart drain layer tines protruding from the common drain body portion in a first lateral direction. A second dielectric layer portion is disposed in the space between the drain layer tines. The device further includes a gate body including a common gate body portion and a set of vertically spaced apart gate tines projecting from the common gate body portion in a second lateral direction opposite the first lateral direction. Each gate tine is formed between a respective pair of first and second dielectric layer portions. The device further includes a channel region located between the source region and the drain region and including a set of vertically spaced apart channel layer portions. Each channel layer portion extends between a respective pair of source and drain layer tines. These channel layer portions are disposed in the spaces between the gate tines.
In accordance with a device aspect of the invention, the common gate body portion may be laterally offset relative to both the common source body portion and the common drain body portion, while the gate tines may be vertically offset relative to the source layer tines and the drain layer tines. The gate body and the source/drain regions may thus be arranged without any mutual overlap. This allows the use of thinner gate spacers (spacers), or even the complete omission of gate spacers, which occurs twice in the CPP of conventional FET devices.
The source layer tines and drain layer tines protrude in a lateral direction opposite the gate tines. Accordingly, the common source and drain body portions and the common gate body portion may be arranged on opposite sides of a vertical geometrical plane extending through the source, channel and drain regions (i.e. laterally offset).
The channel layer portions extend between a respective pair of source and drain layer tines and are disposed in the space between the gate tines. At the same time, each gate tine is formed between a respective pair of the first dielectric layer portion and the second dielectric layer portion.
The gate tines may thus be arranged on a different level (i.e., vertically offset) than the source and drain layer tines and the channel layer portion. In other words, the device may include an alternating arrangement of first device levels and second device levels, wherein a pair of dielectric layer portions and one gate tine are disposed in each first device level, and wherein a pair of source and drain layer tines and channel layer portions are disposed in each second device level.
As used herein, the term "lateral" is used to denote an orientation or direction in a horizontal plane, i.e. parallel to the substrate (main extension plane) of the FET device.
The term "vertical" is used to denote an orientation or direction perpendicular to the lateral direction, i.e. perpendicular/normal to the substrate (main extension plane) of the FET device.
Accordingly, the channel layer portion may extend in a horizontal direction perpendicular to the first and second lateral/horizontal directions between the source region and the drain region. This direction may also be referred to as a third lateral or longitudinal direction of the channel layer (or the shorter "channel direction").
The source layer tines and the drain layer tines may each comprise a semiconductor material. The source layer tines and drain layer tines may be epitaxial/epitaxially grown semiconductor source layer tines and drain layer tines.
As used herein, the term "source layer tine/drain layer tine" refers to a portion (e.g., a layer) of the source/drain body that projects laterally from the common source/drain body portion to the respective free end. The term "gate tine" correspondingly refers to a (e.g., laminar) portion of the gate body that projects laterally from the common gate body portion to the respective free end.
According to an embodiment, the common source body portion and the common drain body portion may each comprise a semiconductor material. The common source body portion may be an epitaxial/epitaxially grown semiconductor body portion. The common drain body portion may be an epitaxial/epitaxially grown semiconductor body portion.
According to an embodiment, the common source body portion and the common drain body portion may alternatively each comprise a metal. The common source body portion and the common drain body portion may each be a metal body portion.
The common source body portion and the common drain body portion may each incorporate source layer tines and drain layer tines, respectively.
The common source body portion and the common drain body portion may form wrap-around contacts.
According to an embodiment, a distance between the common gate body portion and the common source and drain body portions along the second lateral direction may correspond to at least one length of each of the gate tines and each of the source and drain layer tines. In other words, the lateral/horizontal distance between the common gate body and the common source body portion and the common drain body portion along the second lateral direction may meet or exceed the length of the gate tines and the source layer tines/drain layer tines. This ensures, on the one hand, that there is no lateral overlap between the gate tines and the common source and drain body portions, and, on the other hand, that there is no lateral overlap between the source and drain layer tines and the common gate body portion.
According to an embodiment, the common source body portion and the common drain body portion may each comprise a wide portion and a narrow portion arranged between the wide portion and the source layer and drain layer tines, respectively, wherein a lateral (horizontal) dimension of the wide portion exceeds a lateral (horizontal) dimension of the narrow portion. The term "lateral dimension" herein refers to the width dimension (i.e., along the channel direction) of the common source/drain body portions. Thus, the width of the common source body portion and the common drain body portion may be increased in a region away from the line of sight of the channel layer portion. This may help to contact the source and drain bodies and allow for reduced source/drain access resistance. Due to the aforementioned mutually opposing arrangement of the common source/drain body portion and the common gate body portion, a respective wide portion is allowed. The wide portions of the common source and drain body portions may have respective width dimensions such that the distance between the wide portions is less than the width dimension of the gate body (i.e. also along the channel direction).
According to a further aspect, there is provided an apparatus having first and second FET devices, each FET device having a design according to the FET device described above. The first FET device and the second FET device may be arranged side-by-side with each other (e.g., on a substrate). The gate body of the first FET device and the gate body of the second FET may share a common gate body portion disposed between the channel region of the first FET and the channel region of the second FET. The gate tines of the first FET and the second FET may protrude in opposite lateral directions from a shared common gate body portion.
This enables the two FET devices to be combined in an area efficient manner in a shared gate configuration. Such a configuration may be useful for combining FET devices having complementary channel types (i.e., to form a CMOS device). Accordingly, the first FET device may be an n-type FET and the second FET device may be a p-type FET.
According to a further aspect of the inventive concept, there is provided a method for forming a FET device. The method includes forming a fin structure including a stack of dielectric layers and channel layers alternating with the dielectric layers. The method includes forming a source trench and a drain trench beside the fin structure at a first side of the fin structure, the source trench and the drain trench exposing respective sidewall portions of the fin structure. The method comprises the following steps: the channel layers are etched from the source trenches to remove a portion of each channel layer within the first region and the channel layers are etched from the drain trenches to remove a portion of each channel layer within the second region, thereby forming a set of source cavities in the first region and a set of drain cavities in the second region, wherein a set of channel layer portions remain in the third region between the first region and the second region. The method comprises the following steps: epitaxially growing source material in the source cavities to form source layer tines within each source cavity in contact with ends of the respective channel layer portions exposed in the source cavity and to form a common source body portion in the source trench; and epitaxially growing drain material in the drain cavities to form drain layer tines within each drain cavity in contact with ends of the respective channel layer portions exposed in the drain cavity and to form a common drain body portion in the drain trench.
The method further includes forming a gate trench beside the set of channel layer portions, the gate trench exposing the set of channel layer portions and corresponding sidewall portions of the dielectric layer along the third region. The dielectric layers are etched from the gate trenches to remove a portion of each dielectric layer within the third region, thereby forming a set of gate cavities in the third region. A gate body is formed that includes a set of gate tines in a gate cavity and a common gate portion in a gate trench.
This method allows the formation of FET devices that provide the advantages discussed in connection with the above-described device aspects.
Forming a source trench and a drain trench beside the fin structure at a first side and a gate trench beside the fin structure at a second, opposite side facilitates forming a common source body portion and a common drain body portion and a gate body portion at opposite sides. That is, the source trench and the drain trench may be formed selectively/only at the first side of the fin structure, and the gate trench may be formed selectively/only at the second side of the fin structure.
The source trench and the drain trench allow access to and selective etching of the channel layer. The channel layer may thus be selectively removed relative to the dielectric layer within the first and second regions, respectively. Source material may then be epitaxially grown to form source layer tines that are vertically spaced apart by (portions of) the dielectric layer remaining in the first region. Correspondingly, drain material may be epitaxially grown to form drain layer tines that are vertically spaced apart by (portions of) the dielectric layer remaining in the second region.
Etching the channel layer may include etching back the channel layer laterally from the source trench and the drain trench. The channel layer may be laterally etched back such that the source and drain cavities extend completely through the fin structure (i.e., from the first side to the second side of the fin structure). The channel layer may be etched using an isotropic etching process. This may facilitate lateral etch back.
The gate trench allows access to and selective etching of the dielectric layer. The dielectric layer can thus be removed selectively in the third region with respect to the channel layer portion. Thus, a gate cavity can be formed that exposes the upper and lower surfaces of the set of channel layer portions.
Etching the dielectric layer may include etching back the dielectric layer laterally from the gate trench. The dielectric layer may be laterally etched back such that the gate cavity extends completely through the fin structure (i.e., from the second side to the first side of the fin structure). The dielectric layer may be etched using an isotropic etch process. This may facilitate lateral etch back.
It should be understood that the expression "forming a trench" means forming a hole in the material deposited beside the fin structure (at the first side when referring to the source and drain trenches, or at the second side when referring to the gate trench).
The fin structure may be surrounded by an insulating material. A source trench and a drain trench may be formed in the insulating material at the first side of the fin structure. A gate trench may be formed in the insulating material at the second side of the fin structure.
The channel layer may be formed of a Si-containing material. The channel layer may be formed of a Si layer or a SiGe layer.
The dielectric layer may include an oxide material or a nitride material. The dielectric layer may be formed of SiGeOx, SiO2, SiN or (low-k) SiCO.
According to an embodiment, forming the common source body portion and the common drain body portion may further comprise growing source material and drain material on the source layer prong and the drain layer prong, respectively, such that the source material merges in the source trench and the drain material merges in the drain trench. The common source body portion and the common drain body portion may thus be formed as a merged epitaxial semiconductor body.
According to an embodiment, forming the common source body portion and the common drain body portion may alternatively comprise depositing metal in the source trench and the drain trench, the metal being in contact with the source layer tines and the drain layer tines, respectively. Epitaxial growth of the source and drain material can thus be stopped before the merging of the source layer tines and the merging of the drain layer tines. The respective common body portions may then be provided by depositing metal in the source and drain trenches, respectively.
According to an embodiment, the method may further comprise: prior to forming the source and drain trenches, an ion implantation process is performed on the fin structure in the first and second regions while the fin structure is masked in the third region. Accordingly, dopants may be selectively introduced into the channel layer and the dielectric layer in the first and second regions. The etch rate may depend on the doping level of the material exposed to the etchant. Accordingly, the ion implantation process allows for the introduction of varying etch characteristics along the length of the fin structure.
After the ion implantation process, the channel layer may thus have an increased dopant concentration in the first and second regions compared to the dopant concentration in the channel layer in the third region. Correspondingly, the dielectric layer may have an increased dopant concentration in the first and second regions compared to the dopant concentration of the dielectric layer in the third region.
Etching the channel layer from the source trench and the drain trench may include selectively etching the doped portions of the channel layer in the first region and the second region. Accordingly, these doped portions may be etched at a greater rate than the dielectric layers in the first and second regions, and at a greater rate than the channel layer portions in the third region (i.e., having a lower doping concentration).
Etching the dielectric layer from the gate trench may include selectively etching a masked portion of the dielectric layer in the third region (i.e., a portion of the dielectric layer that was masked during the ion implantation process). Thus, the mask portions of the dielectric layer (i.e., having a lower doping concentration) may be etched at a greater rate than the dielectric layer in the first and second regions, and at a greater rate than the channel layer portions in the third region (i.e., having a lower doping concentration).
According to an embodiment, the method may further include forming a preliminary fin structure including a stack of process layers and channel layers alternating with the process layers, wherein the process layers are formed of a different semiconductor material than the channel layers, and the method includes selectively removing the process layers to form gaps in the preliminary fin structure, and filling the gaps with a dielectric material to form a dielectric layer. This allows the formation of a preliminary fin structure comprising a stack of semiconductor layers (advantageously epitaxial layers) using prior art nanosheet FET process techniques, and the subsequent conversion of the semiconductor material of the process layers into a dielectric material, thereby providing increased etch selectivity for subsequent process steps.
The channel layer and the process layer may be formed of different Si-containing materials. The process layer may be formed of a Si-containing material having a Ge content greater than the channel layer. The dielectric material may be an oxide material or a nitride material. The dielectric layer can be made of SiGeOx, SiO2SiN or (low k) SiCO.
According to an embodiment, the method may further include forming a preliminary fin structure including a stack of process layers and channel layers alternating with the process layers, wherein the process layers are formed of a different semiconductor material than the channel layers, and converting the process layers into dielectric layers in an oxidation process. The material of the process layer may thus be selectively converted/oxidized to form a layer of dielectric (oxide) material. This provides similar advantages to those described above, however, it is less dependent on the presence of support structures to ensure structural stability of the fin structure.
The channel layer and the process layer may be formed of different Si-containing materials. The process layer may be formed of a Si-containing material having a Ge content greater than the channel layer. A larger Ge content may increase the oxidation rate, thus allowing the process layer to be selectively converted to SiGeOx without significantly affecting (lower or zero Ge content) the channel layer.
According to an embodiment, first, second, and third mask features may be formed on first, second, and third regions of the fin structure, respectively, the second mask feature having a different material than the first and third mask features. The different materials may provide different etch characteristics for the second mask feature and the first/third mask features, thus enabling selective opening of the mask features.
Accordingly, the method may comprise:
the first and second mask features are selectively opened relative to the third mask feature on the first side of the fin structure, and the source trench and the drain trench are etched from respective openings in the first and second mask features.
The method may further comprise:
the third mask feature is opened selectively relative to the first mask feature and the second mask feature on a second side of the fin structure, and the gate trench is etched from the opening in the third mask feature.
Photolithography and etching may be used to form the openings.
The fin structure may include a capping layer overlying the stack of the dielectric layer and the channel layer, wherein forming each of the source, drain, and gate trenches includes using the capping layer as an etch mask. This facilitates the formation of source/drain/gate trenches along both sides of the fin structure without causing undesirable etching of the fin structure.
The openings in the first mask feature and in the third mask feature may, for example, be formed to overlap a portion (from the first side) of the capping layer, wherein the source trench and the drain trench may be self-aligned relative to the first side of the fin structure. Correspondingly, the opening in the second mask feature may be formed to overlap the capping layer (from the second side), wherein the gate trench may be self-aligned with respect to the first side of the fin structure.
Drawings
The above and additional objects, features and advantages of the present inventive concept will be better understood by the following illustrative and non-limiting detailed description with reference to the accompanying drawings. In the drawings, the same reference numerals will be used for the same elements unless otherwise specified.
Fig. 1 is a perspective view of a FET device according to an embodiment.
Fig. 2a to 2d show plan views of a FET device according to further embodiments.
Fig. 3 a-3 d through 10 a-10 d illustrate method steps for forming a FET device, according to an embodiment.
Fig. 11 is a top view of an apparatus having multiple FET devices according to an embodiment.
Fig. 12 is a top view of a FET device according to further embodiments.
Detailed Description
Fig. 1 shows a FET device 100 according to an embodiment in a schematic perspective view. In fig. 1 and subsequent drawings, the X-axis represents a first horizontal direction, the Y-axis represents a second horizontal direction perpendicular to the X-axis, and the Z-axis represents a vertical direction.
FET device 100 includes a source region 20, a drain region 30, and a channel region 40 located between the source region 120 and the drain region 130.
The source region 20 includes a common source body portion 122 and a set of vertically spaced apart source layer tines 124. The source layer tines 124 protrude from the common source body portion 122 in a first lateral direction (i.e., along the X-direction). The common source body portion 122 and the source layer tines 124 together define the source body 120.
The drain region 30 includes a common drain body portion 132 and a set of vertically spaced drain layer tines 134. The drain layer tines 134 project in a first lateral direction (i.e., along the X-direction) from the common drain body portion 132. The common drain body portion 132 and the drain layer tines 134 together define the drain body 130.
The channel region 40 includes a set of vertically spaced apart channel layer portions 112. Each channel layer portion 112 extends horizontally (along second horizontal direction Y) between a respective pair of source layer tines 124 and drain layer tines 134.
Source layer tines 124 and drain layer tines 134 and channel layer portion 112 may each be formed in a nanoplate shape. By way of example, the nanoplatelets may have a width (along the X-direction) in the range of 7nm to 30nm and a thickness (along the Z-direction) in the range of 2nm to 10 nm.
The device 100 further includes a gate body 140 that includes a common gate body portion 142 and a set of vertically spaced gate tines 144. The gate tines 144 project from the common gate body portion 142 in a second lateral direction (i.e., against the X-direction) opposite the first lateral direction. Gate tine 144 extends to overlap channel layer portion 112 in the channel region 40. Channel layer portion 112 is disposed in the space between gate tines 144.
The first dielectric layer portion 126 and the second dielectric layer portion 136 are respectively arranged in the (vertical) space between the source layer tines 124 and the drain layer tines 134. Each gate tine 144 is formed (horizontally) between a respective pair of the first dielectric layer portion 126 and the second dielectric layer portion 136.
Accordingly, the device 100 may include an alternating sequence of source layer tines 124 and first dielectric layer portions 126 in the source region, an alternating sequence of drain layer tines 134 and second dielectric layer portions 136 in the drain region, and an alternating sequence of gate tines 144 and channel layer portions 112 in the channel region.
Each channel layer portion 112 may be flush with a respective pair of source layer tines 124 and drain layer tines 134. At the same time, each gate tine 144 may be flush with a respective pair of the first and second dielectric layer portions 126, 136. The gate tines 144 may thus be vertically offset relative to the source layer tines 124 and drain layer tines 134. In other words, the device 100 may include an alternating arrangement of first and second device levels, with a pair of dielectric layer portions 126, 136 and one gate tine 144 disposed in each first device level, and a pair of source layer tines 124 and one drain layer tine 134 and channel layer portion 112 disposed in each second device level.
As shown in fig. 1, the common source and drain body portions 122, 132 and the common gate body portion 142 may be arranged on opposite sides of a geometric plane P, wherein the plane P is defined as extending through the source, channel and drain regions. This design, in combination with the aforementioned vertical offset between the gate tines 144 and the source and drain layer tines 124, 134, allows for minimal overlap between the source/ drain bodies 120, 130 and the gate body 140. Thus, the need for an insulating gate spacer to ensure reliable electrical and capacitive separation between the gate body 140 and each of the source body 120 and the drain body 130 is reduced.
In the illustrated embodiment, the horizontal distance between the common gate body 142 and each of the common source and drain body portions 122, 134 along the second lateral direction (against the X direction) meets or exceeds the respective lengths of the gate tines 144 and the source/ drain layer tines 122, 132. As seen along a line of sight of the channel layer portion 112, lateral overlap between the gate tines 144 and the common source and drain body portions 122, 132, and between the source and drain layer tines 124, 134 and the common gate body portion 142 may thus be minimized. This eliminates the need for conventional gate spacers.
The channel layer portion 112 may be formed of a semiconductor, such as a Si-containing semiconductor. The channel layer portion 112 may be formed of, for example, a Si layer or a SiGe layer. However, these materials are merely examples, and it is contemplated that other semiconductors, such as Ge, may also be used.
Source layer tines 124 and drain layer tines 134 may each comprise a semiconductor material. Source layer tines 124 and drain layer tines 134 may be epitaxial semiconductor source layer tines 124 and epitaxial semiconductor drain layer tines 134. Source layer tines 124 and drain layer tines 134 may be formed on Si or SiGe channel layer portion 112, for example, from Si or SiGe. Depending on the conductivity type of the device 100, the source layer tines 124 and drain layer tines 134 (and the common source body 124 and common drain body 132, if formed of a semiconductor material) may be doped with either n-type dopants or p-type dopants.
The dielectric layer portions 126, 136 may comprise an oxide material or a nitride material. The dielectric layer can be made of SiGeOx, SiO2SiN, or (low k) SiCO.
The common source body portion 122 and the common drain body portion 132 may both comprise a semiconductor material. The common source body portion 122 and the common drain body portion 132 may be formed as respective epitaxial semiconductor body portions, e.g., made of the same material as the source layer tines 124 and the drain layer tines 134. As will be described further herein, the common source body portion 122 and the common drain body portion 132 may be formed by: the source/drain material is epitaxially grown to form source layer tines 124 and drain layer tines 134 and such epitaxy is continued so that the source/drain material merges to form respective common source body portions 122 and common drain body portions 132.
The common source and drain body portions 122, 132 may alternatively be formed as metal-containing body portions that contact and merge with the source and drain layer tines 124, 134, respectively. The body portions 122, 132 may be formed of, for example, W, Al, Ru, Mo, or Co. The body portions 122, 132 may further include a barrier metal layer, such as Ta or TaN. The common source body portion 122 and the common drain body portion 132 may be formed as wrap-around contacts, i.e., wrapped around the ends of the source and drain layer tines 124, 134, respectively.
Fig. 2 shows a FET device 200 according to a further embodiment. Fig. 2 shows the FET device 200 in a number of schematic plan views, where fig. 2a is a top view, fig. 2B shows a cross-section along a vertical plane C-C, fig. 2C shows a cross-section along a vertical plane a-a, and fig. 2d shows a cross-section along a vertical plane B-B. Thus, fig. 2b shows device 200 along a plane corresponding to plane P in fig. 1, fig. 2c shows a cross-section of device 200 in channel region 40, and fig. 2c shows a cross-section of device 200 in drain region 30. In the embodiment shown, the device 200 has a similar appearance in the source region 20 and the drain region 30, and thus fig. 2c also shows the source region 20 (with reference numerals 130, 134, 136 replaced by 120, 124, 126, respectively).
The FET device 200 generally includes features corresponding to those of the device 100, wherein like reference numerals are used to refer to like features in fig. 1 and 2. Accordingly, it is to be avoided that these correspondingly numbered features are improperly repeated.
As shown in fig. 2 b-2 d, the device 200 may be supported by the substrate 102. The substrate 102 may be a semiconductor substrate, i.e. a substrate comprising at least one semiconductor layer of a material such as Si, SiGe or Ge. The substrate 102 may be a single-layer semiconductor substrate, e.g., formed from a bulk substrate. However, multilayer/composite substrates 102 are also possible, such as an epitaxially grown semiconductor layer on a bulk substrate, or a semiconductor-on-insulator (SOI) substrate.
Channel layer portion 112, gate tines 144, source layer tines 124, drain layer tines 134, and first/second dielectric layer portion 126/136 (i.e., "device layer stack") may be arranged in a generally fin-shaped structure extending horizontally along substrate 102. The fin structure may comprise a (fin) base portion 104 protruding from the substrate 102. As shown by the similar fill pattern, the base portion 104 may be made of the same material as the substrate 102, for example.
As shown, the device layer stack and the common source body portion 120, the common drain body portion 130 and the common gate body portion 140 may be arranged in an insulating layer 106. The insulating layer 106 may surround the device 200 on either side. The insulating layer 106 may be formed of an oxide material, such as SiO2Flowable CVD oxide, or some other conventional insulating (low-k) material.
As further shown, the device 200 may include a capping layer 150 on top of the device layer stack. The capping layer 150 may be formed of a hard mask material, such as an oxide hard mask or a nitride hard mask. The capping layer 150 may be a residue of the fabrication process, wherein the capping layer 150 may be used as a hard mask during fin patterning.
Although shown as a monolithic material in fig. 1 and 2, it should be noted that the gate body 120 may include two or more layers, such as a gate dielectric layer conforming to at least the channel layer portion 112, and one or more layers of gate electrode material, such as one or more gate Work Function Metal (WFM) layers and a gate electrode fill layer, sequentially formed over the gate dielectric layer. The gate dielectric layer may be a high-k conventional gate dielectric such as HfO2LaO, AlO and ZrO. Examples of gate WFM materials include conventional n-type and p-type effect WFM metals such as TiN, TaN, TiAl, TiAlC or WCN or combinations thereof. Examples of gate fill material gates include W and Al.
Fig. 3 a-3 d through 10 a-10 d illustrate method steps for forming a FET device, such as device 100 or 200, according to an embodiment. Unless otherwise stated, the views in the following figures generally correspond to the views of fig. 2a to 2 d.
Fig. 3 a-3 d illustrate a preliminary fin structure 300' including a stack of process layers 302 and channel layers 304 alternating with the process layers 302. Fig. 4 a-4 d illustrate fin structure 300 including dielectric layer 306 in place of process layer 302, after a "conversion step" applied to preliminary fin structure 300'. The fin structure 300 thus includes a stack of alternating dielectric layers 306 and channel layers 304. The layers 302, 304, 306 may be formed as nanoplatelets.
To facilitate selective processing, the process layer 302 of the preliminary fin structure 300' is formed of a different semiconductor material than the channel layer 304. In the present embodiment, it is assumed that the channel layer 304 is a Si layer, and the process layer 302 is a SiGe layer having a Ge content of 25% or more. However, the method has more general applicability, and layers 302 and 304 may be formed of any combination of semiconductors compatible with the subsequent method steps to be described. For example, the process layer 302 and the channel layer 304 may both be formed of SiGe, but with different relative Ge contents, such as SiGe0.75Process layer 302 and SiGe0.15Channel layer 304, SiGe0.15Process layer 302 and SiGe0.75Channel layer 304, or SiGe0.5 A process layer 302 and a Ge channel layer 304, as non-limiting examples.
The stack of process layers 302 and channel layers 304 may be formed by epitaxially growing the process layers 302 and channel layers 304 alternately on top of each other, for example by Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD).
The stack of layers 302, 304 may be formed on an upper layer or thickness portion 104 of the substrate 102 (e.g., Si) and patterned into a fin structure 300'. Fin patterning may be performed in a manner known per se in the art, for example by patterning trenches in the stack of layers 302, 304 using single patterning or multiple patterning techniques using, for example, a patterned hard mask as an etch mask. The etch may extend into the substrate such that upper layer/thickness portion 104 forms a portion of fin 300 '(e.g., base portion 104 of fin 300'). A portion of the patterned hardmask may remain on top of the layer stack as an overburden 150 of the fin preliminary structure 300' (and fin structure 300).
The method may continue with "converting" the preliminary fin structure 300' "to the fin structure 300 of fig. 4 by replacing the process layer 302 with the dielectric layer 306.
According to a first conversion method, the fin structure 300 may be formed by removing the process layer 302 of the preliminary fin structure 300' by selective etching to form a gap, and then filling the gap with a dielectric material to form the dielectric layer 306. For example, the SiGe process layer 302 may be selectively removed with respect to the Si channel layer 304 using an HCl-based dry etch. However, other etching processes (e.g., wet etching processes) that allow for selective etching of SiGe relative to Si are known per se in the art and may also be used for this purpose.
The dielectric material may be an oxide material or a nitride material, such as SiO2SiN or (low k) SiCO. The dielectric material may be conformally deposited, for example, using Atomic Layer Deposition (ALD), such that the gaps are completely filled with the dielectric material. The deposition may be followed by an etching step (wet or dry, isotropic or anisotropic top-down) to remove the dielectric material deposited outside the gaps, so that the dielectric material remains in the gaps to form the dielectric layer 306.
Prior to removing these process layers 302, a support structure in the form of an insulating layer (such as STI oxide) embedding (embedding) the preliminary fin structure 300' may be deposited. The insulating layer may be etched back on one side of the preliminary fin structure 300 'to expose sidewalls thereof, allowing the process layer 302 to be exposed for etching from one side of the preliminary fin structure 300'. After the dielectric layer 306 is formed, the insulating layer may be redeposited and etched back/planarized. An alternative to the insulating layer may be to form one or more sacrificial (fin-like) structures (e.g., amorphous Si sacrificial structures) that extend across and span the preliminary fin structure. Thus, the sacrificial structure may "tie" and "suspend" the channel layer 304 when the process layer 302 is removed. After forming the dielectric layer 306 between the channel layers 304, the sacrificial structure may be removed from the fin structure 300.
According to a second conversion method, the process layer 302 may alternatively be selectively converted into the dielectric layer 306 in an oxidation process. The oxidation process may be, for example, a thermal oxidation process. The higher Ge content of the SiGe process layer 302 allows the process layer 302 to be oxidized at a greater rate than the (lower Ge content) Si channel layer 304. The process layer 302 may thus be fully oxidized and converted to a SiGeOx dielectricThe electrical layer 306 without significantly affecting the channel layer 304. For completeness, it may be noted that the oxidation process may result in the formation of a thin residual oxide layer (e.g., SiO) on the outer surface of the channel layer 3042) However, before continuing with further process steps, it can be removed with a short oxide step.
Fig. 4 a-4 d correspondingly illustrate the resulting/final fin structure 300 after any of the above-described "conversion steps". An insulating material may be deposited to form an insulating layer 106 that surrounds fin structure 300 on either side. Reference numerals 20, 30 and 40 denote "first", second and third "regions, respectively corresponding to regions in which source, drain and channel regions of the device 200 are to be formed. Therefore, the same reference numerals are used for the first, second and third regions and the source, drain and channel regions.
Converting/replacing the process layer 302 to the dielectric layer 306 can provide increased etch selectivity between layers of the fin structure 300 to facilitate subsequent process steps. To facilitate selective processing also along the length of the fin structure 300 (along the Y-direction), the fin structure 300 may further optionally be subjected to an ion implantation process such that the channel layer 304 and the dielectric layer 306 may be formed with an increased dopant concentration in the first and second regions 20, 30 as compared to the dopant concentration in the third region 40. This may be achieved by subjecting fin structure 300 to an ion implantation process in regions 20, 30 while masking fin structure 300 in third region 40. Since the etch rate may depend on the doping level of the material exposed to the etchant, the ion implantation process allows for the introduction of varying etch characteristics along the length of the fin structure 300.
The arrow "I" in fig. 4a schematically represents the ion implantation process. Dashed box 104 represents mask/mask feature 1040 that may be used as an implantation mask. Mask feature 1040 may be formed of a material or combination of materials such that it may withstand ion bombardment and thus counteract implantation of fin structure 300 in third region 40. As shown in fig. 4a, the ion acceleration may be biased in a top-down direction (negative Z-direction) such that the portion of the fin structure 300 directly below the mask feature 1040 is masked andadjacent unmasked portions are implanted. One non-limiting example of a dopant is GeH4More generally, however, any type of ion implantation that affects the etch rate in a desired manner may be used.
One or more layers of a hard mask material (e.g., a nitride-containing hard mask such as SiN or TiN or amorphous Si or a dielectric hard mask material) may be used for the mask features 1040. Mask features 1040 can be formed by patterning a hard mask layer using conventional single patterning or multiple patterning techniques. As further shown in fig. 4a, a plurality of parallel mask features 1042, 1044 may optionally be formed on the fin structure 300. The fin structure 300 may thus be masked in additional regions, which may be useful, for example, for forming multiple similar devices 200 along the length of the same fin structure 300.
In fig. 5a to 5d, a source trench 308 and a drain trench 310 have been formed in the insulating material 106 beside the fin structure at the first side of the fin structure 300. Source trenches 308 and drain trenches 310 expose respective sidewall portions of fin structure 300. Accordingly, the source trench 308 and the drain trench 310 may each expose respective portions of the dielectric layer 306 and the channel layer 304 from the first side of the fin structure 300.
As shown, source trenches 308 and drain trenches 310 may be selectively formed at a first side of the fin structure 300 to expose only a sidewall portion of the fin structure 300 facing the first side, while an immediately opposite sidewall portion remains covered by the insulating material 106.
Forming source trenches 308 and drain trenches 310 may include etching insulating layer 106 through respective openings in an etch mask. As shown in fig. 5 a-5 d, the mask features 1040 may be supplemented by mask features 1020, 1030 (dashed outline) on opposite sides of the first mask feature 1040 (dotted outline), e.g., in the gaps between mask features 1040 and 1042 and between mask features 1040 and 1044. Mask features 1020, 1030 are formed in first region 20 and second region 30, respectively, on fin structure 300. Mask features 1020, 1030, 1040 may be correspondingly referred to as first through third mask features, respectively.
The first and second mask features 1020, 1030 may be a different material than the third mask feature 1040 to enable selective opening of the mask features. The nitride containing third mask features 1040 may be supplemented with first and second mask features 1020, 1030 of amorphous Si, SOC, or SiOC, for example. The first and second mask features 1020, 1030 may be formed, for example, by etching back the deposited mask material (e.g., conformally by ALD or non-conformally by CVD or spin-on deposition) to cover and fill the gaps between the third mask features 1040, 1042, 1044 to (again) expose the third mask features 1040, 1042, 1044, wherein the first and second mask features 1020, 1030 are formed from the mask material remaining therebetween.
The first and second mask features 1020, 1030 may then be opened selectively relative to the third mask feature 1040 on the first side of the fin structure 300 by employing an etch that is selective to the material of the mask features 1020, 1030 (e.g., etching amorphous Si, SOC, or SiOC at a greater rate than SiN or TiN).
Photolithography and etching may be used to open the first and second mask features 1020, 1030. Source trenches 308 and drain trenches 310 may then be etched in insulating material 106 through the openings so formed in first mask feature 20 and second mask feature 30.
Since the first and second mask features 1020, 1030 are formed of a different material than the one or more third mask features 1040, the first and second mask features 1020, 1030 may be opened using an etch mask having an opening with a relaxed critical dimension (i.e., CD/width as viewed along the Y direction). This is illustrated in fig. 5a by the dashed outline boxes 1022, 1032, indicating the opening of relaxed CDs in the etch mask for opening the first and second mask features 1020, 1030. Because the first and second mask features 1020, 1030 are selectively etchable relative to the one or more third mask features 1040, the opening of the third mask features 1040 from the openings 1020, 1030 may be offset.
As further shown, the openings 1022, 1032 may extend to overlap a portion of the fin structure 300 at the first side, more particularly the capping layer 150. By etching the insulating material 106 selectively (also) with respect to the capping layer 150, the source trench 308 and the drain trench 310 may thus be self-aligned to the first side of the fin structure 300.
The source trench 308 and the drain trench 310 allow the channel layer 304 to be accessed and selectively etched relative to the dielectric layer 306 in the first region 20 and the second region 30. This is illustrated in fig. 6 a-6 d, where the channel layer 304 has been etched from the source trench 308 and the drain trench 310 such that a portion of each channel layer 304 has been removed within the first region 20 and the second region 30. A set of source cavities 312 and drain cavities 314 may thus be formed in the first region 20 and the second region 30, respectively. A portion of each channel layer 304 remains while a set of channel layer portions 112 is formed in the third region 40.
To facilitate understanding, the capping layer 150 and the dielectric layer 306 have been omitted from fig. 6a to provide a top view of the fin structure 300 at the level of the channel layer 304. In addition, mask features 1020, 1030, 1040, etc. have been omitted for clarity of illustration. However, mask features may be present during the formation of the source and drain cavities.
Sidewall portions of the channel layer 304 exposed in the source trench 308 and the drain trench 310 may be laterally etched back (along the X direction) from the source trench 308 and the drain trench 310. As shown in fig. 6a and 6d, the channel layers 308, 310 may be etched back such that the source cavity 312 and the drain cavity 314 extend completely through the fin structure 300 (i.e., from the first side to the second side). The channel layer may be etched using a suitable (wet or dry) isotropic etch process, based on TMAH (tetramethylammonium hydroxide) or Cl2HCl, HBr are a few non-limiting examples.
Due to the isotropic nature of the etching process, the source cavity 312 and the drain cavity 314 may result in the formation of a cavity having a curved/rounded shape. Furthermore, if no precautionary measures are taken, the etch may extend into the portion of the channel layer 304 located in the third region 40. However, the above-described doping of the channel layer 304 in the first and second regions 20, 30 may mitigate the risk of overetching into the third region 40 by introducing an etch selectivity between the first and second regions 20, 30 and the channel layer portion in the third region 40. Accordingly, the doped channel layer portions in the first and second regions 20 and 30 may be etched at a greater rate than the channel layer portions in the third region 40 (i.e., having a lower doping concentration). As shown in fig. 6a, the cavity etch may thus be at least substantially confined to the first region 20 and the second region 30. Additionally or alternatively, the extension of the cavities 312, 314 along the fin structure 300 (i.e., along the Y-direction) may be controlled by reducing the width of the source trench 308 and the drain trench 310 (along the Y-direction). That is, the width of the source trench 308 and the drain trench 310 may be smaller than the (target) length (along the Y direction) of the first region 20 and the second region 30. By reducing the width, shorter portions of the channel layer 304 may be exposed in the source trench 308 and the drain trench 310, allowing for a reduction in the amount of etching along the Y-direction.
In fig. 7a to 7d, a source body 120 of the source region 20 and a drain body 130 of the drain region 30 have been formed by epitaxy of the source material and the drain material. Typically, the same semiconductor material may be used for the source and drain regions, wherein the source and drain materials may refer to the same semiconductor material, but are deposited in the source and drain regions, respectively. The source/drain material may be doped (e.g., by in-situ doping) with an n-type dopant or a p-type dopant.
By epitaxy, a (doped) source layer prong 124 may be formed in each source cavity 312 that contacts the end of the corresponding channel layer portion 112 exposed in the source cavity 312. Correspondingly, a (doped) drain layer prong 134 may be formed in each drain cavity 314 that contacts the (opposite) end of the respective channel layer portion 112 exposed in the drain cavity 314. The source layer tines 124 are vertically spaced apart by dielectric layer (portions) 306 that remain in the first region 20. Correspondingly, the source layer tines 134 are vertically spaced apart by the dielectric layer (portions) 306 remaining in the second region 30.
As shown, the epitaxy may continue such that source/drain material merges in source trench 308 and drain material merges in drain trench 310. A common "merged" source body portion 122 may thus be formed in the source trench 308. A common "merged" drain body portion 132 may be formed in the drain trench 310.
In fig. 8a to 8d, a gate trench 314 has been formed in the insulating material 106 beside a set of channel layer portions 112 in the third region 40. The gate trench 314 exposes respective sidewall portions of the set of channel layer portions 112 and the dielectric layer 306 along the third region 40.
As shown, the gate trench 314 may be selectively formed at the second side of the fin structure 300 to expose only a sidewall portion of the fin structure 300 facing the second side, while an immediately opposite sidewall portion remains covered by the insulating material 106.
The gate trench 314 may be formed in a manner similar to the source trench 308 and the drain trench 310, for example, by selectively opening a third mask feature 1040 relative to the first mask feature 1020 and the second mask feature 1030 at a location on the second side of the fin structure 300. The gate trench 314 may then be etched from the thus formed opening in the third mask feature 1040.
Photolithography and etching may be used to open the third mask features 1040. Consistent with the discussion regarding the openings of the first and second mask features 1020, 1030, the openings in the third mask feature 1040 may also be formed by lithography and etching via a relaxed CD opening 1041 (dotted-dashed outline) defined in the etch mask.
Because the third mask feature 1040 is selectively etchable relative to the first and second mask features 1020, 1030, the opening of the first and second mask features 1020, 1030 from the opening 1041 may be offset.
As further shown, the opening 1041 may extend to overlap a portion of the fin structure 300 at the second side, more specifically the capping layer 150. By selectively etching the insulating material 106 relative to the capping layer 150, the gate trench 314 may thus be self-aligned with the second side of the fin structure 300.
The gate trench allows the dielectric layer 306 to be accessed and selectively etched with respect to the channel layer portion 112. This is illustrated in fig. 9a to 9d, where the dielectric layers 306 have been etched from the gate trenches 314, such that within the third region 40 a portion of each dielectric layer 306 has been removed. A set of gate cavities 316 exposing upper and lower surfaces of the set of channel layer portions 112 may thereby be formed in the third region 40. A portion of each dielectric layer 306 may remain with a set of first dielectric layer portions 126 formed in the first region/source region 20 and a set of second dielectric layer portions 136 formed in the second region/drain region 30.
To facilitate understanding, capping layer 150 has been omitted from fig. 9a to provide a top view of fin structure 300 at the level of dielectric layer 306. In addition, mask features 1020, 1030, 1040, etc. have been omitted for clarity of illustration. However, the mask features may be present during gate cavity formation.
Sidewall portions of the dielectric layer 306 exposed in the gate trenches 314 may be etched back laterally (against the X direction) from the gate trenches 314. As shown in fig. 9a and 9c, the dielectric layer 306 may be etched back such that the gate cavity 316 extends completely through the fin structure 300 (i.e., from the second side to the first side). Dielectric layer 306 may be etched using a suitable (wet or dry) isotropic etch process. For example, H can be used3PO4 or CH3F/O2The etch chemistry is to etch SiN selectively to Si, while dilute HF or C may be used4F8/O2To etch SiGeOx selectively with respect to Si.
Similar to the discussion of the etching of the source cavity 312 and the drain cavity 314, the gate cavity 316 may be formed in a curved/rounded shape as shown. Furthermore, the above-described doping of the dielectric layer 306 in the first and second regions 20, 30 may mitigate laterally overetching into the first and second regions 20, 30 by introducing an etch selectivity between the first and second regions 20, 30 and the dielectric layer portions in the third region 40. Accordingly, undoped dielectric layer portions may be etched at a greater rate than dielectric layer portions in first region 20 and second region 30 (i.e., having a greater doping concentration). The gate cavity 316 may thus be confined within the third region 40.
In fig. 10 a-10 d, a gate body 140 has been formed that includes a set of gate tines 144 in a gate cavity 316 and a common gate portion 142 in a gate trench 314 that incorporates the gate tines 144. The gate body 140 may be formed by depositing a gate material stack ("gate stack") including a gate dielectric layer, one or more gate WFM layers, and a gate electrode fill layer. These layers may be formed, for example, from any of the material examples discussed in connection with fig. 2. At least the gate dielectric layer and the one or more WFM layers may be conformally deposited, such as by ALD, to facilitate deposition within the gate cavity 316.
After the gate stack is deposited, the portion of the gate stack deposited outside the gate trench 314 may be removed by polishing (e.g., chemical mechanical polishing) and/or etch back, resulting in the final device structure 200 as shown in fig. 2 a-2 d.
The above method is based on a self-aligned technique, for example by forming the source trenches 308 and the drain trenches 310 and the gate trenches 314 in a self-aligned manner. However, techniques that do not rely on providing self-aligned first through third mask features are also possible. For example, openings (e.g., having non-relaxed CDs) for source trenches 308 and drain trenches 310 may be lithographically defined in a photoresist-based etch mask disposed on insulating layer 106. Source trenches 308 and drain trenches 310 may then be etched in insulating material 106 from the openings in the etch mask. The gate trench 314 may be formed in a corresponding manner using a separate photoresist-based etch mask.
Fig. 11 shows a schematic top view of an apparatus having first and second FET devices 1100, 2100, each having a design according to FET device 100 or 200 described above.
The first device 1100 and the second device 2100 each include respective source bodies 1120, 2120 (corresponding to the source body 120 of the device 100/200), respective drain bodies 1130, 2130 (corresponding to the drain body 130 of the device 100/200), and gate bodies 1140, 2140 (corresponding to the gate body 140 of the device 100/200). For the purpose of the present description, source body 1120, 2120, drain body 1130, 2130 and gate0The pole bodies 1140, 2140 are shown simultaneously to indicate their relative horizontal positions. However, it should be understood that their respective tines are located in different respective vertical device layers/levels.
The first device 1100 and the second device 2100 may be arranged side by side to each other (e.g. on a substrate) in a parallel manner, i.e. such that the channel directions of the devices 1100, 2100 extend in parallel (e.g. along the Y-direction). The gate body 1140 of the first device 1100 and the gate body 2140 of the second device 2100 share a common gate body portion 3142 disposed between the channel region of the first device 1100 and the channel region of the second device 2100. Thus, the gate tine 1144 of the first device 1100 and the gate tine 2144 of the second device 2100 protrude in opposite lateral directions (along the-X and + X directions, respectively) from the shared common gate body portion 3142. Correspondingly, the source tine 1124 of the device 1100 and the source tine 2124 of the device 2100 project in opposite lateral directions (along the + X and-X directions, respectively) from their respective source body portions 1122, 2122.
The apparatus may be embodied in a CMOS device, for example, where the first FET device 1100 may be an n-type FET and the second FET device may be a p-type FET 2100. The first FET device 1100 and the second FET device 2100 may, for example, form part of the same circuit cell (e.g., functional cell, logic cell) of an integrated circuit.
As shown, the apparatus/circuit unit may include a plurality of additional corresponding FET devices, such as devices 1200 and 1300 aligned with/along the same "fin track" as device 1100, and devices 2200 and 2300 aligned with/along the same "fin track" as device 2100. Devices 1100, 1200, 1300 and devices 2100, 2200, 3200 may be formed along the same respective fin structures (e.g., fin structure 300 and second parallel fin structure), for example, according to the methods described previously. Each of these further devices may include respective source bodies 1120, 1220, 1320, 2120, 2220, 2320, drain bodies 1130, 1230, 1330, 2130, 2230, 2330 and gate bodies 1140, 1240, 1340, 2140, 2240, 2340 (where corresponding features are denoted by the same reference numerals with the last two digits). As shown, the drain body 1130 of the device (e.g., 1100) may form a source body (e.g., 1220) that continues the device (e.g., 1200), thus the features 1130/1220, 1230/1320, 2130/2220, 2230/2320 have a double designation.
Fig. 12 is a schematic top view of a FET device 400 according to a further embodiment. Device 400 has generally the same design and includes the same features as device 200. However, the device 400 differs in that it comprises a source body 120 'and a drain body 130' comprising a wide portion 122a, 132a and a narrow portion 122b, 134b, respectively. The narrow portion 122b is disposed between the wide portion 122a and the source layer tines 124. The source layer tine 124 protrudes from the narrow portion 122 b. The narrow portion 132b is disposed between the wide portion 132a and the drain layer tines 134. The drain layer tines 124 protrude from the narrow portion 132 b.
As shown in FIG. 12, the wide portions 122a, 132a have a width dimension DwExceeds the width dimension D of the narrow portions 122b, 132bn. As further shown, the wide portions 122a, 132a may be formed such that the distance D between the wide portions 122a, 132asdIs smaller than the width dimension L of the gate body 140g(which may also be expressed as gate length).
The source body 120 and drain body 130' of this further embodiment may be formed using similar methods as described above, but including forming each of the source trench 308 and drain trench 310 with a wide portion and a narrow portion, the narrow portion being formed between the wide portion and the fin structure 300, wherein the lateral dimensions of the wide portion of the source/drain trenches (e.g., D £ D @)w) Lateral dimensions (e.g., D) of the narrow portions of the source/drain trenches are exceededn<Dw). Reducing the width of the narrow portions may help to limit subsequent source cavity and drain cavity etching to the first and second regions 20, 30, while the wide portions may allow for facilitating the source and drain contact scheme and allow for reducing the source/drain access resistance.
In the foregoing, the inventive concept has been described with primary reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the inventive concept, as defined by the appended claims.
For example, instead of forming the common source body portion 122 and the common drain body portion 132 as merged epitaxial bodies, the source epitaxy/drain epitaxy may be stopped after the source layer tines 124 and drain layer tines 134 are formed, and metal (e.g., W, Al or Cu) may then be deposited in the source trenches 308 and drain trenches 310, which is in contact with the source layer tines 124 and drain layer tines 134, respectively. Thus, the source body 120 and drain body 130 may be formed as a composite body of the semiconducting source layer tine 124/drain layer tine 134 and the common metal body portions 122, 132 incorporating the respective tines 124, 134.
In a further variation, instead of forming source trench 308 and drain trench 310 prior to gate trench 314, the order may be reversed such that gate trench 314 and gate body 340 may be formed prior to source trench 308 and drain trench 310.
It should also be noted that instead of applying a conversion step to the preliminary fin structure 300' to obtain the fin structure 300 including the dielectric layer 306 and the channel layer 304, a multi-layer SOI structure (e.g., Si/SiO) may be formed by2/Si/SiO2Si/.) to directly form fin structure 300.

Claims (15)

1. A field effect transistor, FET, device (100, 200), comprising:
a source region (20) comprising a common source body portion (122) and a set of vertically spaced apart source layer tines (124) protruding from the common source body portion (122) in a first lateral direction, wherein a first dielectric layer portion (126) is arranged in a space between the source layer tines (124),
a drain region (30) comprising a common drain body portion (132) and a set of vertically spaced apart drain layer tines (134) protruding in the first lateral direction from the common drain body portion (132), wherein a second dielectric layer portion (136) is arranged in a space between the drain layer tines (134),
a gate body (140) including a common gate body portion (142) and a set of vertically spaced apart gate tines (144) projecting from the common gate body portion (142) in a second lateral direction opposite the first lateral direction, each gate tine (144) being formed between a respective pair of first (126) and second (136) dielectric layer portions, and
a channel region (10) located between the source and drain regions and comprising a set of vertically spaced apart channel layer portions (112), each channel layer portion extending between a respective pair of source layer tines (124) and drain layer tines (134), wherein the channel layer portions are arranged in spaces between the gate tines (144).
2. The FET device of claim 1, wherein the common source body portion (122) and the common drain body portion (132) are both formed of a semiconductor material.
3. The FET device of claim 1, wherein the common source body portion (122) and the common drain body portion (132) are both formed of metal.
4. The FET device of any preceding claim, wherein the common source body portion and the common drain body portion each comprise a wide portion (122a, 132a) and a narrow portion (122b, 132b) arranged between the wide portion and the source layer prong (124) and the drain layer prong (134), respectively, wherein a lateral dimension of the wide portion (122a, 132a) exceeds a lateral dimension of the narrow portion (132a, 132 b).
5. An apparatus having a first FET device (1100) and a second FET device (2100) according to any of the preceding claims, the devices being arranged side-by-side with each other, wherein the gate body (1140) of the first FET device and the gate body (2140) of the second FET device share a common gate body portion (3142) arranged between the channel region of the first FET device and the channel region of the second FET device, wherein the gate tines (1144, 2144) of the first FET device and the second FET device protrude in opposite lateral directions from the shared common gate body portion.
6. A method for forming a field effect transistor device, the method comprising:
forming a fin structure (300) comprising a stack of dielectric layers (306) and channel layers (304) alternating with the dielectric layers (306);
forming a source trench (308) and a drain trench (310) beside the fin structure (300) at a first side of the fin structure, the source trench and the drain trench exposing respective sidewall portions of the fin structure (300);
etching the channel layers (304) from the source trench (308) to remove a portion of each channel layer within a first region, and etching the channel layers (304) from the drain trench (312) to remove a portion of each channel layer within a second region, forming a set of source cavities (312) in the first region and a set of drain cavities (314) in the second region, wherein a set of channel layer portions (112) remain in a third region between the first region and the second region;
epitaxially growing source material in the source cavities (312) to form source layer tines (124) within each source cavity in contact with ends of the respective channel layer portions (112) exposed in the source cavity and to form a common source body portion (122) in the source trench (308);
epitaxially growing drain material in the drain cavities (314) to form drain layer tines (134) within each drain cavity in contact with ends of the respective channel layer portions (112) exposed in the drain cavity and to form a common drain body portion (132) in the drain trench (310);
forming a gate trench (314) beside the set of channel layer portions (112), the gate trench exposing the set of channel layer portions and respective sidewall portions of the dielectric layers (306) along the third region;
etching the dielectric layers (306) from the gate trench (314) to remove a portion of each dielectric layer within the third region, thereby forming a set of gate cavities (316) in the third region; and
a gate body (140) is formed that includes a set of gate tines (144) in the gate cavities (316) and a common gate portion (142) in the gate trench (314).
7. The method of claim 6, wherein forming the common source body portion (122) and the common drain body portion (132) further comprises growing the source material and the drain material on the source layer tine (124) and the drain layer tine (134), respectively, such that the source material merges in the source trench (308) and the drain material merges in the drain trench (310).
8. The method of claim 6, wherein forming the common source body portion (122) and the common drain body portion (132) comprises depositing metal in the source trench (308) and the drain trench (310), the metal being in contact with the source layer tines (124) and the drain layer tines (134), respectively.
9. The method of any of claims 6 to 8, further comprising: prior to forming the source trench (308) and the drain trench (310), the fin structure (300) is subjected to an ion implantation process in the first and second regions while the fin structure is masked in the third region.
10. The method of claim 9, wherein etching the channel layers (304) from the source trench (308) and the drain trench (310) includes selectively etching doped portions of the channel layers in the first region and the second region.
11. The method according to any of claims 9-10, wherein etching the dielectric layers (306) from the gate trench (314) includes selectively etching mask portions of the dielectric layers in the third region.
12. The method according to any one of claims 6 to 11, further comprising forming a preliminary fin structure (300') comprising a stack of process layers (302) and channel layers (304) alternating with the process layers, wherein the process layers are formed of a different semiconductor material than the channel layers, and the method comprises selectively removing the process layers to form gaps in the preliminary fin structure, and filling the gaps with a dielectric material to form dielectric layers (306).
13. The method according to any one of claims 6 to 11, further comprising forming a preliminary fin structure (300') comprising a stack of process layers (302) and channel layers (304) alternating with the process layers, wherein the process layers are formed of a different semiconductor material than the channel layers, and the method comprises converting the process layers into dielectric layers (306) in an oxidation process.
14. The method of any of claims 6 to 13, wherein first (1020), second (1030) and third (1040) mask features are formed on first, second and third regions of the fin structure (300), respectively, the second mask feature being of a different material than the first and third mask features.
15. The method of claim 14, wherein the method comprises:
opening the first mask feature (1020) and the second mask feature (1030) selectively relative to the third mask feature (1040) on the first side of the fin structure and etching the source trench (308) and the drain trench (310) from respective openings in the first mask feature and the second mask feature, and
the third mask feature (1040) is selectively opened on a second side of the fin structure (300) relative to the first mask feature (1020) and the second mask feature (1030), and the gate trench is etched from the opening in the third mask feature.
CN202111525961.0A 2020-12-22 2021-12-14 FET device and method for forming FET device Pending CN114664945A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP20216325.9A EP4019462A1 (en) 2020-12-22 2020-12-22 A fet device and a method for forming a fet device
EP20216325.9 2020-12-22

Publications (1)

Publication Number Publication Date
CN114664945A true CN114664945A (en) 2022-06-24

Family

ID=73856712

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111525961.0A Pending CN114664945A (en) 2020-12-22 2021-12-14 FET device and method for forming FET device

Country Status (3)

Country Link
US (1) US20220199809A1 (en)
EP (1) EP4019462A1 (en)
CN (1) CN114664945A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4273929A1 (en) * 2022-05-05 2023-11-08 Imec VZW A circuit cell for a standard cell semiconductor device
EP4386841A1 (en) * 2022-12-18 2024-06-19 Imec VZW A semiconductor device structure

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111755333B (en) * 2019-03-27 2024-02-27 芯恩（青岛）集成电路有限公司 Nano-chip field effect transistor and preparation method thereof
CN111584486B (en) * 2020-05-21 2022-07-08 中国科学院微电子研究所 Semiconductor device having staggered structure, method of manufacturing the same, and electronic apparatus

Also Published As

Publication number Publication date
US20220199809A1 (en) 2022-06-23
EP4019462A1 (en) 2022-06-29

Similar Documents

Publication Publication Date Title
CN106653847B (en) Method of manufacturing self-aligned contact in semiconductor device
CN107093556B (en) Method for forming semiconductor device and semiconductor field effect transistor with n-type channel
TWI643345B (en) Tungsten gates for non-planar transistors
US9748239B2 (en) Fin-double-gated junction field effect transistor
CN107039526A (en) Semiconductor devices and its manufacture method
KR101954509B1 (en) Semiconductor device and method
KR20200050424A (en) Semiconductor device and method
EP3155643B1 (en) Vertical channel transistors fabrication process by selective subtraction of a regular grid
US9754935B2 (en) Raised metal semiconductor alloy for self-aligned middle-of-line contact
CN114664945A (en) FET device and method for forming FET device
CN113690141B (en) Method for manufacturing semiconductor device and semiconductor device
CN112563318A (en) Semiconductor device with a plurality of semiconductor chips
CN114121807A (en) Method for forming transistor structure
CN111223781A (en) Semiconductor device and method of forming the same
US20230246026A1 (en) Semiconductor device structure incorporating air gap
KR20220022042A (en) Semiconductor device and method
US20230178629A1 (en) Method for forming a fet device
US20230178630A1 (en) Method for forming a fet device
CN220233202U (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
US20230178640A1 (en) Field-effect transistor device
CN116825723A (en) Semiconductor structure and forming method thereof
CN116544114A (en) Semiconductor device and method for manufacturing the same
CN116230540A (en) Method for forming FET device
CN114203635A (en) Method for forming semiconductor device
CN116313800A (en) Method for forming semiconductor device structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination