CN114664926A - Power semiconductor device structure - Google Patents
Power semiconductor device structure Download PDFInfo
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- CN114664926A CN114664926A CN202210322652.1A CN202210322652A CN114664926A CN 114664926 A CN114664926 A CN 114664926A CN 202210322652 A CN202210322652 A CN 202210322652A CN 114664926 A CN114664926 A CN 114664926A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000002131 composite material Substances 0.000 claims abstract description 64
- 230000001413 cellular effect Effects 0.000 claims abstract description 29
- 238000010586 diagram Methods 0.000 description 16
- 239000002184 metal Substances 0.000 description 11
- 239000000758 substrate Substances 0.000 description 8
- 230000010354 integration Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
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- 230000009286 beneficial effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
The invention provides a power semiconductor device structure, which is a grooved gate power device integrating a rectifier tube and a power tube, and a cellular arrangement structure is formed on a transverse section. The layout structure of the device is arranged in various ways, including strip arrangement and regular n-edge arrangement, wherein n is more than or equal to 3, and when the strip arrangement is adopted, the arrangement structure is formed by circularly arranging power tube cells and rectifier tube cells; when regular n-edge arrangement is adopted, the unit cells are simple unit cells or composite unit cells, the arrangement mode of the simple unit cells is that a plurality of power tube unit cells surround one central rectifier tube unit cell, and the arrangement mode of the composite unit cells is that a plurality of composite unit cells are repeatedly arranged. The simple unit cell is a power tube unit cell or a rectifier tube unit cell, and the composite unit cell is a unit cell comprising a rectifier tube and a power tube. The device is integrated and miniaturized, the area of a chip is reduced, the arrangement mode of unit cells is flexible and changeable, the leakage current of the device is effectively reduced, and the device can be applied to various longitudinal groove gate devices.
Description
Technical Field
The application belongs to the technical field of semiconductor power devices and relates to a power semiconductor device structure.
Background
In the development process of the semiconductor power device, the JFET (junction field effect transistor) area of the traditional planar gate device is eliminated by introducing and optimizing the groove gate technology, the specific on-resistance of the device is greatly reduced, and meanwhile, the development of a longitudinal device is greatly promoted by applying the groove gate technology. The vertical Trench gate device, typically represented by a conventional Trench VDMOS or a split gate MOS (SGT MOS), has a relatively high power density and is often used in conjunction with a rectifier diode. The rectifier tube also develops a groove-shaped rectifier tube, is convenient for integration, miniaturization and chip area reduction, and accords with the development trend of the current integrated circuit. However, the integration of the trench type rectifier tube and the longitudinal trench device is still not common enough, and based on this, the application provides a conventional longitudinal power device of the integrated trench type rectifier tube and a layout structure thereof.
Disclosure of Invention
In view of the above-mentioned situation, the present invention aims to provide a device integrating a conventional trench power device and a rectifier and a layout structure thereof.
The technical scheme of the invention is as follows:
a power semiconductor device structure is a trench gate power device integrating a rectifier tube and a power tube, and a cellular arrangement structure is formed on a transverse section; the layout structure of the device is arranged in various ways, including strip arrangement and regular n-edge arrangement, wherein n is more than or equal to 3;
the strip-shaped arrangement structure is formed by circularly arranging power tube cells and rectifier tube cells and comprises strip-shaped cell rectifier tube grooves 1 and strip-shaped cell power tube grooves 3 on two sides of each strip-shaped cell rectifier tube groove 1, and strip-shaped cell table tops 2 are positioned between the adjacent strip-shaped cell rectifier tube grooves 1 and the strip-shaped cell power tube grooves 3;
the regular n-shaped edges are arranged, the cells are simple cells or composite cells and respectively comprise a power tube cell groove, a rectifier tube cell groove and a cell table board, each simple cell only comprises one of a power tube cell or a rectifier tube cell, and each composite cell simultaneously comprises a power tube cell and a rectifier tube cell;
the simple cells in the regular n-edge arrangement are arranged in a manner that a plurality of power tube cells surround a central rectifier tube cell;
the arrangement mode of the composite unit cells in the regular n-edge arrangement is that a plurality of composite unit cells are repeatedly arranged.
Preferably, the arrangement of simple cells in the regular n-sided polygonal arrangement is as follows: all the surrounding of one rectifier tube cell are power tube cells.
Preferably, the arrangement of simple cells in the regular n-sided polygonal arrangement is as follows: the power tube unit cells and the rectifier tube unit cells are alternately arranged in the transverse direction or the longitudinal direction.
Preferably, oxide layers are arranged between the power tube cell groove, the rectifier tube cell groove and the cell table-board.
Preferably, the strip-shaped arrangement structure is formed by circularly arranging a power tube cell and a rectifier tube cell; or the power tube unit cell group and a rectifier tube unit cell are circularly arranged, wherein one power tube unit cell group comprises more than 2 power tube unit cells.
Preferably, the regular n-polygonal composite cells are arranged in the same manner in the transverse structural cross-sectional view.
The invention has the beneficial effects that:
the power semiconductor device integrates the rectifier tube and the power tube, is favorable for integration and miniaturization, reduces the area of a chip, has various layout arrangement structures, can be selected according to design requirements, can adjust the quantity ratio of the power tube to the rectifier tube in each layout arrangement structure, effectively reduces leakage current of the device, and can be applied to various longitudinal groove grid devices.
Drawings
FIG. 1 is a schematic diagram of the arrangement of stripe-shaped unit cells of example 1.
FIG. 2 is a schematic diagram of the arrangement of the stripe-shaped unit cells of example 2.
Fig. 3 is a schematic diagram of a square cell arrangement according to embodiment 3, in which fig. 3A to 3B are schematic diagrams of a simple cell arrangement, and fig. 3C is a schematic diagram of a composite cell arrangement;
fig. 4 is a schematic diagram of a regular hexagonal cell arrangement according to example 4, wherein fig. 4A is a schematic diagram of a simple cell arrangement, and fig. 4B is a schematic diagram of a composite cell arrangement;
FIGS. 5A-5B are a first schematic cross-sectional view and a top view of the stripe-shaped cell arrangement of example 2;
FIGS. 6A-6B are a second cross-sectional view and a top view of the stripe-shaped cell arrangement of example 2;
FIGS. 7A-7B are a third schematic cross-sectional view and a top view of the stripe-shaped cell arrangement of example 2;
FIGS. 8A-8B are a fourth schematic cross-sectional view and a top view of the stripe-shaped cell arrangement of example 2;
fig. 9 is a schematic diagram of a square unit cell according to embodiment 3, in which the unit cell in fig. 9A is a composite unit cell, and the unit cell in fig. 9B is a simple unit cell;
FIGS. 10A-10B are top views of power transistor unit cells in a square simple unit cell according to embodiment 3;
FIGS. 11A to 11C are top views of the rectifier cell in the square simple cell of example 3;
FIGS. 12A-12B are schematic top view and cross-sectional views of a first square composite cell of example 3;
FIGS. 13A-13B are schematic top view and cross-sectional views of a second square composite cell of example 3;
FIGS. 14A-14B are schematic top view and cross-sectional views of a third square composite cell of example 3;
FIGS. 15A-15B are schematic top view and cross-sectional view of a fourth square composite cell of example 3;
fig. 16 is a schematic diagram of a regular hexagonal cell according to example 4, in which the cell in fig. 16A is a composite cell, and the cell in fig. 16B is a simple cell;
FIGS. 17A to 17B are plan views of power tube unit cells among the regular hexagonal simple unit cells of embodiment 4;
FIGS. 18A to 18C are plan views of a rectifier cell in a regular hexagonal simple cell according to example 4;
FIGS. 19A to 19B are schematic cross-sectional views and plan views of a first regular hexagonal composite unit cell according to example 4;
FIGS. 20A-20B are schematic cross-sectional views and top views of a second regular hexagonal composite unit cell according to example 4;
FIGS. 21A-21B are schematic cross-sectional views and top views of a third regular hexagonal composite unit cell of example 4;
FIGS. 22A-22B are schematic cross-sectional views and top views of a fourth regular hexagonal composite unit cell of example 4;
description of the reference numerals
1-bar-shaped cellular rectifier tube groove, 2-bar-shaped cellular table surface, 3-bar-shaped cellular power tube groove, 400-square cellular rectifier tube groove, 401-square cellular power tube groove, 402-square cellular table surface, 404-square composite cellular, 500-regular hexagonal cellular rectifier tube groove, 501-regular hexagonal cellular power tube groove, 502-regular hexagonal cellular table surface, 504-regular hexagonal composite cellular; 10-a first conductivity type first substrate, 11-a first conductivity type first epitaxial layer, 21-a first trench, 22-a first split gate electrode, 23-a first control gate electrode, 24-a first gate oxide layer, 25-a second gate oxide layer, 26-a second control gate electrode, 27-a first P-type well region, 28-a first heavily doped N-type source region, 29-a first heavily doped P-region, 30-a first source metal, 40-a first drain metal, 50-a first source metal contact hole, 51-a third control gate electrode, 52-a third gate oxide layer, 53-a fourth control gate electrode, 54-a fourth gate oxide layer, 55-a fifth control gate electrode, 56-a fifth gate oxide layer, 57-a second trench; 110-square composite cellular rectifier tube groove, 120-square composite cellular mesa, 130-square composite cellular tube groove, 140-square simple cellular groove, 150-square simple cellular mesa, 5-square simple cellular mesa without metal hole; 200-a first conductivity type second substrate, 210-a first conductivity type second epitaxial layer, 221-a third trench, 222-a second split gate electrode, 223-a sixth control gate electrode, 225-a seventh control gate electrode, 226-a sixth gate oxide, 227-a seventh gate oxide, 231-a second P-type well region, 232-a second heavily doped N-type source region, 233-a second heavily doped P-region, 230-a second source metal, 240-a second drain metal, 250-a second source metal contact hole, 235-an eighth control gate electrode, 236-a ninth control gate electrode, 237-a fourth trench, 238-a tenth control gate electrode, 239-an eighth gate oxide; 61-regular hexagon composite cellular rectifier tube groove, 62-regular hexagon composite cellular table surface, 63-regular hexagon composite cellular tube groove, 64-regular hexagon simple cellular tube or rectifier tube groove, 65-regular hexagon simple cellular table surface, 6-regular hexagon simple cellular table surface without metal hole.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Example 1
The embodiment provides a power semiconductor device structure, which is a trench gate power device integrating a rectifier tube and a power tube, and a cellular arrangement structure is formed on a transverse cross section; the layout structure of the device is arranged in a strip shape;
the strip-shaped arrangement structure is formed by circularly arranging power tube cells and rectifier tube cells and comprises a rectifier tube cell groove 1 and power tube cell grooves 3 on two sides of the rectifier tube cell groove 1, and a cell table top 2 is positioned between the adjacent rectifier tube cell grooves 1 and the power tube cell grooves 3;
as shown in fig. 1, the stripe arrangement structure is a power tube cell and a rectifier tube cell arranged in a circular manner.
Example 2
As shown in fig. 2, the difference from embodiment 1 is that: the power tube unit cell group and a rectifier tube unit cell are circularly arranged, and each power tube unit cell group comprises more than 2 power tube unit cells.
The number of the power tube unit cells and the number of the rectifier tube unit cells are n:1, the n power tube unit cells and one rectifier tube unit cell are arranged in a circulating mode, n is larger than or equal to 2, the number of the rectifier tube unit cells can be adjusted, but the adjustment of the number of the power tube unit cells n is more convenient.
The cross-sectional view and the top view of the present embodiment can have four structures, as shown in fig. 5-8. The power tube cell structure can be a traditional Trench MOS and SGT MOS structure, the groove type rectifier tube can have a similar Trench MOS structure and a similar SGT MOS structure, under a general condition, the depth of grooves of the power tube cell and the rectifier tube cell is consistent, so that the process flow is simplified, and different grooves can be adopted under a necessary condition.
Fig. 5B is a first cross-sectional view, as shown in fig. 5B, including a first substrate 10 of a first conductivity type, the first-conductivity-type first epitaxial layer 11 grows on a first-conductivity-type first substrate 10, 3 first grooves 21 are formed in the first-conductivity-type first epitaxial layer 11, a first separation gate electrode 22 is arranged in each first groove 21, a first control gate electrode 23 is arranged above each first separation gate electrode 22 of each power tube cell, a second control gate electrode 26 is arranged above each first separation gate electrode 22 of each rectifier tube cell, the first gate oxide 24 surrounds the first control gate electrode 23, the second gate oxide 25 surrounds the second control gate electrode 26, a first P-type well region 27 is arranged between every two adjacent first grooves 21, a first heavily-doped N-type source region 28 is arranged above each first P-type well region 27, each first heavily-doped P region 29 is located in each first P-type well region 27, and a first source metal 30 covers the surface of the whole device; FIG. 5A is a top view of FIG. 5B;
fig. 6B is a second cross-sectional view, as shown in fig. 6B, which differs from fig. 5B in that: a third control gate electrode 51 is arranged in the first groove 21 of the rectifier tube unit cell, a third gate oxide layer 52 surrounds the third control gate electrode 51, and the rest is the same; FIG. 6A is a top view of FIG. 6B;
fig. 7B is a second cross-sectional view, as shown in fig. 7B, which differs from fig. 6B in that: the groove of the rectifier tube unit cell is a second groove 57, and the depth of the second groove 57 is different from that of the first groove 21 in FIG. 6B;
fig. 8B is a second cross-sectional view, as shown in fig. 8B, which differs from fig. 7B in that: in the first trench 21 of the power transistor unit cell is a fifth control gate electrode 55, and a fifth gate oxide layer 56 surrounds the fifth control gate electrode 55.
Example 3
The embodiment provides a power semiconductor device structure, which is a trench gate power device integrating a rectifier tube and a power tube, and a cellular arrangement structure is formed on a transverse cross section; the layout structure of the device is arranged in a regular n-polygon shape; in the embodiment, n is 4;
the cells are arranged in a regular quadrangle, the cells are simple cells or composite cells and comprise power tube cell grooves, rectifier tube cell grooves and cell table tops, the simple cells only comprise one of the power tube cells or the rectifier tube cells, and the composite cells simultaneously comprise the power tube cells and the rectifier tube cells;
the simple cells are arranged in a way that a plurality of power tube cells surround a central rectifier tube cell;
the arrangement mode of the composite unit cells is that a plurality of composite unit cells are repeatedly arranged.
FIGS. 3A-3B are schematic diagrams of simple cell arrangements:
the arrangement mode of the simple cells is as follows: in fig. 3A, all the power tube cells are around one rectifier tube cell, and in fig. 3B, the power tube cells and the rectifier tube cells are alternately arranged in the horizontal or vertical direction. In the schematic diagram of simple cell arrangement, a simple cell unit is arranged in a dotted frame and comprises a square cell rectifier tube groove 400, a square cell power tube groove 401 and a square cell table top 402;
fig. 3C is a schematic diagram of the arrangement of the composite unit cells, wherein the arrangement of the composite unit cells is a repeated arrangement of a plurality of composite unit cells.
The schematic plan view of the simple cell is shown in fig. 9B, and is divided into a power tube cell and a rectifier tube cell, which includes a square simple cell mesa 150 and a square simple cell trench 140;
a top view of a power tube cell in a simple cell is shown in fig. 10, a top view of a rectifier tube cell in a simple cell is shown in fig. 11, fig. 10A is an SGT MOS structure, and fig. 10B is a Trench MOS structure; fig. 10A is the same as the cross-sectional view of the power tube unit cell in fig. 5B, and fig. 10B is the same as the cross-sectional view of the power tube unit cell in fig. 8B;
FIG. 11A is the same as the cross-sectional view of the rectifier cell in FIG. 5B, FIG. 11B is the same as the cross-sectional view of the rectifier cell in FIG. 6B, and FIG. 11C is the same as the cross-sectional view of the rectifier cell in FIG. 7B;
the composite unit cell is a unit cell integrating a power tube and a rectifier tube, as shown in fig. 9A. The arrangement mode of the composite unit cells is only one: a plurality of composite unit cells are arranged repeatedly; each individual square composite cell 404 has a rectifying effect and comprises a square composite cell rectifying tube groove 110, a square composite cell table top 120 and a square composite cell groove 130;
the composite unit cell has four structures in cross section and top view, as shown in fig. 12-15:
fig. 12B shows a cross-sectional view of the first type, which includes a first conductivity type second substrate 200, a first conductivity type second epitaxial layer 210 grown on the first conductivity type second substrate 200, a third trench 221 in the first conductivity type second epitaxial layer 210, a second split gate electrode 222 inside the third trench 221, a seventh control gate electrode 225 above the second split gate electrode 222 of the power transistor cell trench, a seventh gate oxide 227 surrounding the seventh control gate electrode 225, a sixth control gate electrode 223 above the second split gate electrode 222 of the rectifier transistor cell trench, and a sixth gate oxide 226 surrounding the sixth control gate electrode 223; a second P-type well region 231 is arranged between the adjacent third trenches 221, a second heavily doped N-type source region 232 is arranged above the second P-type well region 231, the second heavily doped P region 233 is located in the second P-type well region 231, and the second source metal 230 covers the surface of the device; FIG. 12A is a top view of FIG. 12B;
the second cross-sectional view is shown in fig. 13B, and differs from fig. 12B in that: an eighth control gate electrode 235 is arranged in the third groove 221 of the rectifier tube unit cell, and the sixth gate oxide layer 226 surrounds the eighth control gate electrode 235;
the third cross-sectional view is shown in fig. 14B, which differs from fig. 13B in that: the trench of the rectifier cell is a fourth trench 237, the depth of the fourth trench 237 is different from that of the third trench 221 in FIG. 13B,
the fourth cross-sectional view is shown in fig. 15B, which differs from fig. 14B in that: in the third trench 221 of the power transistor cell is a tenth control gate electrode 238, and the eighth gate oxide 239 surrounds the tenth control gate electrode 238.
Example 4
The embodiment provides a power semiconductor device structure, which is a trench gate power device integrating a rectifier tube and a power tube, and a cellular arrangement structure is formed on a transverse cross section; the layout structure of the device is arranged in a regular n-polygon shape; in the embodiment, n is 6;
the regular hexagon is arranged, the cells are simple cells or composite cells and comprise power tube cell grooves, rectifier tube cell grooves and cell table tops, the simple cells only comprise one of the power tube cells or the rectifier tube cells, and the composite cells simultaneously comprise the power tube cells and the rectifier tube cells;
the simple unit cells are arranged in a way that a plurality of power tube unit cells surround a central rectifier tube unit cell;
the arrangement mode of the composite unit cells is that a plurality of composite unit cells are repeatedly arranged.
The simple cells are arranged in the manner shown in fig. 4A, all the periphery of a rectifier cell is a regular hexagon cell power tube groove 501, in the simple cell arrangement diagram, a broken line frame is a simple cell unit, which comprises a regular hexagon cell rectifier tube groove 500, a regular hexagon cell power tube groove 501 and a regular hexagon cell table surface 502;
fig. 4B is a schematic diagram of the arrangement of the composite unit cell, in which the composite unit cell is arranged in a manner that a plurality of composite unit cells are repeatedly arranged.
The schematic plan view of the simple cell is shown in fig. 16B, and is divided into a power tube cell and a rectifier tube cell, which includes a regular hexagonal simple cell or a rectifier tube groove 64 and a regular hexagonal simple cell mesa 65;
fig. 17 is a plan view of a power tube unit cell in a simple unit cell, fig. 18 is a plan view of a rectifier tube unit cell in a simple unit cell, fig. 17A is the same as a cross-sectional view of the power tube unit cell in fig. 5B, and fig. 17B is the same as a cross-sectional view of the power tube unit cell in fig. 8B;
FIG. 18A is the same cross-sectional view as FIG. 5B, FIG. 18B is the same cross-sectional view as FIG. 6B, FIG. 18C is the same cross-sectional view as FIG. 7B,
the composite unit cell is a unit cell integrating a power tube and a rectifier tube, as shown in fig. 16A. The composite cell arrangement schematic diagram is that the cells are only one hexagonal composite cell 504, and each single hexagonal composite cell 504 has a rectification function and comprises a regular hexagonal composite cell rectifier tube groove 61, a regular hexagonal composite cell table surface 62 and a regular hexagonal composite cell tube groove 63;
the composite cell can have four structures in cross-section and top view, as shown in fig. 19-22:
fig. 19B shows a cross-sectional view of the first type, which includes a first conductivity type second substrate 200, a first conductivity type second epitaxial layer 210 grown on the first conductivity type second substrate 200, a third trench 221 is formed in the first conductivity type second epitaxial layer 210, a second split gate electrode 222 is disposed inside the third trench 221, a seventh control gate electrode 225 is disposed above the second split gate electrode 222 of the power transistor cell trench, the seventh gate oxide 227 surrounds the seventh control gate electrode 225, a sixth control gate electrode 223 is disposed above the second split gate electrode 222 of the rectifier transistor cell trench, and the sixth gate oxide 226 surrounds the sixth control gate electrode 223; a second P-type well region 231 is arranged between the adjacent third trenches 221, a second heavily doped N-type source region 232 is arranged above the second P-type well region 231, the second heavily doped N-type source region 233 is positioned in the second P-type well region 231, and a second source metal 230 covers the surface of the device; FIG. 19A is a top view of FIG. 19B;
the second cross-sectional view is shown in fig. 20B, and differs from fig. 19B in that: in the third trench 221 of the rectifier cell is an eighth control gate electrode 235, the ninth control gate electrode 226 surrounds the eighth control gate electrode 235,
the third cross-sectional view is shown in fig. 21B, and differs from fig. 20B in that: the trench of the rectifier cell is a fourth trench 237, and the depth of the fourth trench 237 is different from that of the third trench 221 in fig. 13B;
the fourth cross-sectional view is shown in fig. 22B, and differs from fig. 21B in that: in the third trench 221 of the power transistor cell is a tenth control gate electrode 238, an eighth gate oxide 239 surrounds the tenth control gate electrode 238,
in summary, the present application provides a power semiconductor device structure, the device is a trench gate device of an integrated rectifier, the layout structure of the device includes arrangement of bar-shaped cells, arrangement of square and regular hexagonal cells, and the like, and can be used for a vertical trench gate device.
Claims (6)
1. A power semiconductor device structure characterized by: the device is a groove grid power device integrating a rectifier tube and a power tube, and a cellular arrangement structure is formed on a transverse section; the layout structure of the device is arranged in various ways, including strip arrangement and regular n-edge arrangement, wherein n is more than or equal to 3;
the strip-shaped arrangement structure is formed by circularly arranging power tube cells and rectifier tube cells and comprises strip-shaped cell rectifier tube grooves (1) and strip-shaped cell power tube grooves (3) on two sides of each strip-shaped cell rectifier tube groove (1), and strip-shaped cell table tops (2) are positioned between the adjacent strip-shaped cell rectifier tube grooves (1) and the adjacent strip-shaped cell power tube grooves (3);
the regular n-shaped edges are arranged, the cells are simple cells or composite cells and respectively comprise a power tube cell groove, a rectifier tube cell groove and a cell table board, each simple cell only comprises one of a power tube cell or a rectifier tube cell, and each composite cell simultaneously comprises a power tube cell and a rectifier tube cell;
the simple cells in the regular n-edge arrangement are arranged in a manner that a plurality of power tube cells surround a central rectifier tube cell;
the arrangement mode of the composite unit cells in the regular n-edge arrangement is that a plurality of composite unit cells are repeatedly arranged.
2. The power semiconductor device structure of claim 1, wherein: the arrangement mode of simple cells in regular n-polygon arrangement is as follows: all the surrounding of one rectifier tube cell are power tube cells.
3. The power semiconductor device structure of claim 1, wherein: the arrangement mode of simple cells in regular n-polygon arrangement is as follows: the power tube unit cells and the rectifier tube unit cells are alternately arranged in the transverse direction or the longitudinal direction.
4. The power semiconductor device structure of claim 1, wherein: oxide layers are arranged between the power tube cell groove, the rectifier tube cell groove and the cell table surface.
5. The power semiconductor device structure of claim 1, wherein: the strip-shaped arrangement structure is formed by circularly arranging a power tube cell and a rectifier tube cell; or the power tube unit cell group and a rectifier tube unit cell are circularly arranged, wherein one power tube unit cell group comprises more than 2 power tube unit cells.
6. The power semiconductor device structure of claim 1, wherein: when the regular n-edge composite unit cells are arranged, the cross section of the transverse structure is the same.
Priority Applications (1)
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