CN114664893A

CN114664893A - Transparent display device

Info

Publication number: CN114664893A
Application number: CN202111515362.0A
Authority: CN
Inventors: 高兑熙; 朴宣荣
Original assignee: LG Display Co Ltd
Current assignee: LG Display Co Ltd
Priority date: 2020-12-23
Filing date: 2021-12-13
Publication date: 2022-06-24
Also published as: GB202117244D0; TWI798965B; TW202226203A; KR20220090837A; JP2022100254A; GB2603603B; JP7208344B2; GB2603603A; DE102021134086A1; US20220199755A1

Abstract

The transparent display device can improve transmittance in a non-display region and prevent static electricity from occurring. The transparent display device includes: a substrate having a display region on which a plurality of subpixels are disposed, a first non-display region disposed at one side of the display region, and a second non-display region disposed at the other side of the display region; a plurality of power shorting bars disposed in the first non-display area on the substrate and extending in parallel in a first direction; a plurality of power lines disposed in the display area on the substrate, extending in the second direction, and connected with the plurality of power shorting bars; a first transmission region disposed between the plurality of power lines; and a second transmission region disposed between the plurality of power shorting bars and having the same shape as the first transmission region. The plurality of shorting bars are connected to each other at least one end.

Description

Transparent display device

Technical Field

The present disclosure relates to a transparent display device.

Background

With the development of the information-oriented society, the demand for display devices that display images has increased in various forms. Recently, various types of display devices, such as Liquid Crystal Display (LCD) devices, Plasma Display Panel (PDP) devices, Organic Light Emitting Display (OLED) devices, and quantum dot light display (QLED) devices, have been widely used.

Recently, research is actively being conducted on a transparent display device that allows a user to view objects or images disposed on opposite sides of the display device via the display device.

The transparent display device includes a non-display area and a display area on which an image is displayed, wherein the display area may include a non-transmission area and a transmission area that may transmit external light. The transparent display device may have high light transmittance in the display region through the transmissive region.

A plurality of signal lines or a plurality of connection electrodes may be disposed in the non-display area. In the transparent display device, in order to reduce the resistance of the plurality of signal lines or the plurality of connection electrodes provided in the non-display region, the plurality of signal lines or the plurality of connection electrodes may be formed of a metal material having a low resistance. In this case, since a metal material having a low resistance is generally opaque, the transparent display device has a problem in that transmittance is reduced in a non-display region.

Disclosure of Invention

The present disclosure has been made in view of various technical problems including the above problems, and various embodiments of the present disclosure provide a transparent display device which may improve transmittance in a non-display region while reducing resistance of a power supply line.

Another object of the present disclosure is to provide a transparent display device that can minimize recognition of a non-display area.

Another object of the present disclosure is to provide a transparent display device which can prevent static electricity from occurring between a plurality of signal lines or a plurality of connection electrodes arranged in a non-display area.

In addition to the technical benefits of the present disclosure as described above, additional technical benefits and features of the present disclosure will become apparent to those skilled in the art from the following description of the present disclosure.

In accordance with one aspect of the present disclosure, the above and other technical benefits can be achieved by providing a transparent display apparatus including: a substrate having a display region on which a plurality of subpixels are disposed, a first non-display region disposed at one side of the display region, and a second non-display region disposed at the other side of the display region; a plurality of power shorting bars disposed in the first non-display area on the substrate and extending in parallel in a first direction; a plurality of power lines disposed in the display area on the substrate, extending in the second direction, and connected with the plurality of power shorting bars; a first transmission region disposed between the plurality of power lines; and a second transmission region disposed between the plurality of power shorting bars and having the same shape as the first transmission region. The plurality of power shorting bars are connected to each other at least one end.

In accordance with another aspect of the present disclosure, the above and other objects can be accomplished by the provision of a transparent display device comprising: a substrate having a display region on which a plurality of subpixels are disposed, a first non-display region disposed at one side of the display region, and a second non-display region disposed at the other side of the display region; a plurality of pixel power source shorting bars disposed in the first non-display region on the substrate, extending in parallel in a first direction and spaced apart from each other; the first pixel power supply connecting electrode is connected with the end parts of the plurality of pixel power supply short-circuit bars; a plurality of common power shorting bars disposed in the first non-display area on the substrate, extending in parallel in a first direction and spaced apart from each other; and a first common power supply connection electrode connected to ends of the plurality of common power supply shorting bars.

Drawings

The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

fig. 1 is a perspective view illustrating a transparent display device according to one embodiment of the present disclosure;

fig. 2 is a plan view illustrating a transparent display panel according to an embodiment of the present disclosure;

fig. 3 is an enlarged view illustrating a region a of fig. 2;

fig. 4 is a view showing an example in which a plurality of signal lines and a plurality of driving transistors are provided;

FIG. 5 is a sectional view taken along line I-I' of FIG. 4;

fig. 6 is an enlarged view illustrating a region B of fig. 2;

fig. 7 is an enlarged view showing a region C of fig. 6;

FIG. 8 is a sectional view taken along line II-II' of FIG. 7;

FIG. 9 is a sectional view taken along line III-III' of FIG. 7;

fig. 10 is a view illustrating a region D of fig. 6;

fig. 11 is a view showing a region E of fig. 6;

fig. 12 is a view showing a region F of fig. 6; and

fig. 13 is a view showing an example of disposing color filters in a display region, a first non-display region, and a second non-display region.

Detailed Description

Advantages and features of the present disclosure and methods of accomplishing the same will be set forth in the embodiments described below with reference to the accompanying drawings. This disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The shapes, sizes, ratios, angles, numbers disclosed in the drawings for describing the embodiments of the present disclosure are only examples, and thus, the present disclosure is not limited to the illustrated details. Like reference numerals refer to like elements throughout the specification. In the following description, when it is determined that a detailed description of a related known function or configuration unnecessarily obscures the gist of the present disclosure, the detailed description will be omitted. In the case of using "including", "having", and "including" described in this specification, another component may be added unless "only" is used. Terms in the singular may include the plural unless specified to the contrary.

In explaining an element, although not explicitly described, the element is also to be interpreted as including an error range.

In describing positional relationships, for example, when positional relationships are described as "over", "under" and "beside", one or more portions may be disposed between two other portions unless "exactly" or "directly" is used.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

In describing the elements of the present disclosure, the terms "first," "second," and the like may be used. These terms are intended to identify corresponding elements from other elements, and the basis, order, or number of corresponding elements is not limited by these terms. The expression that one element is "connected" or "coupled" to another element should be understood to mean that the element may be directly connected or coupled to the other element, but unless specifically mentioned otherwise, may be directly connected or coupled to the other element or a third element may be interposed between the corresponding elements.

The features of the various embodiments of the present disclosure may be partially or fully coupled or combined with each other and may be interoperated and technically driven in various ways as can be fully appreciated by those skilled in the art. Embodiments of the present disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

Hereinafter, examples of the transparent display device according to the present disclosure will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

Fig. 1 is a perspective view illustrating a transparent display device according to one embodiment of the present disclosure.

Hereinafter, the X-axis represents a line parallel to the scan line, the Y-axis represents a line parallel to the data line, and the Z-axis represents a height direction of the transparent display apparatus 100.

Although description has been made based on the transparent display device 100 according to one embodiment of the present disclosure being implemented as an organic light emitting display device, the transparent display device 100 may be implemented as a liquid crystal display device, a Plasma Display Panel (PDP), a quantum dot light display (QLED), or an electrophoretic display device.

Referring to fig. 1, a transparent display apparatus 100 according to one embodiment of the present disclosure includes a transparent display panel 110, a source driving Integrated Circuit (IC)210, a flexible film 220, a circuit board 230, and a timing controller 240.

The transparent display panel 110 includes a first substrate 111 and a second substrate 112 facing each other. The second substrate 112 may be a package substrate. The first substrate 111 may be a plastic film, a glass substrate, or a silicon wafer substrate formed using a semiconductor process. The second substrate 112 may be a plastic film, a glass substrate, or an encapsulation film. The first substrate 111 and the second substrate 112 may be made of a transparent material.

The scan driver may be disposed at one side of the display region of the transparent display panel 110 by a gate-in-panel driver (GIP) method, or in the non-display regions of both outer circumferential sides of the transparent display panel 110. In another manner, the scan driver may be fabricated in a driving chip, may be mounted on a flexible film, and may be attached to one or both outer circumferential sides of the display region of the transparent display panel 110 by a Tape Automated Bonding (TAB) method.

If the source drive ICs 210 are manufactured in a driving chip, the source drive ICs 210 may be mounted on the flexible film 220 by a Chip On Film (COF) method or a Chip On Plastic (COP) method.

Pads (e.g., power supply pads and data pads) may be disposed in the pad area PA of the transparent display panel 110. A line connecting the pad with the source driving IC 210 and a line connecting the pad with a line of the circuit board 230 may be provided in the flexible film 220. The flexible film 220 may be attached to the pad using an anisotropic conductive film, whereby the pad may be connected with the line of the flexible film 220.

Fig. 2 is a schematic plan view illustrating a transparent display panel according to an embodiment of the present disclosure, and fig. 3 is an enlarged view illustrating a region a of fig. 2. Fig. 4 is a view showing an example of providing a plurality of signal lines and a plurality of driving transistors, and fig. 5 is a sectional view taken along line I-I' of fig. 4.

Referring to fig. 2 and 5, the first substrate 111 may include a display area DA in which pixels P are disposed to display an image, and a non-display area NDA in which an image is not displayed.

The non-display area NDA may be provided with a PAD area PA in which a PAD is disposed, and at least one scan driver 205.

The scan driver 205 is connected to the scan lines scall 1 and SCANL2, and supplies scan signals to the scan lines SCANL1 and SCANL 2. The scan driver 205 may be disposed at one side of the display area DA of the transparent display panel 110 by a gate driver in panel (GIP) method, or in the non-display areas NDA of both outer peripheral sides of the transparent display panel 110. For example, as shown in fig. 2, the scan drivers 205 may be disposed at both sides of the display area DA of the transparent display panel 110, but the scan drivers are not limited thereto. The scan driver 205 may be disposed only at one side of the display area DA of the transparent display panel 110.

As shown in fig. 3, the display area DA includes first transmission areas TA1 and first non-transmission areas NTA 1. The first transmission region TA1 is a region through which most of the externally incident light passes, and the first non-transmission region NTA1 is a region through which most of the externally incident light cannot be transmitted. For example, the first transmission region TA1 may be a region having a light transmittance greater than α% (e.g., about 90%), and the first non-transmission region NTA1 may be a region having a light transmittance less than β% (e.g., about 50%). At this time, α is larger than β. Due to the first transmissive area TA1, the user can view an object or a background disposed on the rear surface of the transparent display panel 110.

The first non-transmissive region NTA1 may include a plurality of pixels P, and a plurality of first signal lines SL1 and a plurality of second signal lines SL2 to supply signals to each of the plurality of pixels P.

The plurality of first signal lines SL1 may extend in a first direction (e.g., an X-axis direction). The plurality of first signal lines SL1 may cross the plurality of second signal lines SL 2. For example, each of the plurality of first signal lines SL1 may include at least one scan line.

Hereinafter, when the first signal line SL1 includes a plurality of lines, one first signal line SL1 may refer to a signal line group including a plurality of lines. For example, when the first signal line SL1 includes two scan lines, one first signal line SL1 may refer to a signal line group including two scan lines.

The plurality of second signal lines SL2 may extend in a second direction (e.g., a Y-axis direction). For example, each of the plurality of second signal lines SL2 may include at least one of at least one data line, one pixel power line, one reference line, or one common power line.

Hereinafter, when the second signal line SL2 includes a plurality of lines, one second signal line SL2 may refer to a signal line group including a plurality of lines. For example, when the second signal line SL2 includes two data lines, one pixel power line, one common power line, and one reference line, one second signal line SL2 may refer to a signal line group including two data lines, one pixel power line, one common power line, and one reference line.

The first transmissive area TA1 may be disposed between the first signal lines SL1 adjacent to each other. Further, the first transmissive area TA1 may be disposed between the second signal lines SL2 adjacent to each other. That is, the first transmission region TA1 may be surrounded by two first signal lines SL1 and two second signal lines SL 2.

The pixels P may be disposed to overlap at least one of the first and second signal lines SL1 and SL2, thereby emitting predetermined light to display an image. The light emitting region EA may correspond to a region emitting light in the pixel P.

Each of the pixels P may include at least one of a first subpixel P1, a second subpixel P2, a third subpixel P3 and a fourth subpixel P4. The first sub-pixel P1 may include a first light emitting area EA1 emitting green light. The second sub-pixel P2 may include a second light emitting area EA2 emitting red light. The third sub-pixel P3 may include a third light emitting region EA3 emitting blue light. The fourth sub-pixel P4 may include a fourth light emitting area EA4 emitting white light. However, the light emitting region is not limited to this example. Each of the pixels P may further include sub-pixels emitting light of a color different from red, green, blue, and white. Further, the arrangement order of the sub-pixels P1, P2, P3, and P4 may be changed in various ways.

Hereinafter, for convenience of description, a description will be given based on the first subpixel P1 being a green subpixel emitting green light, the second subpixel P2 being a red subpixel emitting red light, the third subpixel P3 being a blue subpixel emitting blue light, and the fourth subpixel P4 being a white subpixel emitting white light.

The first and second subpixels P1 and P2 may be disposed to overlap at least a portion of the second signal line SL2, and may be alternately disposed along the second signal line SL 2.

The third and fourth sub-pixels P3 and P4 may be disposed to at least partially overlap the first signal line SL1, and may be alternately disposed along the first signal line SL 1.

As shown in fig. 3, the third and fourth sub-pixels P3 and P4 may be disposed in a region where the first and second signal lines SL1 and SL2 cross each other, but are not limited thereto.

In another embodiment, the first and second sub-pixels P1 and P2 may be disposed in a region where the first and second signal lines SL1 and SL2 cross each other. In this case, the third subpixel P3 and the fourth subpixel P4 may be spaced apart from each other in a region where the first signal line SL1 and the second signal line SL2 cross each other with the first subpixel P1 and the second subpixel P2 interposed therebetween.

Each of the first, second, third, and fourth sub-pixels P1, P2, P3, and P4 may include a circuit element including a capacitor, a thin film transistor, and the like, and a light emitting element. The thin film transistors may include switching transistors, sensing transistors, and driving transistors TR1, TR2, TR3, and TR 4.

The switching transistors switch in accordance with scan signals supplied to the scan lines scall 1 and scall 2 to supply data voltages supplied from the data lines DL1 and DL2 to the driving transistors TR1, TR2, TR3, and TR 4.

The sense transistors are used to sense deviations in the threshold voltages of the drive transistors TR1, TR2, TR3, and TR4, which cause deterioration in image quality.

The driving transistors TR1, TR2, TR3, and TR4 are switched according to the data voltage supplied from the switching thin film transistor to generate a data current according to the power supplied from the pixel power supply line VDDL and supply the data current to the first electrode 120 of the sub-pixel. The driving transistors TR1, TR2, TR3, and TR4 include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

The capacitor serves to hold the data voltage supplied to the driving transistors TR1, TR2, TR3, and TR4 for one frame. The capacitor may include a first capacitor electrode and a second capacitor electrode.

Specifically, the active layer ACT may be disposed on the first substrate 111. The active layer ACT may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material.

The light-shielding layer LS may be disposed between the active layer ACT and the first substrate 111. The light-shielding layer LS may function as a light-shielding layer for shielding external light entering the active layer ACT. The light-shielding layer LS may be made of a conductive material. For example, the light shielding layer LS may be formed of a single layer or a plurality of layers made of any one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu, or an alloy thereof. In this case, the buffer layer BF may be provided between the light-shielding layer LS and the active layer ACT.

A gate insulating layer GI may be provided on the active layer ACT. The gate insulating layer GI may be formed of an inorganic film such as a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a multilayer film of SiOx and SiNx.

The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may be formed of a single layer or a plurality of layers made of any one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof.

An interlayer dielectric layer ILD may be disposed on the gate electrode GE. The interlayer dielectric layer ILD may be made of an inorganic film, such as a silicon oxide film (SiOx), a silicon nitride film (SiNx), or a multi-layer film of SiOx and SiNx.

The source electrode SE and the drain electrode DE may be disposed on the interlayer dielectric ILD. The source electrode SE and the drain electrode DE may be connected to the active layer ACT through a contact hole passing through the gate insulating layer GI and the interlayer dielectric layer ILD.

The source electrode SE and the drain electrode DE may be made of a single layer or a multilayer of any one of Mo, Al, Cr, Au, Ti, Ni, Nd, and Cu or an alloy thereof.

A passivation layer PAS for protecting the driving transistor TR may be disposed on the source electrode SE and the drain electrode DE.

A planarization layer PLN for planarizing a step difference caused by the driving transistors TR1, TR2, TR3, and TR4 may be disposed on the passivation layer PAS. The planarization layer PLN may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, and a polyimide resin.

Each of the light emitting diodes including the first electrode 120, the organic emission layer 130 and the second electrode 140, and the bank 125 is disposed on the planarization layer PLN.

The first electrode 120 may be disposed on the planarization layer PLN and connected to the driving transistors TR1, TR2, TR3, and TR 4. Specifically, the first electrode 120 may be connected to the source electrode SE or the drain electrode DE of the driving transistors TR1, TR2, TR3, and TR4 through a contact hole passing through the planarization layer PLN and the passivation layer PAS. Accordingly, the first electrode 120 may be electrically connected to the driving transistors TR1, TR2, TR3, and TR 4.

The first electrode 120 may be provided for each of the sub-pixels P1, P2, P3, and P4. One first electrode 120 may be disposed in the first subpixel P1, another first electrode 120 may be disposed in the second subpixel P2, yet another first electrode 120 may be disposed in the third subpixel P3, and yet another first electrode 120 may be disposed in the fourth subpixel P4. The first electrode 120 is not disposed in the transmissive area TA.

The first electrode 120 may be formed of a high-reflectivity metal material, for example, a deposition structure of aluminum and titanium (Ti/Al/Ti), a deposition structure of aluminum and ITO (ITO/Al/ITO), a deposition structure of Ag alloy and silver alloy and ITO (ITO/Ag alloy/ITO), a deposition structure of MoTi alloy and ITO (ITO/MoTi alloy/ITO). The Ag alloy may be an alloy of silver (Ag), palladium (Pb), and copper (Cu). The MoTi alloy may be an alloy of molybdenum (Mo) and titanium (Ti). The first electrode 120 may be an anode electrode.

The bank 125 may be disposed on the planarization layer PLN. In addition, the bank 125 may be disposed between the first electrodes 120. The banks 125 may be disposed to cover or at least partially cover edges of each of the first electrodes 120 and expose a portion of each of the first electrodes 120. Accordingly, the bank 125 may prevent the luminous efficiency from being deteriorated due to the current concentrated on each end of the first electrode 120.

The bank 125 may define light emitting regions EA1, EA2, EA3, and EA4 of each of the sub-pixels P1, P2, P3, and P4. The light emitting regions EA1, EA2, EA3, and EA4 of each of the sub-pixels P1, P2, P3, and P4 refer to regions where the first electrode 120, the organic light emitting layer 130, and the second electrode 140 are sequentially deposited such that holes from the anode electrode 120 and electrons from the second electrode 140 are combined with each other in the organic light emitting layer 130 to emit light. In this case, since the region where the bank 125 is disposed does not emit light, the region may be a non-light emitting region, and the regions where the bank 125 is not disposed and the first electrode 120 is exposed may be light emitting regions EA1, EA2, EA3, and EA 4.

The bank 125 may be formed of an organic layer, for example, an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, or the like.

The organic light emitting layer 130 may be disposed on the first electrode 120. The organic light emitting layer 130 may include a hole transport layer, a light emitting layer, and an electron transport layer. In this case, if a voltage is applied to the first electrode 120 and the second electrode 140, holes and electrons move to the light emitting layer through the hole transport layer and the electron transport layer, respectively, and combine with each other in the light emitting layer to emit light.

In one embodiment, the organic light emitting layer 130 may be a common layer commonly disposed for the sub-pixels P1, P2, P3, and P4. For example, the organic light emitting layer 130 may be a white light emitting layer that emits white light.

In another embodiment, the organic light emitting layer 130 may include a light emitting layer disposed per each of the sub-pixels P1, P2, P3, and P4. For example, a green light emitting layer emitting green light may be disposed in the first subpixel P1, a red light emitting layer emitting red light may be disposed in the second subpixel P2, a blue light emitting layer emitting blue light may be disposed in the third subpixel P3, and a white light emitting layer emitting white light may be disposed in the fourth subpixel P4. In this case, the light emitting layer of the organic light emitting layer 130 is not disposed in the transmissive area TA.

The second electrode 140 may be disposed on the organic emission layer 130 and the bank 125. The second electrode 140 may be disposed in the first transmission region TA1 and the first non-transmission region NTA1 including the light emitting region EA, but is not limited thereto. The second electrode 140 may be disposed only in the first non-transmissive area NTA1 including the light emitting area EA, but may not be disposed in the first transmissive area TA1 to improve transmittance.

The second electrode 140 may be a common layer commonly disposed in the sub-pixels P1, P2, P3, and P4 to apply the same voltage. The second electrode 140 may be formed of a conductive material that can transmit light. For example, the second electrode 140 may be formed of a low-resistance metal material, such as Ag or an alloy of Mg and Ag. The second electrode 140 may be a cathode electrode.

The encapsulation layer 150 may be disposed on the light emitting diode. The encapsulation layer 150 may be disposed on the second electrode 140 to cover the second electrode 140. The encapsulation layer 150 serves to prevent oxygen or water from penetrating into the organic emission layer 130 and the second electrode 140. To this end, the encapsulation layer 150 may include at least one inorganic layer and at least one organic layer.

Meanwhile, although not shown in fig. 5, a capping layer may be additionally disposed between the second electrode 140 and the encapsulation layer 150.

A color filter CF may be disposed on the encapsulation layer 150. The color filter CF may be disposed on one surface of the second substrate 112 facing the first substrate 111. In this case, the first substrate 111 provided with the encapsulation layer 150 and the second substrate 112 provided with the color filter CF may be bonded to each other by the adhesive layer 160. At this time, the adhesive layer 160 may be an optically transparent resin (OCR) layer or an optically transparent adhesive (OCA) film.

The color filter CF may be provided to be patterned for each of the sub-pixels P1, P2, P3, and P4. Specifically, the color filters CF may include a first color filter, a second color filter, and a third color filter. The first color filter may be disposed to correspond to the light emitting area EA1 of the first sub-pixel P1, and may be a green color filter transmitting green light. The second color filter may be disposed to correspond to the light emitting area EA2 of the second sub-pixel P2, and may be a red color filter transmitting red light. The third color filter may be disposed to correspond to the light emitting area EA3 of the third sub-pixel P3, and may be a blue color filter transmitting blue light. The color filter CF may further include a fourth color filter disposed to correspond to the light emitting area EA4 of the fourth sub-pixel P4. In this case, the fourth color filter may be made of a transparent organic material that transmits white light.

The transparent display panel 110 according to one embodiment of the present disclosure may prevent the transmittance from being lowered due to the polarizer not attached thereto. In addition, in the transparent display panel 110 according to one embodiment of the present disclosure, the color filter CF may be disposed in the second substrate 112 to partially absorb external incident light, thereby preventing the incident light from being reflected in the electrodes. That is, the transparent display panel 110 according to one embodiment of the present disclosure may reduce the external light reflectance without reducing the transmittance.

Meanwhile, the black matrix BM may be disposed between the color filters CF and between the color filter CF and the first transmission region TA 1. The black matrix BM may be disposed between the subpixels P1, P2, P3, and P4 to prevent color mixing from occurring between the adjacent subpixels P1, P2, P3, and P4.

The black matrix BM may include a material that absorbs light, for example, a black dye that completely absorbs light in a visible wavelength range.

Hereinafter, an example of providing the first signal line SL1, the second signal line SL2, and the driving transistor TR will be described in detail with reference to fig. 4 and 5.

As described above, the display area DA includes the first transmissive area TA1 and the first non-transmissive area NTA 1. The first non-transmissive area NTA1 may extend in a first direction (e.g., an X-axis direction) between adjacent transmissive areas TA, or may extend in a second direction (e.g., a Y-axis direction) between adjacent transmissive areas TA.

The second signal line SL2 and the driving transistors TR1 and TR2 of the sub-pixels P1 and P2 disposed to overlap at least a portion of the second signal line SL2 may be disposed in the first non-transmission region NTA 1. For example, the first and second subpixels P1 and P2 may be disposed to overlap at least a portion of the second signal line SL2, and may be alternately disposed along the second signal line SL 2. A second signal line SL2, a first driving transistor TR1 of the first subpixel P1, and a second driving transistor TR2 of the second subpixel P2 may be disposed in the first non-transmissive area NTA 1.

The second signal line SL2 may be disposed in the first non-transmissive region NTA1 and extend in a second direction (e.g., Y-axis direction). The second signal line SL2 may include a plurality of signal lines, such as power supply lines. The power lines may include a first power line and a second power line.

The first power supply line may be disposed in the first non-transmissive area NTA1 and may extend in a second direction (e.g., Y-axis direction). In one embodiment, the first power line may be a pixel power line VDDL that supplies the first power to the first electrode 120 of each of the subpixels P1, P2, P3, and P4.

The second power line may be disposed in the first non-transmissive region NTA1, and may extend in a second direction (e.g., Y-axis direction) parallel to the first power line. In one embodiment, the second power line may be a common power line VSSL for supplying the second power to the second electrode 140 of each of the sub-pixels P1, P2, P3, and P4.

For example, the second signal line SL2 may further include a first data line DL1, a reference line REFL, and a second data line DL 2.

Specifically, the reference line REFL may be disposed in the first non-transmission region NTA1 and extend in the second direction (e.g., the Y-axis direction). The reference line REFL may supply a reference voltage (or an initialization voltage or a sensing voltage) to the driving transistor TR of each of the sub-pixels P1, P2, P3, and P4 disposed in the display area DA.

The first data line DL1 may be disposed in the first non-transmissive region NTA1, disposed on a first side of the reference line REFL, and extending in a second direction (e.g., Y-axis direction). The first data line DL1 may supply a data voltage to at least a portion of the sub-pixels P1, P2, P3, and P4 disposed in the display area DA.

For example, the first data line DL1 may supply the first data voltage to the second driving transistor TR2 of the second sub-pixel P2 and the third driving transistor TR3 of the third sub-pixel P3 disposed at the first side of the reference line REFL.

The second data line DL2 may be disposed in the first non-transmission region NTA1, disposed at a second side of the reference line REFL, and extending in a second direction (e.g., Y-axis direction). At this time, the second side of the reference line REFL may be a side facing the first side. For example, when the first side is the left side of the reference line REFL, the second side may be the right side of the reference line REFL. The second data line DL2 may supply data voltages to other subpixels, except for subpixels connected to the first data line, among the subpixels P1, P2, P3, and P4 disposed in the display area DA.

For example, the second data line DL2 may supply the second data voltage to the first driving transistor TR1 of the first sub-pixel P1 and the fourth driving transistor TR4 of the fourth sub-pixel P4 disposed at the second side of the reference line REFL.

In the transparent display panel 110 according to an embodiment of the present disclosure, the reference line REFL may not be disposed adjacent to the first and second data lines DL1 and DL 2. A constant voltage may be applied to the reference line REFL, and data voltages may be applied to the data lines DL1 and DL2 in the form of pulses. When the reference line REFL is disposed adjacent to the data lines DL1 and DL2, when a voltage variation occurs in the data lines DL1 and DL2, a crosstalk phenomenon caused by capacitive coupling between the reference line REFL and the data lines DL1 and DL2 may occur. In this case, the voltage of the reference line REFL may vary, and in addition, the luminance of the sub-pixels P1, P2, P3, and P4 may vary. As a result, a dark line or a bright line may be generated.

The transparent display panel 110 may be provided with a wide-area first transmission area TA1 to ensure light transmittance, and may be provided with a relatively narrow-area first non-transmission area NTA 1. The plurality of signal lines have no transmittance and thus may be disposed in the first non-transmissive area NTA 1. In this case, since the plurality of signal lines are disposed in the first non-transmission region NTA1 of the narrow region in the transparent display panel 110 as compared with the general display panel, the spaced distance between the signal lines is not selected except for being reduced. For this reason, in the transparent display panel 110, parasitic capacitance between the reference line REFL and the data lines DL1 and DL2 may increase, and a crosstalk phenomenon caused by capacitive coupling may occur more seriously.

In the transparent display panel 110 according to an embodiment of the present disclosure, in order to minimize parasitic capacitance between the reference line REFL and the data lines DL1 and DL2 in a limited space, the reference line REFL and the data lines DL1 and DL2 may not be disposed adjacent to each other.

Specifically, in the transparent display panel 110 according to one embodiment of the present disclosure, the pixel power supply line VDDL or the common power supply line VSSL may be disposed between the reference line REFL and the first data line DL1, and thus the reference line REFL and the first data line DL1 may not be disposed adjacent to each other. Further, the pixel power supply line VDDL or the common power supply line VSSL may be disposed between the reference line REFL and the second data line DL2, and thus the reference line REFL and the second data line DL2 may not be disposed adjacent to each other. Since a constant power supply voltage, which is not a pulse type, is applied to the pixel power supply line VDDL or the common power supply line VSSL, the pixel power supply line VDDL or the common power supply line VSSL may less affect the reference line REFL.

That is, in the transparent display panel 110 according to one embodiment of the present disclosure, another signal line may be disposed between the reference line REFL and the data lines DL1 and DL2, whereby a spaced distance between the reference line REFL and the data lines DL1 and DL2 may be increased. Accordingly, in the transparent display panel 110 according to one embodiment of the present disclosure, the parasitic capacitance between the reference line REFL and the data lines DL1 and DL2 may be reduced.

Meanwhile, in the transparent display panel 110 according to an embodiment of the present disclosure, the reference line REFL may be disposed on a different layer from the data lines DL1 and DL 2. Specifically, the reference line REFL may be disposed on a first layer, and the data lines DL1 and DL2 may be disposed on a second layer different from the first layer.

In one embodiment, the reference line REFL may be disposed on the same layer as one of the elements constituting the driving transistor TR. Specifically, the reference line REFL may be disposed on the same layer as any one of the active layer ACT, the gate electrode GE, the source electrode SE, and the drain electrode DE of the driving transistor TR. For example, as shown in fig. 5, the reference line REFL may be disposed on the same layer as the gate electrode GE.

In one embodiment, the data lines DL1 and DL2 may be disposed between the driving transistor TR and the substrate 111. For example, as shown in fig. 5, the data lines DL1 and DL2 may be disposed on the same layer as the light shielding layer LS.

In the transparent display panel 110 according to an embodiment of the present disclosure, the reference line REFL and the data lines DL1 and DL2 may be disposed on their respective layers different from each other, whereby a spaced distance between the reference line REFL and the data lines DL1 and DL2 in a limited space may be maximized. Accordingly, the transparent display panel 110 according to one embodiment of the present disclosure may minimize parasitic capacitance between the reference line REFL and the data lines DL1 and DL 2.

The first and second driving transistors TR1 and TR2 may be disposed in a zigzag pattern without being disposed on a straight line. Specifically, as shown in fig. 4, the first driving transistor TR1 may be disposed at one side of a first center line parallel to a second direction (e.g., Y-axis direction) in the first non-transmission region NTA1, and the second driving transistor TR2 may be disposed at the other side of the first center line.

That is, the first driving transistor TR1 may be disposed at a second side of the reference line REFL and may be disposed between the second data line DL2 and the first transmission region TA 1. The second driving transistor TR2 may be disposed at a first side of the reference line REFL and may be disposed between the first data line DL1 and the first transmission region TA 1.

The transparent display panel 110 according to one embodiment of the present disclosure is characterized in that the first and second driving transistors TR1 and TR2 are disposed in a zigzag pattern.

For example, it is assumed that the first and second driving transistors TR1 and TR2 are disposed on a straight line on the first side of the reference line REFL.

The first driving transistor TR1 may be connected to the first data line DL1, and the second driving transistor TR2 may be connected to the second data line DL 2. At this time, a connection line for connecting the second driving transistor TR2 and the second data line DL2 should cross the first data line DL1, the pixel power supply line VDDL, the reference line REFL, and the common power supply line VSSL. Accordingly, a connection line for connecting the second driving transistor TR2 and the second data line DL2 may have a longer length, and a loss of the data voltage may occur due to resistance.

In addition, since the connection line for connecting the first driving transistor TR1 and the first data line DL1 and the connection line for connecting the second driving transistor TR2 and the second data line DL2 are different in length from each other, a deviation of the data voltage may occur.

In the transparent display panel 110 according to one embodiment of the present disclosure, the first and second driving transistors TR1 and TR2 may be disposed in a zigzag pattern such that a connection line for connecting the first driving transistor TR1 and the second data line DL2 and a connection line for connecting the second driving transistor TR2 and the first data line DL1 may have the same or similar length.

Accordingly, the transparent display panel 110 according to one embodiment of the present disclosure may prevent a deviation of a signal voltage applied to each of the first and second driving transistors TR1 and TR 2.

In addition, the transparent display panel 110 according to one embodiment of the present disclosure may minimize the length of a connection line for connecting the second and first signal lines DL2 and DL1 and the first and second driving transistors TR1 and TR 2. The transparent display panel 110 according to one embodiment of the present disclosure may prevent a loss of a signal voltage (e.g., a data voltage).

The first signal line SL1 and the driving transistors TR3 and TR4 of the sub-pixels P3 and P4 disposed to overlap at least a portion of the first signal line SL1 may be disposed in the first non-transmission region NTA 1. For example, the third and fourth sub-pixels P3 and P4 may be disposed to overlap at least a portion of the first signal line SL1, and may be alternately disposed along the first signal line SL 1. The first signal line SL1, the third driving transistor TR3 of the third subpixel P3, and the fourth driving transistor TR4 of the fourth subpixel P4 may be disposed in the first non-transmissive area NTA 1.

The first signal line SL1 may be disposed in the first non-transmissive region NTA1 and extend in a first direction (e.g., an X-axis direction). The first signal line SL1 may include a plurality of signal lines, for example, at least one scan line scall 1 or scall 2.

In the following description, the first non-transmissive region NTA1 is provided with two scan lines scall 1 and scall 2, but is not limited thereto. The first non-transmission region NTA1 may be provided with only one scan line.

Specifically, the first scan line SCANL1 may be disposed in the first non-transmissive region NTA1 and extend in a first direction (e.g., an X-axis direction). The first scan line scall 1 may supply a scan signal to at least a portion of the sub-pixels P1, P2, P3, and P4 disposed in the display area DA.

For example, the first scan line SCANL1 may provide a first scan signal to the first driving transistor TR1 of the first subpixel P1 and the third driving transistor TR3 of the third subpixel P3.

The second scan line SCANL2 may be disposed in the first non-transmissive region NTA1 and extend in a first direction (e.g., an X-axis direction). The second scan line scall 2 may supply scan signals to sub-pixels other than the sub-pixels connected to the first scan line scall 1 among the sub-pixels P1, P2, P3, and P4 disposed in the display region DA.

For example, the second scan line scall 2 may provide a second scan signal to the second drive transistor TR2 of the second subpixel P2 and the fourth drive transistor TR4 of the fourth subpixel P4.

The first and second scan lines scall 1 and scall 2 may be disposed on different layers from the second signal line SL 2. Specifically, the first and second scan lines scall 1 and SCANL2 may be disposed on different layers from the first, reference and second data lines DL1, REFL and DL 2.

In one embodiment, the first scan line scall 1 and the second scan line scall 2 may be provided on the same layer as one of elements constituting the driving transistor TR. Specifically, the first and second scan lines scall 1 and scall 2 may be disposed on the same layer as any one of the active layer ACT, the gate electrode GE, the source electrode SE, and the drain electrode DE of the driving transistor TR. For example, the first and second scan lines scall 1 and scall 2 may be disposed on the same layer as the source and drain electrodes SE and DE.

Referring again to fig. 2, the non-display area NDA may include a PAD area PAD provided with a PAD, and at least one scan driver 205.

Specifically, the non-display region NDA may include a first non-display region NDA1 disposed at one side of the display region DA, a second non-display region NDA2 disposed at the other side perpendicular to one side of the display region DA, a third non-display region NDA3 disposed in parallel with the first non-display region NDA1 with the display region DA interposed therebetween, and a fourth non-display region NDA4 disposed in parallel with the second non-display region NDA2 with the display region DA interposed therebetween. At this time, the pad may be disposed in the third non-display area NDA 3.

The first non-display area NDA1 may include a pixel power shorting bar (shorting bar) VDD connected to a plurality of pixel power lines VDDL disposed in the display area DA and a common power shorting bar VSS connected to a plurality of common power lines VSSL disposed in the display area DA.

The scan driver 205 may be disposed in any one of the second non-display region NDA2 and the fourth non-display region NDA 4. The scan driver 205 is connected to the scan lines to supply scan signals. The scan driver 205 may be disposed at one side or both sides of the display area DA in a gate driver in panel (GIP) type. For example, as shown in fig. 2, the scan driver 205 may be disposed in the second non-display region NDA2, and another scan driver 205 may be disposed in the fourth non-display region NDA4, but is not limited thereto. The scan driver 205 may be disposed in only one of the second and fourth non-display regions NDA2 and NDA 4.

The ground line GND may be disposed in the first, second, and fourth non-display regions NDA1, NDA2, and NDA 4. The ground GND may be provided at an edge of at least one side of the substrate 111. For example, the ground line GND may be provided along an edge of a side surface other than the side surface on which the pad area PA is provided among the plurality of side surfaces of the substrate 111.

Hereinafter, the pixel power shorting bar VDD, the common power shorting bar VSS, the scan driver 205, and the ground line GND disposed in the non-display area NDA will be described in more detail.

Fig. 6 is an enlarged view illustrating a region B of fig. 2, fig. 7 is an enlarged view illustrating a region C of fig. 6, fig. 8 is a sectional view taken along a line II-II 'of fig. 7, and fig. 9 is a sectional view taken along a line III-III' of fig. 7.

Fig. 10 is a view illustrating a region D of fig. 6, fig. 11 is a view illustrating a region E of fig. 6, fig. 12 is a view illustrating a region F of fig. 6, and fig. 13 is a view illustrating an example in which color filters are disposed in a display region, a first non-display region, and a second non-display region.

As described with reference to fig. 3, the display area DA may include the first non-transmission areas NTA1 and the first transmission areas TA1 disposed between the first non-transmission areas NTA 1. The first transmission region TA1 is a region transmitting most of light incident from the outside, and the first non-transmission region NTA1 is a region not transmitting most of light incident from the outside.

The first non-transmissive region NTA1 may include a pixel power supply line VDDL, a common power supply line VSSL, a reference line, a data line, scan lines scall 1 and scall 2, and sub-pixels P1, P2, P3, and P4.

The scan lines SCANL1 and SCANL2 may extend in a first direction (e.g., an X-axis direction) and may cross the pixel power supply line VDDL, the common power supply line VSSL, the reference line, and the data line in the display area DA.

The pixel power supply line VDDL, the common power supply line VSSL, the reference line, and the data line may extend from the display area DA in a second direction (e.g., a Y-axis direction).

The first non-display area NDA1 may include second non-transmission areas NTA2 and second transmission areas TA2 disposed between the second non-transmission areas NTA 2. The second transmission region TA2 is a region that transmits almost as it is light incident from the outside as the first transmission region TA1, and the second non-transmission region NTA2 is a region that does not transmit most of light incident from the outside as the first non-transmission region NTA 1.

The second non-transmissive area NTA2 may include a pixel power supply shorting bar VDD, a common power supply shorting bar VSS, a pixel power supply line VDDL, and a common power supply line VSSL.

The pixel power supply shorting bar VDD may extend in the first direction (e.g., X-axis direction) in the second non-transmissive area NTA 2. At this time, the pixel power supply shorting bar VDD disposed in the second non-transmissive area NTA2 may be set to be plural. As shown in fig. 6, the pixel power shorting bar VDD may include, but is not limited to, a first pixel power shorting bar VDD1 and a second pixel power shorting bar VDD 2. The pixel power supply shorting bar VDD may be three or more.

When the plurality of pixel power supply shorting bars VDD are disposed as described above, each of the first and second pixel power supply shorting bars VDD1 and VDD2 may extend parallel to each other in a first direction (e.g., an X-axis direction) and may be spaced apart from each other. The second non-transmissive area NTA2 may include first and second pixel power supply connection electrodes VDDC1 and VDDC2 that connect the first and second pixel power supply shorting bars VDD1 and VDD 2.

As shown in fig. 10, the first pixel power supply connection electrode VDDC1 may extend in the second direction, and may connect at least one end of the first pixel power supply shorting bar VDD1 with at least one end of the second pixel power supply shorting bar VDD 2. For example, one first pixel power supply connection electrode VDDC1 may connect one end of the first pixel power supply shorting bar VDD1 with one end of the second pixel power supply shorting bar VDD 2. Another first pixel power supply connection electrode VDDC1 may connect the other end of the first pixel power supply shorting bar VDD1 with the other end of the second pixel power supply shorting bar VDD 2.

The transparent display panel 110 according to one embodiment of the present disclosure is characterized in that ends of a plurality of pixel power shorting bars VDD1 and VDD2 are connected to each other. The current may be concentrated at the ends of the electrode pattern. When the end portions of the electrode patterns protrude and are disposed adjacent to each other, static electricity may occur between the end portions due to a current concentration phenomenon. In the transparent display panel 110 according to one embodiment of the present disclosure, the ends of the plurality of pixel power shorting bars VDD1 and VDD2 may be connected to each other through the first pixel power connecting electrode VDDC1, whereby current may not be concentrated on the end of each of the plurality of pixel power shorting bars VDD1 and VDD 2. Therefore, in the transparent display panel 110 according to one embodiment of the present disclosure, the plurality of pixel power shorting bars VDD1 and VDD2 may prevent static electricity from occurring between other electrodes or signal lines disposed adjacent thereto.

Meanwhile, the second pixel power supply connection electrode VDDC2 may extend from the second non-transmissive region NTA2 in a second direction (e.g., a Y-axis direction) to connect the first and second pixel power supply shorting bars VDD1 and VDD 2. The second pixel power supply connection electrode VDDC2 may be disposed between two first pixel power supply connection electrodes VDDC 1. Specifically, a plurality of second pixel power supply connection electrodes VDDC2 may be disposed between one first pixel power supply connection electrode VDDC1 for connecting one end of the first pixel power supply shorting bar VDD1 and one end of the second pixel power supply shorting bar VDD2 and the other first pixel power supply connection electrode VDDC1 for connecting the other end of the first pixel power supply shorting bar VDD1 and the other end of the second pixel power supply shorting bar VDD 2.

The second pixel power supply connection electrode VDDC2 may be formed of a line, but is not limited thereto. The second pixel power supply connection electrode VDDC2 may be formed of a plurality of lines spaced apart from each other.

In the transparent display panel 110 according to one embodiment of the present disclosure, the second pixel power supply connection electrode VDDC2 disposed in the second non-transmissive area NTA2 in the second direction may be provided with a plurality of lines, and thus may have a structure similar to that of the first non-transmissive area NTA1 provided with a plurality of signal lines. Accordingly, the transparent display panel 110 according to one embodiment of the present disclosure may minimize a difference between the display area DA and the first non-transmissive area NTA 1.

In the description, reference may be made to "visual uniformity" or "difference in visual appearance". When various regions or areas of a transparent display panel, such as the transparent display panel 110, are configured differently, for example, to perform different functions, each region or area may exhibit slightly different visual characteristics. Examples of visual characteristics include, but are not limited to: transparency/transmission, reflectance, haze, color, moir effect, and the like. Two regions having "high" visual uniformity may include some or all of the visual characteristics at substantially the same level. When two regions have "low" visual uniformity, a perceptible interface between the two regions may occur, for example, because one of the regions has high transparency (e.g., > 90%) and the other region has low transparency (e.g., < 85%). For example, if there is a large transmittance divergence between the non-display area and the display area DA, one or more of the non-display areas NDA1 through NDA4 may be visually recognized.

The second transmissive area TA2 may be disposed between the first and second pixel power supply shorting bars VDD1 and VDD 2.

The second transmission area TA2 disposed between the first pixel power supply shorting bar VDD1 and the second pixel power supply shorting bar VDD2 may have substantially the same shape or the same light transmittance as the first transmission area TA1 disposed in the display area DA. In this case, "substantially the same shape" means that the properties of the shapes displayed on the plane are the same as each other. The dimensions or ratios may be the same or different from each other.

For example, the first transmissive area TA1 disposed in the display area DA may have a rectangular shape with rounded corners or pointed corners, but is not limited thereto. In this case, the second transmission region TA2 may also have a rectangular shape, wherein the rectangular shape may have rounded corners or pointed corners.

Meanwhile, the second non-transmissive area NTA2 provided with the first and second pixel power source shorting bars VDD1 and VDD2 may have a width W2 in a second direction perpendicular to the first direction, and the width W2 may be substantially the same as the width W1 of the first non-transmissive area NTA1 provided in the display area DA in the second direction.

Each of the first and second pixel power source shorting bars VDD1 and VDD2 may be disposed in the second non-transmissive area NTA2 in the first direction. Accordingly, as shown in fig. 7, each of the first and second pixel power source shorting bars VDD1 and VDD2 may have the same width W3 as the width W2 of the second non-transmissive area NTA2 in the second direction, or may have a width W3 smaller than the width W2 of the second non-transmissive area NTA2 in the second direction.

As a result, the plurality of pixel power source shorting bars VDD disposed in the first non-display area NDA1 may have the same width W3 as the width W1 of the first non-transmission area NTA1 disposed in the display area DA in the second direction, or may have a width W3 smaller than the width W1 of the first non-transmission area NTA1 in the second direction.

Meanwhile, the second pixel power supply connection electrode VDDC2 may extend in the second direction between the first pixel power supply shorting bar VDD1 and the second pixel power supply shorting bar VDD 2. The second non-transmissive region NTA2 provided with the second pixel power supply connection electrode VDDC2 may have a width W5 in the first direction, and the width W5 may be substantially the same as a width W4 of the first non-transmissive region NTA1 provided in the display region DA in the first direction.

The second pixel power supply connection electrode VDDC2 may be disposed in the second non-transmissive area NTA2 in the second direction. Accordingly, the second pixel power supply connection electrode VDDC2 may have the same width W6 as the width W5 of the second non-transmissive region NTA2 in the first direction, or may have a width W6 smaller than the width W5 of the second non-transmissive region NTA2 in the first direction.

The second pixel power supply connection electrode VDDC2 may be disposed as one line, but is not limited thereto. As shown in fig. 7, the second pixel power supply connection electrode VDDC2 may be provided with a plurality of lines. In addition, the second pixel power supply connection electrode VDDC2 may be disposed in parallel with the common power supply line VSSL in the second non-transmissive region NTA 2. In this case, the second pixel power supply connection electrode VDDC2 may have a width W6 smaller than a width W5 of the second non-transmissive region NTA2 in the first direction.

In the transparent display panel 110 according to one embodiment of the present disclosure, the plurality of pixel power shorting bars VDD disposed in the first non-display area NDA1 do not have a wide width. In the transparent display panel 110 according to an embodiment of the present disclosure, the width W3 of the pixel power shorting bar VDD is equal to or less than the width W1 of the first non-transmission region NTA1 disposed in the display region DA, and thus the second transmission region TA2 may be provided with a wide range in the first non-display region NDA 1.

In the transparent display panel 110 according to an embodiment of the present disclosure, a plurality of pixel power source shorting bars VDD are provided, whereby the total area of the pixel power source shorting bars VDD may be increased.

In addition, in the transparent display panel 110 according to an embodiment of the present disclosure, the pixel power shorting bar VDD may be formed of a plurality of metal layers to increase the total area thereof.

Specifically, the pixel power supply shorting bar VDD may include a plurality of metal layers. For example, each of the first and second pixel power shorting bars VDD1 and VDD2 may include a first metal layer VDD1-1 or VDD2-1 and a second metal layer VDD1-2 or VDD2-2 disposed on the first metal layer VDD1-1 or VDD2-1, as shown in FIG. 8. The second metal layers VDD1-2 and VDD2-2 at least partially overlap the first metal layers VDD1-1 and VDD2-1 and may be connected to the first metal layers VDD1-1 and VDD2-1 through first contact holes CH 1.

At this time, the first metal layer VDD1-1 or VDD2-1 of each of the first and second pixel power shorting bars VDD1 and VDD2 may be disposed on the same layer as the pixel power source line VDDL extending from the display area DA. For example, the first metal layer VDD1-1 or VDD2-1 of each of the first and second pixel power supply shorting bars VDD1 and VDD2 may be disposed on the same layer as the light shielding layer LS. The first metal layer VDD1-1 or VDD2-1 of each of the first and second pixel power supply shorting bars VDD1 and VDD2 may be formed of the same material as the light-shielding layer LS at the same time as the light-shielding layer LS.

The second metal layer VDD1-2 or VDD2-2 of each of the first and second pixel power supply shorting bars VDD1 and VDD2 may be made of an opaque metal material having a low resistance. For example, the second metal layer VDD1-2 or VDD2-2 of each of the first and second pixel power supply shorting bars VDD1 and VDD2 may be disposed on the same layer as the source electrode SE and the drain electrode DE of the driving transistor TR disposed in the display area DA. The second metal layer VDD1-2 or VDD2-2 of each of the first and second pixel power supply shorting bars VDD1 and VDD2 may be formed of the same material as that of the source and drain electrodes SE and DE of the driving transistor TR at the same time. In this case, the second metal layer VDD1-2 or VDD2-2 of each of the first and second pixel power supply shorting bars VDD1 and VDD2 may be connected to the first metal layer VDD1-1 or VDD2-1 through a plurality of first contact holes CH1 passing through the interlayer dielectric film ILD, the gate insulating film GI, and the buffer film BF.

In the transparent display panel 110 according to an embodiment of the present disclosure, each of the plurality of pixel power shorting bars VDD1 and VDD2 disposed in the first non-display area NDA1 is disposed as a double layer, whereby the total area of the pixel power shorting bars VDD may be increased. Therefore, in the transparent display panel 110 according to one embodiment of the present disclosure, even if the pixel power supply shorting bar VDD is formed with a small width W3, the resistance of the pixel power supply shorting bar VDD may be prevented from increasing.

In addition, in the transparent display panel 110 according to an embodiment of the present disclosure, the second metal layers VDD1-2 and VDD2-2 of the first and second pixel power supply shorting bars VDD1 and VDD2 are respectively connected to the first metal layers VDD1-1 and VDD2-1 of the first and second pixel power supply shorting bars VDD1 and VDD2 through the plurality of first contact holes CH1, whereby the first metal layers VDD1-1 and VDD2-1 may be stably connected to the second metal layers VDD1-2 and VDD2-2, respectively.

The common power source shorting bar VSS may extend from the second non-transmissive area NTA2 in a first direction (e.g., X-axis direction). At this time, the common power supply shorting bar VSS disposed in the second non-transmissive area NTA2 may be disposed in plurality. As shown in fig. 6, the common power shorting bar VSS may include, but is not limited to, a first common power shorting bar VSS1, a second common power shorting bar VSS2, and a third common power shorting bar VSS 3. The common power source shorting bar VSS may be two or four or more.

When the plurality of common power source shorting bars VSS are disposed as described above, the first, second, and third common power source shorting bars VSS1, VSS2, and VSS3 may extend parallel to and be spaced apart from each other in a first direction (e.g., X-axis direction). The second non-transmissive area NTA2 may include a first common power connection electrode VSSC1 and a second common power connection electrode VSSC2 that connect the first common power shorting bar VSS1, the second common power shorting bar VSS2, and the third common power shorting bar VSS3 to each other.

As shown in fig. 10, the first common power supply connection electrode VSSC1 may extend in the second direction to connect at least one end of the first common power supply shorting bar VSS1, at least one end of the second common power supply shorting bar VSS2, and at least one end of the third common power supply shorting bar VSS3 to each other. For example, one first common power supply connection electrode VSSC1 may connect one end of the first common power supply shorting bar VSS1, one end of the second common power supply shorting bar VSS2, and one end of the third common power supply shorting bar VSS3 to each other. Another first common power supply connection electrode VSSC1 may connect the other end of the first common power supply shorting bar VSS1, the other end of the second common power supply shorting bar VSS2, and the other end of the third common power supply shorting bar VSS3 to each other.

The transparent display panel 110 according to one embodiment of the present disclosure is characterized in that ends of a plurality of common power shorting bars VSS1, VSS2, and VSS3 are connected to each other. The current may be concentrated at the ends of the electrode pattern. When the end portions of the electrode patterns protrude and are disposed adjacent to each other, static electricity may occur between the end portions due to a current concentration phenomenon. In the transparent display panel 110 according to one embodiment of the present disclosure, ends of the plurality of common power shorting bars VSS1, VSS2, and VSS3 may be connected to each other through the first common power connection electrode VSSC1, and thus current may not be concentrated at the end of each of the plurality of common power shorting bars VSS1, VSS2, and VSS 3. Therefore, in the transparent display panel 110 according to one embodiment of the present disclosure, the plurality of common power shorting bars VSS1, VSS2, and VSS3 may prevent static electricity from occurring between other electrodes or signal lines disposed adjacent thereto.

The second common power connection electrode VSSC2 may extend in the second non-transmissive region NTA2 in the second direction (e.g., Y-axis direction) to connect the first common power shorting bar VSS1 with the second common power shorting bar VSS2 or to connect the second common power shorting bar VSS2 with the third common power shorting bar VSS 3. The second common power connection electrode VSSC2 may be disposed between the two first common power connection electrodes VSSC 1. Specifically, a plurality of second common power supply connection electrodes VSSC2 may be disposed between one first common power supply connection electrode VSSC1 connecting one end of the first common power supply shorting bar VSS1, one end of the second common power supply shorting bar VSS2, and one end of the third common power supply shorting bar VSS3 to each other, and the other first common power supply connection electrode VSSC1 connecting the other end of the first common power supply shorting bar VSS1, the other end of the second common power supply shorting bar VSS2, and the other end of the third common power supply shorting bar VSS3 to each other.

The second common power supply connection electrode VSSC2 may be formed of one line, but is not limited thereto. The second common power connection electrode VSSC2 may be formed of a plurality of lines spaced apart from each other.

In the transparent display panel 110 according to one embodiment of the present disclosure, the second common power connection electrode VSSC2 disposed in the second non-transmissive area NTA2 in the second direction may be provided with a plurality of lines, and thus may have a similar structure to the first non-transmissive area NTA1 provided with a plurality of signal lines. Accordingly, the transparent display panel 110 according to one embodiment of the present disclosure may minimize a difference between the display area DA and the first non-transmission area NTA 1.

The second transmissive area TA2 may be disposed between the first, second, and third common power shorting bars VSS1, VSS2, and VSS 3.

The second transmissive area TA2 disposed between the first, second, and third common power source shorting bars VSS1, VSS2, and VSS3 may have substantially the same shape as the first transmissive area TA1 disposed in the display area DA. In this case, the substantially same shape means that the properties of the shapes displayed on the plane are the same as each other. The dimensions or ratios may be the same or different from each other.

Meanwhile, the second non-transmissive area NTA2 provided with the first, second, and third common power shorting bars VSS1, VSS2, and VSS3 may have a width W7 in a second direction perpendicular to the first direction, and the width W7 may be substantially the same as a width W1 of the first non-transmissive area NTA1 in the second direction, which is provided in the display area DA.

Each of the first, second, and third common power source shorting bars VSS1, VSS2, and VSS3 may be disposed in the second non-transmissive region NTA2 along the first direction. Accordingly, as shown in fig. 7, each of the first, second, and third common power shorting bars VSS1, VSS2, and VSS3 may have the same width W8 as the width W7 of the second non-transmissive region NTA2 in the second direction, or may have a width W8 smaller than the width W7 of the second non-transmissive region NTA2 in the second direction.

As a result, the plurality of common power source shorting bars VSS disposed in the first non-display area NDA1 may have the same width W8 as the width W1 of the first non-transmissive area NTA1 disposed in the display area DA in the second direction, or may have a width W8 smaller than the width W1 of the first non-transmissive area NTA1 in the second direction.

Meanwhile, the second common power connection electrode VSSC2 may extend in the second direction between the first and second common power shorting bars VSS1 and VSS2 or between the second and third common power shorting bars VSS2 and VSS 3. The second non-transmissive region NTA2 provided with the second common power supply connection electrode VSSC2 may have a width W9 in the first direction, and the width W9 may be substantially the same as a width W4 of the first non-transmissive region NTA1 provided in the display region DA in the first direction.

The second common power connection electrode VSSC2 may be disposed in the second non-transmission region NTA2 along the second direction. Accordingly, the second common power connection electrode VSSC2 may have the same width W10 as the width W9 of the second non-transmissive region NTA2 in the first direction, or may have a width W10 smaller than the width W9 of the second non-transmissive region NTA2 in the first direction.

The second common power connection electrode VSSC2 may be disposed in one line, but is not limited thereto. As shown in fig. 7, the second common power connection electrode VSSC2 may be provided with a plurality of wires. In this case, the second common power connection electrode VSSC2 may have a width W10 smaller than the width W9 of the second non-transmissive region NTA2 in the first direction.

In the transparent display panel 110 according to one embodiment of the present disclosure, the plurality of common power shorting bars VSS disposed in the first non-display area NDA1 do not have a wide width. In the transparent display panel 110 according to one embodiment of the present disclosure, the width W8 of the common power shorting bar VSS is equal to or less than the width W1 of the first non-transmission region NTA1 disposed in the display region DA, thereby securing a wide range of the second transmission region TA2 in the first non-display region NDA 1.

In the transparent display panel 110 according to an embodiment of the present disclosure, the plurality of common power shorting bars VSS are formed, whereby the total area of the common power shorting bars VSS may be increased.

Further, in the transparent display panel 110 according to one embodiment of the present disclosure, the common power shorting bar VSS may be formed of a plurality of metal layers to increase the total area thereof.

Specifically, the common power supply shorting bar VSS may include a plurality of metal layers. For example, each of the first and second common power shorting bars VSS1 and VSS2 may include a first metal layer VSS1-1 or VSS2-1 and a second metal layer VSS1-2 or VSS1-2 disposed on the first metal layer VSS1-1 or VSS2-1, as shown in FIG. 9. Second metal layers VSS1-2 and VSS2-2 at least partially overlap first metal layers VSS1-1 and VSS2-1 and may be connected to first metal layers VSS1-1 and VSS2-1 through second contact holes CH 2.

At this time, the first metal layer VSS1-1 or VSS2-1 of each of the first, second, and third common power shorting bars VSS1, VSS2, and VSS3 may be disposed on the same layer as the common power line VSSL extending from the display area DA. For example, the first metal layer VSS1-1 or VSS2-1 of each of the first, second, and third common power shorting bars VSS1, VSS2, and VSS3 may be disposed on the same layer as the light shielding layer LS. The first metal layer VSS1-1 or VSS2-1 of each of the first, second, and third common power source shorting bars VSS1, VSS2, and VSS3 may be formed of the same material as that of the light shielding layer LS at the same time as the light shielding layer LS.

The second metal layer VSS1-2 or VSS2-2 of each of the first, second, and third common power shorting bars VSS1, VSS2, and VSS3 may be made of an opaque metal material having a low resistance. For example, the second metal layer VSS1-2 or VSS2-2 of each of the first, second, and third common power source shorting bars VSS1, VSS2, and VSS3 may be disposed on the same layer as the source electrode SE and the drain electrode DE of the driving transistor TR disposed in the display area DA. The second metal layer VSS1-2 or VSS2-2 of each of the first, second, and third common power source shorting bars VSS1, VSS2, and VSS3 may be formed of the same material as the source and drain electrodes SE and DE of the driving transistor TR at the same time. In this case, the second metal layer VSS1-2 or VSS2-2 of each of the first, second and third common power shorting bars VSS1, VSS2 and VSS3 may be connected to the first metal layer VSS1-1 or VSS2-1 through a plurality of second contact holes CH2 passing through the interlayer dielectric film ILD, the gate insulating film GI and the buffer film BF.

In the transparent display panel 110 according to one embodiment of the present disclosure, each of the plurality of common power shorting bars VSS1, VSS2, and VSS3 disposed in the first non-display area NDA1 is disposed in a double layer, whereby the total area of the common power shorting bars VSS may be increased. Therefore, in the transparent display panel 110 according to one embodiment of the present disclosure, even if the common power source shorting bar VSS is formed with a small width W7, the resistance of the common power source shorting bar VSS may be prevented from increasing.

Further, in the transparent display panel 110 according to one embodiment of the present disclosure, the second metal layers VSS1-2 and VSS2-2 of each of the first, second, and third common power shorting bars VSS1, VSS2, and VSS3 are connected to the first metal layers VSS1-1 and VSS2-1 of each of the first, second, and third common power shorting bars VSS1, VSS2, and VSS3, whereby the first metal layers VSS1-1 and VSS2-1 may be stably connected to the second metal layers VSS1-2 and VSS 2-2.

Meanwhile, the first non-display area NDA1 may be provided with a plurality of dummy patterns DP on at least a portion of the second non-transmission area NTA 2. At this time, the plurality of dummy patterns DP may be floating patterns that are not electrically connected to other elements. Specifically, the plurality of dummy patterns DP may include a plurality of first dummy patterns DP1 disposed between the display area DA and the pixel power shorting bar VDD, and a plurality of second dummy patterns DP2 disposed between the pixel power shorting bar VDD and the common power shorting bar VSS.

Other electrodes or signal lines than the pixel power supply line VDDL and the common power supply line VSSL may not be disposed between the display area DA and the pixel power supply shorting bar VDD. In this case, the second non-transmission region NTA2 disposed between the display region DA and the pixel power source shorting bar VDD may have a higher light transmittance than the second non-transmission region NTA2 or the first non-transmission region NTA1 disposed with the pixel power source shorting bar VDD and the common power source shorting bar VSS. Accordingly, an area between the display area DA and the pixel power supply shorting bar VDD may be recognized due to a difference in light transmittance or visibility from other areas.

In the transparent display panel 110 according to an embodiment of the present disclosure, the plurality of first dummy patterns DP1 may be disposed in an area excluding the pixel power source line VDDL and the common power source line VSSL in the second non-transmission area NTA2 disposed between the display area DA and the pixel power source shorting bar VDD.

The plurality of first dummy patterns DP1 may be formed of a conductive material. In one embodiment, the plurality of first dummy patterns DP1 may be formed of the same material as one of the light blocking layer LS, the gate electrode GE, the source electrode SE, and the drain electrode DE on the same layer as one of them. When the plurality of first dummy patterns DP1 are disposed on the same layer as the pixel power supply line VDDL or the common power supply line VSSL, the plurality of first dummy patterns DP1 may be disposed to be spaced apart from the pixel power supply line VDDL or the common power supply line VSSL.

Other electrodes or signal lines than the common power line VSSL may not be disposed between the pixel power shorting bar VDD and the common power shorting bar VSS. In this case, the second non-transmission region NTA2 disposed between the pixel power source shorting bar VDD and the common power source shorting bar VSS may have a higher light transmittance than the second non-transmission region NTA2 or the first non-transmission region NTA1 disposed with the pixel power source shorting bar VDD and the common power source shorting bar VSS. Accordingly, an area between the pixel power supply shorting bar VDD and the common power supply shorting bar VSS may be identified due to a difference in light transmittance or visibility from other areas.

In the transparent display panel 110 according to an embodiment of the present disclosure, the plurality of second dummy patterns DP2 may be disposed in an area excluding the common power line VSSL in the second non-transmission area NTA2 disposed between the pixel power source shorting bar VDD and the common power source shorting bar VSS.

The plurality of second dummy patterns DP2 may be formed of a conductive material. In one embodiment, the plurality of second dummy patterns DP2 may be formed of the same material as one of the light blocking layer LS, the gate electrode GE, the source electrode SE, and the drain electrode DE on the same layer as one of them. When the plurality of second dummy patterns DP2 are disposed on the same layer as the common power line VSSL, the plurality of second dummy patterns DP2 may be disposed to be spaced apart from the common power line VSSL.

Referring again to fig. 6, the second non-display region NDA2 may include a third non-transmission region NTA3, a third transmission region TA3, a fourth non-transmission region NTA4, and a fourth transmission region TA 4. The third and fourth transmission regions TA3 and TA4 are regions that transmit light incident from the outside almost as it is as the first transmission region TA1, and the third and fourth non-transmission regions NTA3 and NTA4 are regions that do not transmit most of light incident from the outside as the first non-transmission region NTA 1. As shown in fig. 6, the third transmission regions TA3 are located between the third non-transmission regions NTA3, and the fourth transmission regions TA4 are located between the fourth non-transmission regions NTA 4. It will be appreciated that each of the third and fourth non-transmissive regions NTA3 and NTA4 may be a continuous region, such that the third and fourth transmissive regions TA and TA4 may be considered to be embedded in the third and fourth non-transmissive regions NTA3 and NTA4, respectively. The third and fourth transmission regions TA3 and TA4 may be considered to be located between segments of the third and fourth non-transmission regions NTA3 and NTA4, respectively. From the perspective of the third and fourth transmission regions TA3 and TA4, the third non-transmission region NTA3 may surround (e.g., encircle) the third transmission region TA3, and the fourth non-transmission region NTA4 may surround (e.g., encircle) the fourth transmission region TA 4. Although not specifically labeled in fig. 6, the third non-transmission region NTA3 may surround a plurality of third transmission regions TA3, and the fourth non-transmission region NTA4 may surround a plurality of fourth transmission regions TA 4. The above discussion of "being located between … …" can be similarly applied to the context of the first transmission region TA1 and the first non-transmission region NTA1, and the context of the second transmission region TA2 and the second non-transmission region NTA 2.

Each of the third and fourth transmission regions TA3 and TA4 disposed in the second non-display region NDA2 may have substantially the same shape or the same light transmittance as the first transmission region TA1 disposed in the display region DA. In this case, the substantially same shape means that the properties of the shapes displayed on the plane are the same as each other. The dimensions or ratios may be the same or different from each other.

For example, the first transmissive area TA1 disposed in the display area DA may have a rectangular shape with rounded corners or pointed corners, but is not limited thereto. In this case, each of the third and fourth transmission regions TA3 and TA4 may also have a rectangular shape, wherein the rectangular shape may have rounded corners or pointed corners.

Each of the third and fourth non-transmissive regions NTA3 and NTA4 disposed in the second non-display region NDA2 may be substantially the same as the first non-transmissive region NTA1 disposed in the display region DA in terms of a width W1 in the second direction or a width W4 in the first direction.

The third non-transmissive region NTA3 may be provided with a gate driver connected to the scan lines scall 1 and scall 2 provided in the display region DA to supply scan signals. The gate driver may include a plurality of circuit regions and a plurality of signal lines. The plurality of signal lines may include a plurality of first lines L1 extending in a first direction (e.g., an X-axis direction) and a plurality of second lines L2 extending in a second direction (e.g., a Y-axis direction).

One end of at least one of the plurality of signal lines of the gate driver may protrude toward the ground GND. In order to form a transmissive area having the same shape as the first transmissive area TA1 of the display area DA, the ground line GND may be branched and protruded toward the gate driver. In this case, the end of the signal line of the gate driver and the end of the electrode pattern branched from the ground line GND may be disposed adjacent to each other. Due to the current concentration phenomenon, static electricity may occur between the end of the signal line of the gate driver and the end of the ground GND, so that a burn (burn) phenomenon may occur.

In the transparent display panel 110 according to one embodiment of the present disclosure, as shown in fig. 11 and 12, a plurality of third dummy patterns DP3 may be disposed between the gate driver and the ground line GND, whereby a spacing distance between the gate driver and the ground line GND may be increased.

More specifically, in the transparent display panel 110 according to one embodiment of the present disclosure, the ground line GND may be formed in the form of one line, and the plurality of third dummy patterns DP3 may be disposed between the ground line GND and the plurality of signal lines L1 and L2 of the gate driver. In this case, the plurality of third dummy patterns DP3 may be disposed in the fourth non-transmission region NTA4, and may be floating patterns that are not electrically connected to other elements. The third dummy pattern DP3 may be made of substantially the same material as the ground line GND and may be located in the same layer as the bottom line GND. In one embodiment, the third dummy pattern DP3 and the ground line GND are or include a conductive material. For example, the third dummy pattern DP3 and the ground line GND may be or include a metal material (e.g., made of a metal material).

As a result, in the transparent display panel 110 according to one embodiment of the present disclosure, static electricity may be prevented from occurring between the gate driver and the ground GND.

In addition, a plurality of third dummy patterns DP3 may be disposed between the pixel power shorting bar VDD and the ground line GND and between the common power shorting bar VSS and the ground line GND. Specifically, a plurality of third dummy patterns DP3 may be disposed between the first pixel power supply connection electrode VDDC1 and the ground line GND and between the first common power supply connection electrode VSSC1 and the ground line GND, as shown in fig. 6 and 10.

In the transparent display panel 110 according to one embodiment of the present disclosure, the spaced distance between the first pixel power supply connection electrode VDDC1 and the ground line GND may be increased by the plurality of third dummy patterns DP3, whereby static electricity may be prevented from occurring between the first pixel power supply connection electrode VDDC1 and the ground line GND.

Further, in the transparent display panel 110 according to one embodiment of the present disclosure, the spaced distance between the first common power supply connection electrode VSSC1 and the ground line GND may be increased by the plurality of third dummy patterns DP3, whereby static electricity may be prevented from occurring between the first common power supply connection electrode VSSC1 and the ground line GND.

In fig. 6 to 12, only the first and second non-display regions NDA1 and NDA2 are described. However, the third non-display region NDA3 may also have substantially the same structure as the second non-display region NDA2, and in this case, a detailed description thereof will be omitted.

In the transparent display panel 110 according to one embodiment of the present disclosure, the first non-display area NDA1, the second non-display area NDA2, and the display area DA may have similar light transmittance. For this reason, in the transparent display panel 110 according to one embodiment of the present disclosure, at least one of the size of the second transmission region TA2 provided in a unit area, the size of the third transmission region TA3 provided in a unit area, or the size of the fourth transmission region TA4 provided in a unit area may be designed to be the same as the size of the first transmission region TA1 provided in a unit area. It will be understood that "… … size disposed in a unit area" may refer to the area of the transmissive region per unit of total area. For example, in the display area DA, the first non-transmissive area NTA1 may occupy a first area of the display area DA, and the first transmissive area TA1 may occupy a second area of the display area DA. The unit area (e.g., 10 cm) of the display area DA²) May include a unit portion (e.g., 2 cm) of the first area occupied by the first non-transmissive region NTA1²) And a unit portion (for example, 8 cm) of the second area occupied by the first transmission region TA1²). Thus, the "size of the first transmission region TA1 provided in the unit area" may be expressed as the portion of the second area itself (for example, for 10 cm)²8cm per unit area²) Or a ratio of fraction of the second area to unit area (e.g., 8 cm)²/10cm²Or 80%). It is beneficial to have the amount of transmissive regions per unit area (e.g., TA1, TA2, TA3, TA4) be substantially the same in one or more regions (e.g., DA, NDA1, NDA2, NDA3, NDA4) so that the transmittance is substantially uniform in the one or more regions. When the transparent display panel 110 is not powered on, if the display area is not powered onThe transmittance of the domain DA is different from the transmittance of the non-display regions NDA1 to NDA4, viewing of an object or a background through the transparent display panel 110 when not powered may not be uniform. For example, if the transmittance in the non-display areas NDA1 to NDA4 surrounding the display area DA is substantially lower than the transmittance in the display area DA, a dark boundary or a dark frame may be seen on an object or a background seen through the transparent display panel 110.

Accordingly, in the transparent display panel 110 according to one embodiment of the present disclosure, a transmittance similar to that of the display region DA may be achieved even in the first and second non-display regions NDA1 and NDA 2.

Further, in the transparent display panel 110 according to an embodiment of the present disclosure, the color filters CF1, CF2, CF3, and CF4 may be disposed in the second non-transmission region NTA2 disposed in the first non-display region NDA1, and in the third non-transmission region NTA3 and the fourth non-transmission region NTA4 disposed in the second non-display region NDA 2.

More specifically, black matrices (not shown) disposed between the color filters CF1, CF2, CF3, and CF4 and the color filters CF1, CF2, CF3, and CF4 may be disposed in the second non-transmission regions NTA2 disposed in the first non-display region NDA1 and the third and fourth non-transmission regions NTA3 and NTA4 disposed in the second non-display region NDA 2. In this case, as shown in fig. 13, the color filters CF1, CF2, CF3, and CF4 may be patterned on the first and second non-display areas NDA1 and NDA2 in the same shape as the color filters CF1, CF2, CF3, and CF4 disposed in the display area DA as shown in fig. 13.

As shown in fig. 13, the color filters CF1, CF2, CF3, and CF4 and a black matrix (not shown) may not be disposed in the second transmission region TA2 disposed in the first non-display region NDA1 and the third and fourth transmission regions TA3 and TA4 disposed in the second non-display region NDA2 to improve transmittance.

Accordingly, the transparent display panel 110 according to one embodiment of the present disclosure may minimize a difference between the transmittance in the first and second non-display regions NDA1 and NDA2 and the transmittance in the display region DA.

According to the present disclosure, the following advantageous effects can be obtained.

In the present disclosure, the plurality of pixel power source shorting bars and the plurality of common power source shorting bars may be disposed in the non-display region, and the transmission region may be disposed between the plurality of pixel power source shorting bars and between the plurality of common power source shorting bars. Since the transmissive area is disposed in the non-display area, the transmittance in the non-display area can be improved.

Further, the transmissive region provided in the non-display region and the transmissive region provided in the display region have the same shape, whereby transmittance similar to that of the display region can be achieved in the non-display region.

In addition, since the ends of the plurality of pixel power source shorting bars are connected to each other, it is possible to prevent current from being concentrated on the ends of the pixel power source shorting bars. As a result, it is possible to prevent static electricity from occurring between the signal lines or the electrode patterns disposed adjacent to the pixel power supply shorting bars.

Further, since the ends of the plurality of common power source shorting bars are connected to each other, it is possible to prevent current from concentrating on the ends of the common power source shorting bars. As a result, it is possible to prevent static electricity from occurring between the signal lines or the electrode patterns disposed adjacent to the common power source shorting bar.

In addition, a plurality of dummy patterns are disposed between the gate driver and the ground line, between the pixel power shorting bar and the ground line, and between the common power shorting bar and the ground line, whereby occurrence of static electricity can be prevented.

Further, the color filter is disposed in the non-display region and patterned in the same shape as that of the color filter disposed in the display region, whereby a difference between the transmittance in the non-display region and the transmittance in the display region may be minimized. Accordingly, the present disclosure may minimize the recognition of the non-display area.

It will be apparent to those skilled in the art that the present disclosure described above is not limited by the above embodiments and drawings, and that various substitutions, modifications and changes may be made in the present disclosure without departing from the spirit or scope of the present disclosure. Accordingly, the scope of the present disclosure is defined by the appended claims, and all changes or modifications derived from the meaning, range, and equivalent concept of the claims are intended to fall within the scope of the present disclosure.

Claims

1. A transparent display device, comprising:

a substrate provided with a display area on which a plurality of sub-pixels are disposed, a first non-display area disposed at one side of the display area, and a second non-display area disposed at the other side of the display area;

a plurality of power shorting bars disposed in the first non-display area on the substrate and extending in parallel in a first direction;

a plurality of power lines disposed in the display area on the substrate, extending in a second direction, and connected with the plurality of power shorting bars;

a first transmissive region disposed between the plurality of power supply lines; and

a second transmission region disposed between the plurality of power supply shorting bars and having the same shape as the first transmission region,

wherein the plurality of power shorting bars are connected to each other at least one end.

2. The transparent display device according to claim 1, wherein one end of each of the plurality of power shorting bars is connected to one first power connection electrode extending in the second direction, and the other end of each of the plurality of power shorting bars is connected to another first power connection electrode extending in the second direction.

3. The transparent display device according to claim 1, wherein the display region includes first non-transmission regions provided with the plurality of sub-pixels and the first transmission regions provided between the first non-transmission regions,

the first non-display area includes second non-transmissive areas provided with the plurality of power shorting bars and the second transmissive areas disposed between the second non-transmissive areas, and

the second non-transmissive area includes a plurality of second power supply connection electrodes connected to the plurality of power supply shorting bars.

4. The transparent display device according to claim 3, wherein each of the plurality of second power supply connection electrodes comprises a plurality of connection lines.

5. The transparent display device according to claim 3, wherein the second non-transmissive region has the same width as that of the first non-transmissive region in the first direction.

6. The transparent display device according to claim 3, wherein the second non-transmissive area has the same width as that of the first non-transmissive area along the second direction.

7. The transparent display device according to claim 3, wherein a size of the first transmissive region provided in a unit area and a size of the second transmissive region provided in a unit area are the same as each other.

8. The transparent display device of claim 3, further comprising a color filter disposed on the plurality of power shorting bars in the second non-transmissive region.

9. The transparent display device according to claim 1, wherein each of the plurality of sub-pixels comprises a first electrode, an organic light emitting layer, and a second electrode, and

the power supply line is a pixel power supply line supplying a first power to the first electrode or a common power supply line supplying a second power to the second electrode.

10. The transparent display device according to claim 1, further comprising a scan driver disposed in the second non-display region,

wherein the second non-display area includes third non-transmissive areas provided with the scan driver and third transmissive areas provided between the third non-transmissive areas, and

the third transmissive region has the same shape as the first transmissive region.

11. The transparent display device of claim 1, further comprising:

a scan driver disposed in the second non-display area;

a ground line disposed along an edge of the substrate in the first and second non-display areas; and

a plurality of dummy patterns disposed between the ground line and the scan driver and between the ground line and the power shorting bar,

wherein the second non-display area includes fourth non-transmission areas provided with the plurality of dummy patterns and fourth transmission areas disposed between the fourth non-transmission areas, and

the fourth transmissive region has the same shape as the first transmissive region.

12. The transparent display device according to claim 11, wherein the plurality of dummy patterns are made of the same material as that of the ground lines on the same layer as that of the ground lines.

13. The transparent display device according to claim 11, wherein the plurality of dummy patterns are disposed to be spaced apart from the scan driver and the ground line.

14. The transparent display device according to claim 11, wherein the plurality of dummy patterns are disposed to be spaced apart from the power shorting bar.

15. A transparent display device, comprising:

a plurality of pixel power source shorting bars disposed in the first non-display area on the substrate, extending in parallel in a first direction and spaced apart from each other;

a first pixel power supply connection electrode connected to ends of the plurality of pixel power supply shorting bars;

a plurality of common power source shorting bars disposed in the first non-display area on the substrate, extending in parallel in the first direction and spaced apart from each other; and

and the first public power supply connecting electrode is connected with the end parts of the plurality of public power supply short-circuit bars.

16. The transparent display device of claim 15, further comprising:

a plurality of pixel power lines disposed in the display area on the substrate, extending in a second direction and connected to the plurality of pixel power shorting bars; and

a plurality of common power lines disposed in the display area on the substrate, extending in the second direction and connected with the plurality of common power shorting bars.

17. The transparent display device according to claim 15, wherein the display region includes first non-transmission regions provided with the plurality of sub-pixels and first transmission regions provided between the first non-transmission regions,

the first non-display area includes a second non-transmission area and a second transmission area, the second non-transmission area is provided with the plurality of pixel power supply shorting bars, the first pixel power supply connection electrode, the plurality of common power supply shorting bars, and the first common power supply connection electrode, the second transmission area is disposed between the second non-transmission areas, and

the second transmission region has a width in a second direction that is the same as a width of the first transmission region.

18. The transparent display device of claim 17, wherein the second transmissive region has the same light transmittance as that of the first transmissive region.

19. The transparent display device of claim 17, wherein the second transmissive region has the same shape as the first transmissive region.

20. The transparent display device according to claim 15, further comprising a scan driver disposed in the second non-display area,

the third transmissive region has a light transmittance identical to that of the first transmissive region.

21. The transparent display device of claim 15, further comprising:

a scan driver disposed in the second non-display area;

a plurality of dummy patterns disposed between the ground line and the scan driver and between the ground line and the pixel power shorting bar and the common power shorting bar,

wherein the second non-display area includes fourth non-transmission areas provided with the plurality of dummy patterns and fourth transmission areas provided between the fourth non-transmission areas, and

22. The transparent display device of claim 21, wherein the plurality of dummy patterns are made of a metal material.

23. The transparent display device of claim 21, wherein the plurality of dummy patterns are disposed apart from the scan driver, the ground line, the plurality of pixel power shorting bars, and the plurality of common power shorting bars.

24. The transparent display device of claim 15, wherein the plurality of pixel power shorting bars are made of a first metal layer and a second metal layer disposed over the first metal layer.

25. The transparent display device of claim 24, wherein at least a portion of the second metal layer of the pixel power supply shorting bar overlaps the first metal layer of the pixel power supply shorting bar and is connected to the first metal layer of the pixel power supply shorting bar through a first contact hole.

26. The transparent display device of claim 24, further comprising a plurality of pixel power supply lines extending from the first metal layer of a pixel power supply shorting bar of the plurality of pixel power supply shorting bars closest to the display area in a second direction to provide a first power supply to the plurality of subpixels disposed in the display area.

27. The transparent display device according to claim 15, wherein the plurality of common power shorting bars are made of a first metal layer and a second metal layer disposed over the first metal layer.

28. The transparent display device of claim 27, wherein at least a portion of the second metal layer of the common power shorting bar overlaps the first metal layer of the common power shorting bar and is connected to the first metal layer of the common power shorting bar through a second contact hole.

29. The transparent display device of claim 27, further comprising a plurality of common power supply lines extending from the first metal layer of a common power supply shorting bar of the plurality of common power supply shorting bars closest to the display area in a second direction to provide a second power supply to the plurality of subpixels disposed in the display area.