CN114664653A - Silicon nitride etching method - Google Patents

Silicon nitride etching method Download PDF

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CN114664653A
CN114664653A CN202210254276.7A CN202210254276A CN114664653A CN 114664653 A CN114664653 A CN 114664653A CN 202210254276 A CN202210254276 A CN 202210254276A CN 114664653 A CN114664653 A CN 114664653A
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silicon nitride
etching
nitride film
power supply
passivation
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Inventor
陈长鸿
孙一军
孙颖
王妹芳
孙家宝
刘艳华
刘志
谢石建
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Zhejiang University ZJU
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings

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  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

The invention discloses a silicon nitride etching method. Generating passivation gas plasma by using an RF power supply to attach a passivation layer on the surface of the silicon nitride film, wherein the passivation layer is formed in a bulge and a groove on the surface of the silicon nitride film; adjusting an RF power supply to generate cleaning gas plasma, reserving a passivation layer on the side wall of the groove on the surface of the silicon nitride film, and enabling the cleaning gas plasma to remove residues on the surface of the silicon nitride film along the vertical direction; and introducing etching gas, and adjusting process parameters to etch the surface of the silicon nitride film. The invention realizes C for the first time4F6The method is applied to silicon nitride etching, and through optimization of process parameters such as RF power, ICP power, gas types, gas proportion, etching pressure and the like, the etching problems of low etching rate, over-etching of lower-layer materials and the like in the traditional hard mask etching process are overcome, the Si etching rate can be effectively reduced, and meanwhile, the Si etching rate is improved3N4The etch rate.

Description

Silicon nitride etching method
Technical Field
The invention belongs to an etching treatment method in the technical field of semiconductor processing, and particularly relates to a silicon nitride etching method.
Background
With the continuous advance of the technology node of the integrated circuit, the precision requirement of the manufacturing process is more and more strict. Wherein the etching process is more challenging as one of the key steps of the manufacturing process. For process nodes below 55nm, the photolithography process typically requires the use of thinner photoresists to achieve higher photolithography accuracy. But the thin glue is difficult to use as an etch mask. To improve the etching of the underlying material, it is often necessary to deposit Si3N4The thin film material serves as a hard mask instead of a conventional photoresist mask. While the main difficulties of hard mask etching include:
the pattern transfer precision of the traditional process is poor. The photoresist lateral etching is easily caused by the pattern transfer etching of the hard mask, so that the hard mask pattern size is shifted.
The impurity pollution problem of the traditional process. Due to the fact that one more pattern transfer process is adopted, the problems that impurities, dirt and the like appear at positions such as grooves of the device easily occur, and the device fails are caused.
The selectivity of the photoresist/silicon nitride etched by the traditional process is low, so that the hard mask is not etched through after the photoresist is etched.
The silicon nitride/silicon selectivity of the conventional process is low. The underlying material (e.g., Si, SiO) is easily etched during the process of etching the hard mask2Etc.) over-etching.
Disclosure of Invention
In order to solve the problems, the invention provides a three-step silicon nitride etching process, which improves the pattern transfer precision, the lower layer material selection ratio, the dielectric layer etching speed and the photoresist selection ratio through passivation, cleaning and novel electron gas etching, and effectively avoids the failure of devices caused by impurity pollution.
The technical scheme adopted by the invention is as follows:
s1, passivating: in the etching machine, an RF power supply of the etching machine is utilized to generate passivation gas plasma to attach a passivation layer on the surface of the silicon nitride film, and the passivation layer is formed in a protrusion and a groove on the surface of the silicon nitride film;
s2, cleaning: in the etching machine, adjusting an RF power supply of the etching machine to generate cleaning gas plasma, and keeping a passivation layer on the side wall of the groove on the surface of the silicon nitride film to ensure that the cleaning gas plasma removes residues on the surface of the silicon nitride film along the vertical direction;
s3, formal etching step: and introducing etching gas, and adjusting process parameters to etch the surface of the silicon nitride film.
The silicon nitride film is respectively a photoresist, a silicon nitride layer and a silicon substrate from top to bottom.
Before step S1, the silicon nitride film masked with the photoresist is also pre-etched using an etcher containing an ICP-RF dual power supply to form projections and grooves on the surface of the silicon nitride film.
All the passivating gases are C4F6The cleaning gas is O2And Ar, the etching gas is C4F6、CHF3And SF6The mixed gas of (1).
In the passivation step of S1, 50sccm of C is introduced4F6The chamber pressure of the etching machine is adjusted to make the environmental pressure 40-80mtorr, the ICP power supply 900-.
This step leads to C of chain-like molecular structure4F6Rapidly decomposing to form a passivation free radical, and rapidly attaching to form a passivation film. Meanwhile, the film formed by the chain-shaped molecular structure is easier to remove by chemical etching, and is beneficial to cleaning the vertical surface in the S2 cleaning step.
In the cleaning step of S2, 45sccm O is introduced2And 10sccm Ar, adjusting the chamber pressure of the etching machine to make the ambient pressure 3-10mtorr, ICP power supply 1000-The source 65W is maintained at the silicon nitride film temperature of 5-40 ℃ for 25 s.
Ionization of O at 8mtorr Using 1200W ICP Power supply2A large number of O free radicals can be generated, and meanwhile, a large vertical physical bombardment effect can be generated by the bias voltage of 65W and the air pressure of 8mtorr, so that the phenomenon that a side wall passivation film is chemically etched and removed is avoided, and the accuracy of pattern transfer is facilitated.
In the etching step of S3, 10sccm C is introduced4F6、15sccm CHF3And 5sccmSF6The chamber pressure of the etching machine is adjusted to make the environmental pressure 15-30mtorr, the ICP power supply 1000-1500W and the RF power supply 40-60W, and the temperature of the silicon nitride film is maintained at 5-40 ℃. The step increases the RF voltage, which is beneficial to anisotropic etching.
The invention realizes the application of the novel environment-friendly electronic gas C4F6 in silicon nitride etching. The invention provides a three-step etching method, overcomes the problems of low selection ratio, transverse etching and the like in the traditional silicon nitride etching process, improves the pattern transfer precision, the lower layer material selection ratio, the dielectric layer etching rate and the selection ratio of photoresist, and effectively avoids the failure of devices caused by impurity pollution.
Different from the prior art, the invention adds a pre-passivation step, namely pre-turning on C4F6As the side wall of the passivation gas protection device structure, the lateral side etching is effectively reduced, and the pattern transfer precision is improved.
Different from the prior art, the invention adds a vertical cleaning step, can effectively remove residual impurities in the groove of the device, and effectively avoids the failure of the device caused by impurity pollution.
Unlike the prior art, the present invention uses C4F6As silicon nitride etching, the etching rate of photoresist and lower layer Si can be effectively reduced and Si can be improved3N4The etching rate, the photoresist/silicon nitride selection ratio and the silicon nitride/silicon selection ratio are obviously improved, so that the etching efficiency can be effectively improved, and the lower layer material is prevented from being over-etched.
The invention realizes C for the first time4F6In the silicon nitride etching, and by RF power, ICP power, gas speciesThe optimization of technological parameters such as gas proportion, etching pressure and the like overcomes the problems of low etching rate, over-etching of lower-layer materials and the like in the traditional hard mask etching process.
The etching method can effectively reduce the Si etching rate and improve the Si3N4The selection of the etching rate is obviously improved compared with the traditional etching process.
The invention particularly adopts high selection ratio of the dielectric layer to the silicon when etching the contact hole and the through hole, and can avoid etching the lower layer material.
The beneficial effects of the invention are:
the invention provides a three-step etching method, overcomes the problems of low selection ratio, transverse etching and the like in the traditional silicon nitride etching process, improves the pattern transfer precision, the lower layer material selection ratio, the dielectric layer etching rate and the selection ratio of photoresist, and effectively avoids the failure of devices caused by impurity pollution.
Drawings
FIG. 1 is a flow chart of a silicon nitride etch process according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of a photoresist/silicon nitride hard mask/silicon substrate sample according to an embodiment of the present invention;
fig. 3 is a schematic cross-sectional structure diagram of a sample wafer after a passivation step S1 in the silicon nitride etching method according to the embodiment of the present invention;
fig. 4 is a schematic cross-sectional structure diagram of the substrate after the etching step S2 in the silicon nitride etching method according to the embodiment of the present invention;
fig. 5 is a schematic cross-sectional view of the substrate after the cleaning step S3 in the silicon nitride etching method according to the embodiment of the invention;
FIG. 6 is a scanning electron microscope (left: the etching method of the present invention etches 60, 90, 120s from top to bottom; right: the conventional process etches 60, 90, 120s from top to bottom);
table 1 results of etch data for different etch methods.
Detailed Description
The invention is described in further detail below with reference to the figures and the embodiments.
In the traditional silicon nitride etching process, etching gases CHF3, SF6 and the like are alternately introduced into a chamber for one-step etching, and proper conditions are obtained after multiple process adjustments, but the method has low silicon etching selection ratio, so that the problems of small etching window and the like are caused, and the problems of poor pattern transfer precision, impurity pollution, hard mask not being etched through after photoresist is etched due to low photoresist/silicon nitride selection ratio and the like are easily caused. Particularly, when etching contact holes and through holes, a high selectivity of the dielectric layer to silicon is important to avoid etching the underlying material.
To avoid the above problems, the embodiment of the invention performs a three-step silicon nitride etching process as shown in fig. 1.
In this example, a 300nm SiN layer was deposited on a silicon substrate by a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus, and a 5350 photoresist layer was used to pattern the SiN layer by photolithography, and the sample preparation process is shown in FIG. 2.
S1, placing silicon nitride on a silicon substrate, placing photoresist with microstructure patterns on the surface of the silicon nitride, and pre-etching the silicon nitride film with the photoresist as a mask by using an etching machine containing ICP-RF dual power supply to form bulges and grooves on the surface of the silicon nitride film.
S2, introducing 50sccm C in the passivation step4F6。
By C4F6To passivate the gas, not only by C of chain-like molecular structure4F6Can be quickly decomposed to form passivation free radicals and quickly attached to form a passivation film. Meanwhile, the film formed by the chain-shaped molecular structure is easier to be removed by chemical etching, which is beneficial to the cleaning step of S2, and in addition, C4F6Very low greenhouse effect, and C4F8Compared with etching gas, the volume fraction of perfluorinated compounds (PFCs) as greenhouse gases in the exhaust gas can be respectively reduced by 82%, and the method has good environmental friendliness.
The chamber pressure of the etcher is adjusted while this step is performed so that the ambient pressure is 40-80mtorr, which is higher than the pressure set in the pre-cleaning step, so that the (C-F)2 radicals can sufficiently react to form a passivation film.
Then starting ICP power supply 900 and 1100W to fully ionize C4F6To inactivate qi. According to different structures of the carrier plate material and the etching sample device, the RF power supply is adjusted to 10-35W, in the embodiment, the aluminum sheet is used as the carrier plate, and the RF power supply 15W is adjusted to generate 48V DC-bias, so that C-F free radicals can be stably attached to the surface of the substrate to form a passivation film.
In addition, the temperature of the silicon nitride film is maintained at 5-40 ℃, and the excessive temperature can cause the volatilization failure of the product to be unfavorable for the adhesion of the passivation film. Due to C4F6The easy-to-break chain molecular structure can quickly generate a metastable film, so that the passivation time is only 10 s. Fig. 3 is a schematic cross-sectional structure diagram of the sample after the passivation step S1.
S3, in the cleaning step, 45sccm O is introduced2And 10sccm Ar, wherein O2The main cleaning gas can be used for directionally etching the passive film on the vertical surface of the sample after low-pressure ionization, and simultaneously, the side wall passive film is prevented from being stripped. And Ar is used as an auxiliary gas to increase O2The ionization degree and the certain physical etching are provided, so that the residual etching products at the bottom of the deep groove can be bombarded, and the etching roughness is further optimized.
When the step S2 is carried out, the optimal cavity pressure is adjusted to be between 3 and 10mtorr according to the cavity environment of different equipment, so that the etching product can be discharged and the bottom product of the deep groove can be removed, and the influence on the pattern transfer precision caused by the removal of a passivation film on the side wall of the photoresist pattern is avoided.
After the pressure adjustment is finished, the ICP power supply is started for 1000 plus 1500W to ensure that O is2And fully ionizing, and simultaneously adjusting the RF power supply 65W according to different structures of the carrying disc material and the etching sample device to enable the lower electrode to generate a small amount of self-bias voltage, so as to ensure that oxygen plasma is chemically etched in an infiltration mode.
In the embodiment, an aluminum sheet is used as a carrier plate, and 195V DC-bias can be generated by adjusting the RF power supply 65W, so that etching products at the bottom of the trench can be effectively removed, and excessive physical bombardment etching is avoided. According to the etching depth of the sample wafer and the environmental difference of the equipment cavity, the cleaning time can be controlled to be 5-30 s. Fig. 4 is a schematic cross-sectional view of the sample wafer after the cleaning step S3.
S4, in the etching step, 10sccm C is introduced4F6、15sccm CHF3，5sccm SF6。
The three gases all contain F, and F-containing plasma with extremely high concentration can be generated after ionization, so that a high-efficiency chemical etching effect is provided. Wherein C is4F6Has higher C/F ratio, can effectively improve the etching rate of SiN and simultaneously slow down the etching of the photoresist mainly with a C-H structure when being matched properly. When the step is carried out, the chamber pressure of the etching machine is required to be adjusted to enable the ambient pressure to be 15-30mtorr, the etching gas is ensured to be normally started and ionized, high-density F-containing plasma is formed, and the etching speed and uniformity are good.
After the pressure is adjusted, the etching gas can be fully ionized by starting the ICP power source 1100-1300W. According to different structures of a carrying disc material and an etched sample device, an RF power source 40-60W is adjusted, in the embodiment, an aluminum sheet is used as a carrying plate, and an RF power source 55W is adjusted to generate 473V DC-bias, so that plasma in a cavity can move vertically to the surface of a sample, and vertical surface etching of the sample can be effectively performed through directional physical impact without damaging a side wall passivation film.
In addition, the temperature of the substrate is regulated to 5-40 ℃, so that the sharp transverse etching is avoided. The etching step has obvious thermal reaction formation, the leakage rate of the back helium is controlled, 10Torr back helium is used in the experiment, and the leakage rate is controlled to be less than 3 sccm. The specific etching time can be adjusted by the etching rate and the SiN film thickness. The etching rate of the embodiment reaches 214nm/min, and the etching speed reaches 300nmSiN after etching for 1.5 min. Fig. 5 is a schematic cross-sectional structure diagram of the sample wafer after the etching step S3.
FIG. 6 and Table 1 are the electron scanning microscope image of the section of the sample wafer and the data table of the etching measurement for different etching methods.
TABLE 1 results of etch data for different etch methods
Figure BDA0003547953910000051
As can be seen from FIG. 6 and Table 1, the etching method of the present invention can effectively reduce the etching rate of Si and increase the etching rate of Si at the same time3N4The etching rate and the SiN/Si selection ratio are improved from 0.143 to 1.57, so that the lower layer Si can be effectively prevented from being over etched. The photoresist/SiN selection ratio is reduced from 0.35 to 0.14, so that the photoresist scale resistance can be effectively improved.
Therefore, the implementation shows that the three-step silicon nitride etching process improves the pattern transfer precision, the lower layer material selection ratio, the dielectric layer etching rate and the photoresist selection ratio through passivation, cleaning and novel electron gas etching, and effectively avoids the device failure caused by magazine pollution.

Claims (7)

1. A silicon nitride etching method is characterized by comprising the following steps:
s1, passivating: in an etching machine, generating passivation gas plasma by using an RF power supply to attach a passivation layer on the surface of a silicon nitride film, wherein the passivation layer is formed in a bulge and a groove on the surface of the silicon nitride film;
s2, cleaning: in the etching machine, adjusting an RF power supply to generate cleaning gas plasma, and keeping a passivation layer on the side wall of the groove on the surface of the silicon nitride film to ensure that the cleaning gas plasma removes residues on the surface of the silicon nitride film along the vertical direction;
s3, etching: and introducing etching gas, and adjusting process parameters to etch the surface of the silicon nitride film.
2. The silicon nitride etching method according to claim 1, characterized in that:
the silicon nitride film is respectively a photoresist, a silicon nitride layer and a silicon substrate from top to bottom.
3. The silicon nitride etching method according to claim 1, characterized in that:
before step S1, the silicon nitride film masked with the photoresist is also pre-etched using an etcher containing an ICP-RF dual power supply to form projections and grooves on the surface of the silicon nitride film.
4. The silicon nitride etching method according to claim 1, characterized in that:
all the passivating gases are C4F6The cleaning gas is O2And Ar, wherein the etching gas is C4F6、CHF3And SF6The mixed gas of (1).
5. The silicon nitride etching method according to claim 1, characterized in that:
in the passivation step of S1, 50sccm of C is introduced4F6The environmental pressure is adjusted to be 40-80mtorr, the ICP power supply 900-1100W and the RF power supply 10-35W, the temperature of the silicon nitride film is maintained to be 5-40 ℃, and the passivation time is 10 s.
6. The silicon nitride etching method according to claim 1, characterized in that:
in the cleaning step of S2, 45sccm O is introduced2And 10sccm Ar, adjusting the ambient pressure to 3-10mtorr, ICP power supply 1000-.
7. The silicon nitride etching method according to claim 1, characterized in that:
in the etching step of S3, 10sccm C is introduced4F6、15sccm CHF3And 5sccmsF6The ambient pressure is adjusted to 15-30mtorr, the ICP power supply is 1000-1500W, the RF power supply is 40-60W, and the temperature of the silicon nitride film is maintained to 5-40 ℃.
CN202210254276.7A 2022-03-15 2022-03-15 Silicon nitride etching method Pending CN114664653A (en)

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