CN114664352A - Memory circuit and memory programming method - Google Patents

Memory circuit and memory programming method Download PDF

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Publication number
CN114664352A
CN114664352A CN202011547642.5A CN202011547642A CN114664352A CN 114664352 A CN114664352 A CN 114664352A CN 202011547642 A CN202011547642 A CN 202011547642A CN 114664352 A CN114664352 A CN 114664352A
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China
Prior art keywords
programming
voltage
memory
current
predetermined
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CN202011547642.5A
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Chinese (zh)
Inventor
何文乔
柳弼相
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Winbond Electronics Corp
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Winbond Electronics Corp
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Priority to CN202011547642.5A priority Critical patent/CN114664352A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)

Abstract

The invention provides a memory circuit and a memory programming method, which are suitable for programming a flash memory and comprise a charge pump circuit, a charge pump circuit and a memory controller, wherein the charge pump circuit generates a pump voltage and a pump current; a voltage regulator coupled to the charge pump circuit and generating a programming voltage and a programming current according to the pump voltage and the pump current to program the flash memory; a voltage sensor coupled to the voltage regulator to monitor a voltage value of the programming voltage; and a plurality of switch circuits, wherein one end of each switch circuit is coupled with the voltage sensor, the other end of each switch circuit is coupled with the flash memory, and the conducting number of the switch circuits is determined according to the voltage value of the programming voltage.

Description

Memory circuit and memory programming method
Technical Field
The present invention relates to a circuit, and more particularly, to a memory circuit and a memory programming (program) method.
Background
Charge pump circuits and voltage regulators are often used to program flash memories. The charge pump circuit generates a pump voltage and a pump current to the voltage regulator, and the voltage regulator generates a programming voltage and a programming current according to the received pump voltage and pump current to program the flash memory.
However, due to the uncertainty of various combinations of process variations (i.e., process variations), circuit operating temperature variations, and memory leakage currents, when designing a charge pump circuit, it is necessary to design the pump voltage and the pump current provided by the charge pump circuit to be at a predetermined programming voltage in consideration of the uncertainty, so that the charge pump circuit can supply the maximum programming current consumed in the situation where the combination of the uncertainty is the most power consumed in programming.
Such a design of the charge pump circuit increases the cost because the circuit area is too large due to the need to provide a large enough programming current.
Nothing herein is to be construed as an admission that any of the prior art forms part of this disclosure is prior art.
Disclosure of Invention
The invention provides a memory circuit and a memory programming method, wherein a charge pump circuit does not need to take the situation that the combination of the uncertainties occurs in the most power consumption condition as a design consideration, and only needs to take the situation that the combination of the uncertainties occurs in the common condition (typical case) as a design consideration to design the pump voltage and the pump current of the charge pump circuit.
The memory circuit of the present invention is suitable for programming a flash memory, and includes: a charge pump circuit for generating a pump voltage and a pump current; a voltage regulator coupled to the charge pump circuit and generating a programming voltage and a programming current according to the pump voltage and the pump current to program the flash memory; a voltage sensor coupled to the voltage regulator to monitor a voltage value of the programming voltage; and one end of each of the plurality of switch circuits is coupled with the voltage sensor, the other end of each of the plurality of switch circuits is coupled with the flash memory, and the conducting number of the plurality of switch circuits is determined according to the voltage value of the programming voltage.
The memory programming method of the invention is suitable for programming a flash memory, and comprises the following steps: generating a programming voltage and a programming current; setting a plurality of programming paths to be all conducted, and programming the flash memory in the programming pulse period by a programming voltage and a programming current through the plurality of programming paths; monitoring a voltage value of a programming voltage after a programming pulse period is ended; judging whether the programming voltage is greater than or equal to a preset programming voltage or not; comparing the programming voltage with a plurality of preset voltages and generating switching weights of a plurality of programming paths according to the comparison result; selecting a plurality of program paths of the disconnection portion according to the switching weights of the plurality of program paths; and determining whether the program verification is passed.
The memory programming method of the invention is suitable for programming a flash memory, and comprises the following steps: generating a programming voltage and a programming current; setting a plurality of programming paths to be all on, wherein the programming voltage and the programming current pass through the plurality of programming paths, and during the programming pulse: programming the flash memory; monitoring a voltage value of a program voltage; comparing the programming voltage with a plurality of preset voltages and generating switching weights of a plurality of programming paths according to the comparison result; and selecting the plurality of programming paths of the disconnection part according to the switching weights of the plurality of programming paths, and judging whether the programming verification is passed or not after the programming pulse period is ended.
Based on the above, the present invention provides a memory circuit and a memory programming method, which only need to design the pump voltage and the pump current of the charge pump circuit for design consideration under the general condition by combining the above uncertainties, thereby reducing the circuit area and the cost.
In order that the foregoing may be better understood, several embodiments are described in detail below with accompanying figures.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated into and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
FIG. 1 is a diagram illustrating an example of programming a flash memory with a programming voltage and a programming current according to the memory circuit of the present invention;
FIG. 2 is a diagram of respective voltage-current load lines of a charge pump circuit and a voltage regulator in a memory circuit according to the present invention;
FIG. 3 is a diagram showing the relationship between the monitored programming voltage and the programming current when the monitored programming voltage is less than the predetermined programming voltage in the memory circuit of the present invention;
FIG. 4 shows the relationship between the monitored programming voltage and the switch weights of the programming path and the open programming path in the memory circuit of the present invention;
FIG. 5 is a flow chart of a memory programming method according to the present invention;
FIG. 6 is a flow chart of another memory programming method according to the present invention.
Description of the reference numerals
100: a memory circuit;
101: a charge pump circuit;
102: a voltage regulator;
103: flashing;
VPGM: a predetermined programming voltage;
VPUMP: a pump voltage;
G. d, S: a grid electrode, a drain electrode and a source electrode;
ILEAK: average leakage current;
IPGMALL: a total programming current;
VD、VDrain: a programming voltage;
WL [0] to WL [511 ]: a word line;
IPUMP: a pump current;
IPGMCELL0～IPGMCELL7: programming current of the memory cell;
IPGMCELL: average programming current of the memory cell;
IPGM0～IPGM7: a programming current for each programming path;
ILEAK0～ILEAK7: leakage current of each programming path;
IMAX: the maximum current which can be output when the voltage regulator outputs a preset programming voltage;
IPGMALL_TYPICAL: total programming current under normal conditions;
IPGMALL_MAX: total programming current under extreme conditions;
V1-V4: a predetermined voltage;
200. 300, and (2) 300: a programming method;
I2-I4: a current corresponding to a predetermined voltage;
s201 to S207: a step of;
Y0-Y7: a plurality of switching circuits;
s301 to S306: and (5) carrying out the following steps.
Detailed Description
Embodiments of the present disclosure are described below with reference to the drawings.
FIG. 1 shows a memory circuit 100 of the present invention with a predetermined programming voltage VPGMAnd the total programming current IPGMALLAn example of programming the flash memory 103 is shown. The memory circuit 100 includes a charge pump circuit 101 and a voltage regulator 102, the charge pump circuit 101 generating a pump voltage VPUMPAnd the pump current IPUMPTo the voltage regulator 102, the voltage regulator 102 is responsive to the pump voltage VPUMPAnd the pump current IPUMPGenerating a predetermined programming voltage VPGMAnd the total programming current IPGMALLTo flash memory 103 to program flash memory 103.
Flash memory 103 includes 512 rows by 8 columns of memory cells (memory cells) as shown in fig. 1, but not limited thereto, wherein the switch of the memory cell in the nth row is a word line WL [ n-1 ]]Coupled to the gates (Gate, G) of the memory cells in the nth row and controlling the switches of the memory cells in the nth row, the drains (Drain, D) of the memory cells in the mth column share the bit line BL [ m-1 ]](not shown) and receives a predetermined programming voltage V from the memory circuit 100PGM(VPGM≈VD≈VDrain) And programming current I corresponding to memory cell in m-th columnPGM(m-1)Wherein n is an integer of 1 to 512, m is an integer of 1 to 8, and the Source (S) of each memory cell is coupled to a reference voltage (e.g., 0V).
As shown in FIG. 1, when the target cell to be programmed by the memory circuit 100 is the 1 st column of the flash memory 103, WL [0]]Set to high voltage (e.g., 10V), WL [ 1]]～WL[511]Set to low voltage (e.g., 0V), the total programming current I consumed by the flash memory 103PGMALLCan be represented by formula 1.
IPGMALL≈8*(IPGMCELL+511*ILEAK) ... (formula 1), wherein IPGMCELLFor each memory cell (I) in column 1 of flash memory 103PGMCELL0～IPGMCELL7) What is eliminatedAverage value of the programming current consumed, ILEAKThe average value of the leakage current consumed by each of the memory cells in the 2 nd to 512 th rows of the flash memory 103.
The total programming current I consumed by the flash memory 103 according to equation 1PGMALLWill vary depending on the number of memory cells to be programmed by memory circuit 100 and the programming current consumed by and the leakage current of unprogrammed memory cells, which may vary due to uncertainties in various combinations of semiconductor process drift, circuit operating temperature variations, and the like. The total programming current I consumed by the flash memory 103 under normal conditions (e.g., normal temperature, process)PGMALLCan be set as IPGMALL_TYPICALAnd can be set as I under extreme conditions (e.g., extreme power consumption temperature, process)PGMALL_MAX。
Fig. 2 is a diagram of the respective voltage-current load lines of the charge pump circuit 101 and the voltage regulator 102 in the memory circuit 100 according to the present invention. Wherein the pump voltage V generated by the charge pump circuit 101PUMPAnd the pump current IPUMPIn inverse relation, i.e. the pump voltage VPUMPThe larger the pump current IPUMPThe smaller (as shown by the dashed line in fig. 2). The predetermined programming voltage V generated by the voltage regulator 102PGMMay be determined according to design specifications. The voltage-current load line (shown by the dotted line in fig. 2) of the charge pump circuit 101 and the voltage V are the predetermined programming voltage VPGMCurrent value I corresponding to the crossed pointMAXIndicating that the voltage regulator 102 is outputting a predetermined programming voltage VPGMThe maximum current that can be output.
Design goal 1 shown in FIG. 2 indicates that IMAXIs set to IPGMALL_MAXAnd design goal 2 denotes to assign IMAXIs set to IPGMALL_TYPICALDesign goal 1 may be to have the voltage regulator 102 output a predetermined programming voltage VPGMThe current that can be output during the programming process covers the current consumed by the flash memory 103 under all conditions (including the temperature and process of extreme power consumption), and the design objective 2 enables the voltage regulator 102 to output a predetermined programming voltage VPGMTime clockThe current that can be outputted covers the current consumed by the flash memory 103 under the general conditions (general temperature, process), compared to the design target 1, the charge pump circuit 101 of the design target 2 adopted in the present invention does not need to provide the pump current I as large as the design target 1PUMPAnd has a smaller area and lower cost.
Referring to FIGS. 3 and 4, FIG. 3 shows a memory circuit according to the present invention when the program voltage V is monitoredDrainLess than a predetermined programming voltage VPGMWhen (i.e. when I)PGMALL>IMAX＝IPGMALL_TYPICALTime), the monitored programming voltage VDrainAnd the total programming current IPGMALLCorresponding relation of (1), monitored programming voltage VDrainThe purpose is to ensure that the flash memory 103 can be programmed at a predetermined voltage VPGMProgramming is performed.
Y0-Y7 in FIG. 4 are a plurality of switch circuits, one end of each of the plurality of switch circuits Y0-Y7 is coupled to the voltage output terminal of the voltage regulator 102, and the other end of each of the plurality of switch circuits Y0-Y7 is coupled to the bit line BL [0] of the flash memory 103]Bit line BL [7 ]]. The switch circuits Y0-Y7 are coupled to control the switching of the programming paths. A voltage sensor (not shown) including a comparator monitors the programming voltage VDrainThe voltage sensor monitors the programming voltage VDrainBy sensing the programming voltage VDrainAnd output to one input terminal of the comparator, and compare with a plurality of predetermined voltages (e.g., V1, V2, but not limited thereto) at another input terminal of the comparator, and output a comparison result representing the switch weight of each programming path (e.g., two bits of programming path switch weight [1: 0]]But not limited to) to a decoder that switches weights 1:0 according to a programmed path]And outputting control signals to control ends of the switch circuits Y0-Y7 to selectively control whether the switch circuits Y0-Y7 are conducted or not.
FIG. 4 is a table for monitoring programming voltage V for a voltage sensorDrainAnd performs an example of switching control of each program path according to the monitoring result. Setting a predetermined programming voltage VPGMThe predetermined voltage V1 is 7V, and the predetermined voltage V2 is 6V. When the voltage sensor monitors the programming voltage VDrainVoltage of not less than V1(═ 7V), the voltage sensor outputs the programmed path switch weight [1: 0]]＝[00]To the decoder, the decoder switches the weights [1: 0] according to the programming path]＝[00]Outputting control signals to the control terminals of the switch circuits Y0-Y7 to turn on all the switch circuits Y0-Y7, i.e. the total programming current IPGMALL<IMAX＝IPGMALL_TYPICALThe flash memory 103 can be programmed at a voltage greater than or equal to a predetermined programming voltage VPGMIs programmed.
When the voltage sensor monitors the programming voltage VDrainIs between V1 and V2(═ 6V) (i.e., V2)<Programming voltage VDrain<V1), voltage sensor output programmed path switch weights [1: 0]]＝[10]To the decoder, the decoder switches the weights [1: 0] according to the programming path]＝[10]Outputting control signals to control terminals of the plurality of switch circuits Y0-Y7 to turn off part of the switch circuits Y7-Y6 and turn on part of the switch circuits Y0-Y5, in other words, the total programming current I at this timePGMALL>IMAX＝IPGMALL_TYPICALThe flash memory 103 is programmed at a voltage less than a predetermined programming voltage VPGMTo avoid programming errors, the memory circuit 100 must temporarily disconnect some of the programming paths to ensure that the flash memory 103 is programmed at a voltage greater than or equal to the predetermined programming voltage VPGMIs programmed.
When the voltage sensor monitors the programming voltage VDrainIs less than or equal to V2(═ 6V), the voltage sensor outputs a programmed path switch weight [1: 0]]＝[11]To the decoder, the decoder switches the weights [1: 0] according to the programming path]＝[11]Outputting control signals to control terminals of the plurality of switch circuits Y0-Y7 to turn off part of the switch circuits Y7-Y2 and turn on part of the switch circuits Y0-Y1, in other words, the total programming current I at this timePGMALL>IMAX＝IPGMALL_TYPICAL(and the total programming current I at this timePGMALLGreater than programming path switch weight [1:0]＝[10]Total programming current I of timePGMALL) The flash memory 103 is programmed at a voltage less than a predetermined programming voltage VPGMTo avoid programming errors, the memory circuit 100 must temporarily disconnect some of the programming paths to ensure that the flash memory 103 is programmed at a voltage greater than or equal toPredetermined programming voltage VPGMIs programmed.
FIG. 5 is a flow chart of a memory programming method 200 of the present invention, suitable for programming the flash memory 103, comprising: setting all programming paths to be conducted S201; programming the flash memory 103 during the program pulse period S202; after the end of the program pulse period S202, the program voltage V is monitoredDrainS203; judging the programming voltage VDrainWhether it is greater than or equal to the predetermined programming voltage VPGMS204; comparing the programming voltage VDrainGenerating programming path switch weights with a plurality of predetermined voltages S205; selecting a program path S206 of the disconnection part according to the program path switch weight; it is determined whether the flash memory 103 passes the program verification S207.
Fig. 6 shows a flow chart of a memory programming method 300 of the present invention, suitable for programming a flash memory 103, comprising: setting all programming paths to be conducted S301; programming the flash memory 103 during the program pulse period S302; monitoring a programming voltage VDrainS303; comparing the programming voltage VDrainGenerating programming path switch weights with a plurality of predetermined voltages S304; selecting a program path S305 of the disconnection part according to the program path switch weight; after the program pulse period S302 ends, it is determined whether the flash memory 103 passes the program verification S306.
In summary, the memory circuit and the memory programming method of the present invention only need to design the pump voltage and the pump current of the charge pump circuit for design consideration under the general condition by combining the above uncertainties, thereby reducing the circuit area and the cost.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims (12)

1. A memory circuit adapted to program a flash memory, the memory circuit comprising:
a charge pump circuit for generating a pump voltage and a pump current;
a voltage regulator coupled to the charge pump circuit and generating a programming voltage and a programming current according to the pump voltage and the pump current to program the flash memory;
a voltage sensor coupled to the voltage regulator to monitor a voltage value of the programming voltage; and
and one end of each of the plurality of switch circuits is coupled to the voltage sensor, the other end of each of the plurality of switch circuits is coupled to the flash memory, and the conducting number of the plurality of switch circuits is determined according to the voltage value of the programming voltage.
2. The memory circuit of claim 1 wherein the pump voltage generated by the charge pump circuit is inversely proportional to the pump current.
3. The memory circuit of claim 1, wherein the one terminal of each of the plurality of switch circuits is coupled to the voltage regulator and the other terminal is coupled to a different bit line of the flash memory.
4. The memory circuit of claim 1, wherein the number of turns on of the plurality of switch circuits is proportional to the voltage value of the programming voltage.
5. The memory circuit of claim 1, wherein the voltage sensor comprises a comparator that compares the voltage value of the programming voltage with a plurality of predetermined voltages to generate a comparison result, the voltage sensor generating switching weights for the plurality of switching circuits according to the comparison result.
6. The memory circuit of claim 5, wherein the plurality of predetermined voltages includes a predetermined programming voltage and a first predetermined voltage, and the predetermined programming voltage is greater than the first predetermined voltage, the voltage sensor generates a first switching weight when the programming voltage is greater than or equal to the predetermined programming voltage, the voltage sensor generates a second switching weight when the programming voltage is less than the predetermined programming voltage and greater than the first predetermined voltage, and the voltage sensor generates a third switching weight when the programming voltage is less than or equal to the first predetermined voltage.
7. The memory circuit of claim 6, wherein the plurality of switch circuits determines the number of turns on based on the switch weights.
8. The memory circuit of claim 7, wherein all of the plurality of switching circuits are turned on when the voltage sensor generates the first switching weight.
9. The memory circuit of claim 7, wherein the plurality of switch circuits conduct a first number of conduction when the voltage sensor generates the second switch weight, and the plurality of switch circuits conduct a second number of conduction when the voltage sensor generates the third switch weight, the first number of conduction being greater than the second number of conduction.
10. The memory circuit of claim 5, further comprising a decoder for generating a control signal to a control terminal of each of the plurality of switching circuits according to the switching weights.
11. A memory programming method, suitable for programming a flash memory, includes:
generating a programming voltage and a programming current;
setting a plurality of programming paths to be all on, wherein the programming voltage and the programming current program the flash memory during a programming pulse through the plurality of programming paths;
after the end of the programming pulse period,
monitoring a voltage value of the programming voltage;
determining whether the programming voltage is greater than or equal to a predetermined programming voltage;
comparing the programming voltage with a plurality of predetermined voltages and generating switching weights of the plurality of programming paths according to the comparison result;
selecting the plurality of programming paths of the turn-off portion according to the switching weights of the plurality of programming paths; and
it is determined whether the program verification is passed.
12. A memory programming method, suitable for programming a flash memory, includes:
generating a programming voltage and a programming current;
setting a plurality of programming paths to be all on, the programming voltage and the programming current flowing through the plurality of programming paths, during a programming pulse:
programming the flash memory;
monitoring a voltage value of the programming voltage;
comparing the programming voltage with a plurality of preset voltages and generating switching weights of the plurality of programming paths according to the comparison result; and
selecting the plurality of programming paths for the off portion based on the switching weights for the plurality of programming paths, an
After the programming pulse period is over, whether the programming verification is passed is judged.
CN202011547642.5A 2020-12-23 2020-12-23 Memory circuit and memory programming method Pending CN114664352A (en)

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Application Number Priority Date Filing Date Title
CN202011547642.5A CN114664352A (en) 2020-12-23 2020-12-23 Memory circuit and memory programming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011547642.5A CN114664352A (en) 2020-12-23 2020-12-23 Memory circuit and memory programming method

Publications (1)

Publication Number Publication Date
CN114664352A true CN114664352A (en) 2022-06-24

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