CN114662443A - Integrated circuit layout design method, device and readable storage medium - Google Patents
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Abstract
The invention relates to a method, a device and a readable storage medium for designing integrated circuit layout, firstly generating a grid, wherein the grid comprises a plurality of grid points; converting the grid into a matrix, wherein each grid point corresponds to an element of the matrix; judging whether each grid point falls in the layout range of the integrated circuit; if so, setting the value of the corresponding element as true; and designating all elements with true numerical values as an original layout matrix, wherein the original layout matrix carries the integrated circuit information. The invention can quickly and efficiently obtain the operation result of the geometric figure.
Description
Technical Field
The present invention relates generally to the field of semiconductors. More particularly, the present invention relates to an integrated circuit layout design method, apparatus and readable storage medium.
Background
The chip design is mainly divided into two major stages: a logical design of the front-end design and a physical design of the back-end design. The front end design is to obtain a gate-level netlist circuit of the chip to realize a specific function; the physical design is generally based on GDSII standard layout description language, and a binary format is adopted to convert a gate-level netlist circuit into layout geometric figures, topological relations, structures, layers and other information, and the gate-level netlist circuit can be manufactured into an integrated circuit in a wafer form only by the information.
In the physical design phase, layout geometry is used in many programs, for example, when a design rule is applied, all the geometries in the layout are compared with the size and the spacing specified by the design rule, and the developer is informed of all the places where the rule is violated to make an adjustment. And for example, when the delay operation of the circuit is evaluated, the calculation is also carried out based on the layout geometry. In addition, the floorplanning also needs to arrange the chip size, input and output, etc. based on the layout geometry.
Therefore, a method of calculating the geometry of an integrated circuit is highly desirable.
Disclosure of Invention
In order to at least partially solve the technical problems mentioned in the background, the invention provides an integrated circuit layout design method, an integrated circuit layout design device and a readable storage medium.
In one aspect, the present invention discloses a method for designing an integrated circuit layout, comprising: generating a grid, the grid comprising a plurality of grid points; converting the grid into a matrix, wherein each grid point corresponds to an element of the matrix; judging whether each grid point falls in the layout range of the integrated circuit; if so, setting the value of the corresponding element to be true; and designating all elements with true values as an original layout matrix, wherein the original layout matrix carries the integrated circuit information.
In another aspect, the present invention discloses a computer readable storage medium having stored thereon computer program code for obtaining geometry information of a circuit layout, which when executed by a processor performs the aforementioned method.
In another aspect, the present invention discloses an apparatus for designing an integrated circuit layout, which includes a generating module, a converting module, a determining module, a setting module and a designating module. The generation module is used for generating a grid, and the grid comprises a plurality of grid points; the conversion module is used for converting the grids into a matrix, and each grid point corresponds to an element of the matrix; the judging module is used for judging whether each lattice point falls in the layout range of the integrated circuit; the setting module is used for setting the numerical value of the corresponding element as true when the lattice point falls in the layout range; the specifying module is configured to specify all elements with true values as an original layout matrix, where the original layout matrix carries the information of the integrated circuit.
The invention converts the geometric figure of the integrated circuit into a matrix, presents the geometric space in a matrix mode, and can quickly and efficiently obtain the operation result of the geometric figure based on the correlation algorithm of the figure calculation of the matrix operation.
Drawings
The above and other objects, features and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. In the accompanying drawings, several embodiments of the present invention are illustrated by way of example and not by way of limitation, and like reference numerals designate like or corresponding parts throughout the several views, in which:
FIG. 1 is a grid showing an EDA tool;
FIG. 2 is a flow chart illustrating an integrated circuit layout design method of an embodiment of the present invention;
FIG. 3 is a diagram illustrating the conversion of grid points into matrix elements according to an embodiment of the invention;
FIG. 4 is a schematic diagram showing an exemplary integrated circuit in a grid;
FIG. 5 is a diagram illustrating matrix element values for an embodiment of the invention;
FIG. 6 is a flow chart illustrating a method of integrated circuit layout design according to another embodiment of the present invention;
FIG. 7 is a diagram illustrating the original layout matrix of another embodiment of the present invention shifted to the right by one grid point on the grid;
FIG. 8 is a schematic diagram showing the geometry of a second layout matrix of another embodiment of the present invention;
FIG. 9 is a schematic diagram showing the geometry of a third layout matrix of another embodiment of the present invention;
FIG. 10 is a schematic diagram illustrating the geometry of a fifth layout matrix of another embodiment of the present invention;
FIG. 11 is a schematic diagram illustrating the geometry of a fourth layout matrix of another embodiment of the present invention;
FIG. 12 is a schematic diagram showing the geometry of a sixth layout matrix of another embodiment of the present invention; and
fig. 13 is a block diagram showing an integrated circuit layout designing apparatus according to another embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be understood that the terms "first", "second", "third" and "fourth", etc. in the claims, the description and the drawings of the present invention are used for distinguishing different objects and are not used for describing a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification and claims of this application, the singular form of "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this specification refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.
As used in this specification and claims, the term "if" may be interpreted contextually as "when.. or" once "or" in response to a determination "or" in response to a detection ".
The following detailed description of embodiments of the invention refers to the accompanying drawings.
Nowadays, the chip design is assisted by an EDA tool, which is an electronic design automation system and is used to implement software for compiling, simplifying, dividing, laying out, optimizing logic and the like. As shown in fig. 1, the display page of each EDA tool is provided with a grid 100, the grid 100 including a plurality of grid points 101 so that a developer can align and lay out a circuit, the grid 100 being a process manufacturing grid, a standard cell layout grid, a routing channel grid, or a custom grid.
One embodiment of the invention is an integrated circuit layout design method for obtaining geometry of an integrated circuit layout as a reference for subsequent physical design. Fig. 2 shows a flow chart of this embodiment.
In step 201, a mesh is generated. The grid referred to herein, i.e., grid 100 of fig. 1, may be a process-manufacturing grid, a standard cell layout grid, a routing channel grid, or a custom grid that forms an array that includes a plurality of grid points 101.
In step 202, the grid is converted into a matrix, with each grid point corresponding to an element of the matrix. The grid 100 of fig. 1 is a square matrix, and each grid point 101 can be considered as an element of one matrix. This embodiment matrixes the grid and encodes each grid point according to the rules of the matrix, e.g. element a of the matrixxyWhere subscript x represents the coordinate value of a grid point along the x-axis and subscript y represents the coordinate value of a grid point along the y-axis, as shown in FIG. 3, grid point 301 is the matrix element a11The grid point 302 is the matrix element a21The grid point 303 is the matrix element a12And so on.
In step 203, it is determined whether each grid point falls within the layout range of the integrated circuit. In an EDA tool, the layout of an integrated circuit is based on this grid, and fig. 4 shows a schematic diagram of an exemplary integrated circuit in the grid, the layout area 401 of the integrated circuit being the planar area of the integrated circuit. In this step, it is determined whether each grid point falls within the layout area 401 of the integrated circuit, i.e., the black area in the figure.
If so, step 204 is executed to set the value of the corresponding element to true. The element value "1" is denoted as true in this embodiment. If not, step 205 is executed to set the value of the corresponding element to false, in this embodiment, the value "0" of the element indicates false. After steps 204 and 205 are completed, the whole matrix is shown in fig. 5, and the values of the elements falling within the layout range of the integrated circuit are 1, and the rest are 0.
Next, in step 206, all elements whose values are true are designated as the original layout matrix, i.e., the original layout matrix 501 in fig. 5, and the original layout matrix 501 carries information of the integrated circuit, in particular, information of the geometric figure.
The embodiment converts the geometry of the integrated circuit into a matrix, and presents the geometry space in the form of the matrix as the basis for the subsequent procedures in the physical design stage.
Another embodiment of the present invention is an integrated circuit layout design method for obtaining geometry of an integrated circuit layout, and in particular for obtaining edge information of the integrated circuit layout for reference in a subsequent physical design. Fig. 6 shows a flowchart of this embodiment.
In step 601, a mesh is generated. In step 602, the grid is converted into a matrix, with each grid point corresponding to an element of the matrix. In step 603, it is determined whether each grid point falls within the layout range of the integrated circuit. If so, step 604 is executed to set the value of the corresponding element to true, in this embodiment the value "1" of the element is indicated as true. If not, go to step 605 to set the value of the corresponding element to false, in this embodiment, the element value "0" indicates false. Next, in step 606, all elements whose values are true are designated as an original layout matrix, which carries the geometry information of the integrated circuit. Steps 601 to 606 are the same as steps 201 to 206, and are not repeated.
In step 607, the original layout matrix is shifted one grid point to one side on the grid to form a first layout matrix. Fig. 7 shows a schematic diagram of the original layout matrix 501 moving one grid point to the right on the grid, forming a first layout matrix 701, where the geometry of the first layout matrix 701 is identical to that of the original layout matrix 501, except that the first layout matrix 701 is a new layout matrix formed by moving one grid point to the right of the original layout matrix 501. For the first layout matrix 701, only the elements within the first layout matrix 701 are 1, and the rest are 0.
In step 608, the original layout matrix 501 and the first layout matrix 701 are bitwise arranged to form a second layout matrix. Fig. 8 shows the geometry of the second layout matrix 801, which is the union of the original layout matrix 501 and the first layout matrix 701, where the black elements have a value of 1 and the rest are 0.
In step 609, the second layout matrix 801 and the original layout matrix 501 are xored in bits to form a third layout matrix. The bitwise exclusive-or operation represents that the intersection of the second layout matrix 801 and the original layout matrix 501 is set to 0, and the non-intersection of the second layout matrix 801 and the original layout matrix 501 is set to 1. Fig. 9 shows the geometry of the third layout matrix 901, and the third layout matrix 901 carries the geometric periphery information on the right side of the layout range (i.e. the original layout matrix 501) of the integrated circuit, and the black elements in the figure have values of 1, and the rest are 0. To this end, the embodiment obtains the geometric outer edge information on the right side of the layout range.
In step 610, the third layout matrix 901 is shifted by one grid point on the grid to the opposite direction of the side to form a fifth layout matrix. For a grid point shift to the right in step 607, this step is to shift a grid point to the left, as shown in fig. 10, forming a fifth layout matrix 1001, which carries the geometric inner edge information of the side.
In step 611, it is determined whether all sides have the geometric periphery information. If not, returning to 607, the original layout matrix 501 is shifted by one grid point to the other side on the grid, and goes through steps 608, 609 and 610 to obtain the geometric inner and outer edge information of the other side of the layout range of the integrated circuit. Until the information of the inner and outer edges of the geometry at the four sides of the layout range is obtained.
If all sides have the geometric periphery information, step 612 is performed to form a fourth layout matrix by bit or all of the third layout matrices 901. Fig. 11 shows a fourth layout matrix 1101, which carries geometric peripheral length information of the circuit layout.
Finally, step 613 is performed to bitwise or all of the fifth layout matrix 1001 to form a sixth layout matrix, which is shown in fig. 12 as 1201 and which carries information about the geometric inner perimeter of the circuit layout.
In this embodiment, the geometry of the integrated circuit is converted into a matrix, and the information of the geometry of the inner and outer edges of each side and the geometry of the inner and outer circumferences of the integrated circuit is obtained respectively as the basis for the subsequent procedures in the physical design stage. The following will illustrate how the aforementioned geometry information is used in the physical design phase.
The original layout matrix 501 may be summed directly if area information for the integrated circuit is needed in the physical design stage. The area of each grid point is known, and the area of the original layout matrix 501 can be obtained by multiplying the area of each grid point by counting the number of elements (i.e., the number of elements whose value is 1) in the original layout matrix 501.
If the integrated circuit needs to be scaled up in the physical design stage, the seventh layout matrix is formed by first pressing bits or the original layout matrix 501 and the fourth layout matrix 1101, and then the seventh layout matrix is updated to the original layout matrix 501, so that the original layout matrix 501 is expanded by one grid point to four sides, and steps 607 to 612 are performed based on the updated original layout matrix 501 to form the updated fourth layout matrix. This cycle successively enlarges the original layout matrix 501.
If the integrated circuit needs to be scaled down in the physical design stage, the original layout matrix 501 and the sixth layout matrix 1201 are xored by bits to form an eighth layout matrix, the eighth layout matrix is updated to the original layout matrix 501, so that the original layout matrix 501 is scaled inward by one grid point from four sides, and steps 607 to 613 are performed based on the updated original layout matrix 501 to form the updated sixth layout matrix 1201. This cycle can successively reduce the original layout matrix 501.
If the integrated circuit needs to be flipped clockwise or counterclockwise in the physical design stage, the original layout matrix 501 is transposed and then flipped horizontally, so that a clockwise flipped result can be obtained, and the original layout matrix 501 is transposed and then flipped vertically, so that a counterclockwise flipped result can be obtained.
If it is necessary to determine whether two integrated circuits intersect in the physical design stage, steps 601 to 606 are performed for the two integrated circuits, so as to form a first original layout matrix and a second original layout matrix, respectively, and then the two integrated circuits are bitwise connected with the first original layout matrix and the second original layout matrix to form an intersecting matrix, and then it is determined whether an element with a value of 1 exists in the intersecting matrix, if so, the two integrated circuits intersect, and if not, the two integrated circuits do not intersect.
If it is necessary to determine whether an integrated circuit is included in another integrated circuit in the physical design stage, steps 601 to 606 are performed for the two integrated circuits to form a first original layout matrix and a second original layout matrix, respectively, then bitwise or the first original layout matrix and the second original layout matrix are performed to form a union matrix, then bitwise xoring the first original layout matrix and the union layout matrix is performed to form a first xor matrix, then it is determined whether an element with a value of 1 exists in the first xor matrix, if so, the first original layout matrix does not include the second original layout matrix, and if not, the first original layout matrix includes the second original layout matrix. Otherwise, the second original layout matrix is subjected to bitwise XOR and the union layout matrix to form a second XOR matrix, and whether an element with the value of 1 exists in the second XOR matrix is judged, if so, the second original layout matrix does not contain the first original layout matrix, and if not, the second original layout matrix contains the first original layout matrix.
If the intersection graph of two integrated circuits is needed to be obtained in the physical design stage, steps 601 to 606 are executed for the two integrated circuits first, so as to form a first original layout matrix and a second original layout matrix respectively, and then the first original layout matrix and the second original layout matrix are bitwise combined to form an intersection matrix, wherein the intersection matrix is the intersection graph of the two integrated circuits.
If a union graph of two integrated circuits is needed to be obtained in the physical design stage, steps 601 to 606 are performed for the two integrated circuits, respectively forming a first original layout matrix and a second original layout matrix, and then forming a union matrix by bit or the first original layout matrix and the second original layout matrix, where the union matrix is the union graph of the two integrated circuits.
If a graph of subtracting another integrated circuit from one integrated circuit is required to be obtained in the physical design stage, steps 601 to 606 are executed for the two integrated circuits, respectively forming a first original layout matrix and a second original layout matrix, bitwise or the first original layout matrix and the second original layout matrix to form a union matrix, and bitwise xoring the second original layout matrix and the union layout matrix to form an xor matrix, wherein the xor matrix is the geometric graph of subtracting the second integrated circuit from the first integrated circuit.
The above are only examples, and according to the geometric figures of the inner and outer edges and the geometric inner and outer circumferences obtained by the flow of fig. 6 in this embodiment, all the geometric information required in the physical design stage can be obtained through appropriate logical operations.
Another embodiment of the present invention is an integrated circuit layout design apparatus for obtaining geometry of an integrated circuit layout, and in particular for obtaining edge information of the integrated circuit layout for reference in a subsequent physical design. Fig. 13 shows a schematic structural diagram of this embodiment, the apparatus 1300 includes a generating module 1301, a converting module 1302, a determining module 1303, a setting module 1304, a specifying module 1305, a shifting module 1306, an operation module 1307, and a summing module 1308, where each module transmits a signal through a bus 1309. The integrated circuit layout apparatus of the present invention shown in FIG. 13 can be integrated into a layout and routing tool such as an EDA tool.
The generation module 1301 is used to generate a mesh. The grid referred to herein may be a process manufacturing grid, a standard cell layout grid, a routing channel grid, or a custom grid that forms an array that includes a plurality of grid points.
The conversion module 1302 is configured to convert the grid into a matrix, eachThe grid points correspond to elements of the matrix. Each lattice point 101 can be considered as an element of a matrix, and the transformation module 1302 matrixing the grid and encoding each lattice point according to the rule of the matrix, for example, the element a of the matrixxyWhere subscript x represents the coordinate value of a grid point along the x-axis and subscript y represents the coordinate value of a grid point along the y-axis.
The determining module 1303 is used for determining whether each grid point falls within the layout range of the integrated circuit. In the EDA tool, the layout of the integrated circuit is performed based on the aforementioned grid, and the determining module 1303 determines whether each grid point falls within the layout range of the integrated circuit.
When the grid point falls within the layout range, the setting module 1304 is used to set the value of the corresponding element to true, in this embodiment, the value "1" of the element is indicated as true. When the grid point does not fall within the layout range, the setting module 1304 is used to set the value of the corresponding element to false, in this embodiment, the value "0" of the element is represented as false. That is, the elements of the entire matrix have a value of 1 falling within the layout range of the integrated circuit, and the remainder are 0.
The designating module 1305 is configured to designate all elements with true values as an original layout matrix, and the original layout matrix carries the ic information.
The shift module 1306 is configured to shift the original layout matrix by one grid point on the grid to a side to form a first layout matrix. The shifting module 1306 makes the original layout matrix shift one grid point on the grid to the upper, lower, left and right sides, respectively, to form 4 first layout matrices, each corresponding to one side. The first layout matrix has the same geometry as the original layout matrix, except that the first layout matrix is a new layout matrix formed by moving one grid point to one side of the original layout matrix.
The operation module 1307 is used for forming a second layout matrix by bit or the original layout matrix and the first layout matrix. The operation module 1307 generates 4 second layout matrices based on the 4 first layout matrices, where each second layout matrix corresponds to one side, and the second layout matrix is a union of the original layout matrix and the first layout matrix.
The operation module 1307 then xors the second layout matrix and the original layout matrix in terms of bits to form a third layout matrix, where the third layout matrix carries the geometric periphery information of the side. The operation module 1307 sets the intersection element of the second layout matrix and the original layout matrix to 0, and sets the non-intersection element of the second layout matrix and the original layout matrix to 1, so as to form 4 third layout matrices, where each third layout matrix corresponds to one side. To this end, the embodiment obtains the geometric periphery information of the four sides of the layout range.
The determining module 1303 further determines whether all sides obtain the geometric edge information. If not, the notification shift module 1306 moves the original layout matrix by one grid point on the grid to the side where the geometric outer edge information is not obtained, so that the operation module 1307 obtains the geometric inner and outer edge information of the side. Until the information of the inner and outer edges of the geometry at the four sides of the layout range is obtained.
If all sides have the geometric periphery information, the operation module 1307 performs bitwise or all of the third layout matrices to form a fourth layout matrix, which carries the geometric periphery length information of the circuit layout.
The shifting module 1306 continues to shift all the third layout matrices by one grid point on the grid in the opposite direction of the side, so as to form 4 fifth layout matrices, each of which carries geometric inner edge information of the side.
The shifting module 1306 further shifts or shifts the fifth layout matrix to form a sixth layout matrix, which carries geometric inner perimeter information of the circuit layout.
The summing module 1308 is used to sum the elements of the original layout matrix to obtain the geometric area information of the circuit layout. The area of each grid point is known, and the summing module 1308 can obtain the area of the original layout matrix by simply counting the number of elements in the original layout matrix (i.e., the number of elements having a value of 1) and multiplying the area of each grid point.
Another embodiment of the invention is a computer-readable storage medium having stored thereon computer program code for obtaining geometry information of a circuit layout, which, when executed by a processor, performs the method of the embodiments as described above. In some implementation scenarios, the integrated units may be implemented in the form of software program modules. If implemented in the form of software program modules and sold or used as a stand-alone product, the integrated units may be stored in a computer readable memory. In this regard, when the aspects of the present invention are embodied in a software product (e.g., a computer-readable storage medium), the software product may be stored in a memory, which may include instructions for causing a computer device (e.g., a personal computer, a server, or a network device, etc.) to perform some or all of the steps of the methods described in the embodiments of the present invention. The Memory may include, but is not limited to, a usb disk, a flash disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.
The invention converts the geometric figure of the integrated circuit into a matrix, respectively obtains the information of the geometric figures of the inner edge and the outer edge of each side and the geometric inner and outer circumferences of the integrated circuit, and can efficiently execute chip design as the basis of subsequent programs in the physical design stage.
It is noted that for the sake of simplicity, the present invention sets forth some methods and embodiments thereof as a series of acts or combinations thereof, but those skilled in the art will appreciate that the inventive arrangements are not limited by the order of acts described. Accordingly, persons skilled in the art may appreciate that certain steps may be performed in other sequences or simultaneously, in accordance with the disclosure or teachings of the invention. Further, those skilled in the art will appreciate that the described embodiments of the invention are capable of being practiced in other alternative embodiments that may involve fewer acts or modules than are necessary to practice one or more aspects of the invention. In addition, the description of some embodiments of the present invention is also focused on different schemes. In view of this, those skilled in the art will understand that portions of the present invention that are not described in detail in one embodiment may also refer to related descriptions of other embodiments.
In particular implementations, based on the disclosure and teachings of the present invention, one of ordinary skill in the art will appreciate that the several embodiments disclosed herein can be practiced in other ways not disclosed herein. For example, as for the units in the foregoing embodiments of the electronic device or apparatus, the units are split based on the logic function, and there may be another splitting manner in the actual implementation. Also for example, multiple units or components may be combined or integrated with another system or some features or functions in a unit or component may be selectively disabled. The connections discussed above in connection with the figures may be direct or indirect couplings between the units or components in terms of connectivity between the different units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection utilizing an interface, where the communication interface may support electrical, optical, acoustic, magnetic, or other forms of signal transmission.
In the present invention, units described as separate parts may or may not be physically separate, and parts shown as units may or may not be physical units. The aforementioned components or units may be co-located or distributed over multiple network elements. In addition, according to actual needs, part or all of the units can be selected to achieve the purpose of the scheme of the embodiment of the invention. In addition, in some scenarios, multiple units in an embodiment of the present invention may be integrated into one unit or each unit may exist physically separately.
In other implementation scenarios, the integrated unit may also be implemented in hardware, that is, a specific hardware circuit, which may include a digital circuit and/or an analog circuit, etc. The physical implementation of the hardware structure of the circuit may include, but is not limited to, physical devices, which may include, but are not limited to, transistors or memristors, among other devices. In this regard, the various devices described herein (e.g., computing devices or other processing devices) may be implemented by suitable hardware processors, such as central processing units, GPUs, FPGAs, DSPs, ASICs, and the like. Further, the aforementioned storage unit or storage device may be any suitable storage medium (including magnetic storage medium or magneto-optical storage medium, etc.), and may be, for example, a variable Resistive Memory (RRAM), a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), an Enhanced Dynamic Random Access Memory (EDRAM), a High Bandwidth Memory (HBM), a Hybrid Memory Cube (HMC), a ROM, a RAM, or the like.
The foregoing may be better understood in light of the following clauses:
clause a1, a method of designing an integrated circuit layout, comprising: generating a grid, the grid comprising a plurality of grid points; converting the grid into a matrix, wherein each grid point corresponds to an element of the matrix; judging whether each grid point falls within the layout range of the integrated circuit; if so, setting the value of the corresponding element as true; and designating all elements with true values as an original layout matrix, wherein the original layout matrix carries the integrated circuit information.
Clause a2, the method of clause a1, further comprising: moving the original layout matrix to one side on the grid by one grid point to form a first layout matrix; forming a second layout matrix by bit or the original layout matrix and the first layout matrix; and bitwise exclusive-oring the second layout matrix and the original layout matrix to form a third layout matrix, wherein the third layout matrix carries the geometric outer edge information of the side.
Clause A3, the method of clause a2, wherein the moving, bitwise or and bitwise xor steps are performed on three additional sides, the method further comprising: and forming a fourth layout matrix according to the positions or all of the third layout matrixes, wherein the fourth layout matrix carries the geometric peripheral length information of the circuit layout.
Clause a4, the method of clause a2, further comprising: and moving the third layout matrix to a grid point on the grid in the opposite direction of the side to form a fifth layout matrix, wherein the fifth layout matrix carries the geometric inner edge information of the side.
Clause a5, the method of clause a4, wherein the moving, bitwise or, bitwise xor, and reverse moving steps are performed on three additional sides, the method further comprising: and forming a sixth layout matrix according to the positions or all of the fifth layout matrixes, wherein the sixth layout matrix carries the geometric inner perimeter information of the circuit layout.
Clause a6, the method of clause a1, further comprising: summing elements of the original layout matrix to obtain geometric area information of the circuit layout.
Clause a7, the method of clause a1, wherein the grid is one of a process manufacturing grid, a standard cell placement grid, a routing channel grid, and a custom grid.
Clause A8, a computer-readable storage medium having stored thereon computer program code for obtaining geometry information for a circuit layout, the computer program code, when executed by a processor, performing the method of any of clauses a 1-7.
Clause a9, an integrated circuit layout design apparatus, comprising: a generation module to generate a grid, the grid comprising a plurality of grid points; a conversion module for converting the grid into a matrix, each grid point corresponding to an element of the matrix; the judging module is used for judging whether each grid point falls in the layout range of the integrated circuit; the setting module is used for setting the numerical value of the corresponding element to be true when the lattice point falls in the layout range; and a specifying module for specifying all elements whose values are true as an original layout matrix, the original layout matrix carrying the integrated circuit information.
Clause a10, the apparatus of clause a9, further comprising: a shifting module, configured to shift the original layout matrix to one side on the grid by one grid point to form a first layout matrix; and an operation module for: forming a second layout matrix by bit or the original layout matrix and the first layout matrix; and bitwise exclusive-oring the second layout matrix and the original layout matrix to form a third layout matrix, wherein the third layout matrix carries the geometric outer edge information of the side.
Clause a11, the apparatus of clause a10, wherein the shifting module shifts the original layout matrices by one grid point on three other sides respectively, the arithmetic module performs the bitwise or operation and the bitwise xor operation to form three other third layout matrices respectively, and bitwise or all of the third layout matrices to form a fourth layout matrix carrying geometric perimeter length information of the circuit layout.
Clause a12, the apparatus of clause a10, wherein the shift module shifts the third layout matrix by one grid point on the grid in a direction opposite to the side to form a fifth layout matrix, the fifth layout matrix carrying geometric inner edge information of the side.
Clause a13, the apparatus of clause a12, wherein the shifting module shifts the original layout matrices by one grid point on three other sides respectively, the arithmetic module performs the bitwise or operation and the bitwise xor operation to form three other fifth layout matrices respectively, and bitwise or all of the fifth layout matrices to form a sixth layout matrix carrying geometric inner perimeter length information of the circuit layout.
Clause a14, the apparatus of clause a9, further comprising: a summing module to sum elements of the original layout matrix to obtain geometric area information of the circuit layout.
Clause a15, the apparatus of clause a9, wherein the grid is one of a process manufacturing grid, a standard cell placement grid, a routing channel grid, and a custom grid.
The above embodiments of the present invention are described in detail, and the principle and the implementation of the present invention are explained by applying specific embodiments, and the above description of the embodiments is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (15)
1. An integrated circuit layout design method, comprising:
generating a grid, wherein the grid comprises a plurality of grid points;
converting the grid into a matrix, wherein each grid point corresponds to an element of the matrix;
judging whether each grid point falls within the layout range of the integrated circuit;
if so, setting the value of the corresponding element to be true; and
and designating all elements with true numerical values as an original layout matrix, wherein the original layout matrix carries the integrated circuit information.
2. The method of claim 1, further comprising:
moving the original layout matrix to one side on the grid by one grid point to form a first layout matrix;
forming a second layout matrix by bit or the original layout matrix and the first layout matrix; and
and carrying out bitwise exclusive-or on the second layout matrix and the original layout matrix to form a third layout matrix, wherein the third layout matrix carries the geometric outer edge information of the side.
3. The method of claim 2, wherein the moving, bitwise or and bitwise exclusive OR steps are performed on three additional sides, the method further comprising:
and forming a fourth layout matrix according to the positions or all of the third layout matrixes, wherein the fourth layout matrix carries the geometric peripheral length information of the circuit layout.
4. The method of claim 2, further comprising:
and moving the third layout matrix to a grid point on the grid in the opposite direction of the side to form a fifth layout matrix, wherein the fifth layout matrix carries the geometric inner edge information of the side.
5. The method of claim 4, wherein the moving, bitwise OR, bitwise XOR, and reverse direction moving steps are performed on three additional sides, the method further comprising:
and forming a sixth layout matrix according to the positions or all of the fifth layout matrices, wherein the sixth layout matrix carries the geometric inner perimeter information of the circuit layout.
6. The method of claim 1, further comprising:
summing elements of the original layout matrix to obtain geometric area information of the circuit layout.
7. The method of claim 1, wherein the grid is one of a process manufacturing grid, a standard cell placement grid, a routing channel grid, and a custom grid.
8. A computer readable storage medium having stored thereon computer program code for obtaining geometrical information of a circuit layout, which computer program code, when executed by a processor, performs the method of any of claims 1-7.
9. An integrated circuit layout design apparatus, comprising:
a generation module to generate a grid, the grid comprising a plurality of grid points;
a conversion module for converting the grid into a matrix, each grid point corresponding to an element of the matrix;
the judging module is used for judging whether each grid point falls in the layout range of the integrated circuit;
the setting module is used for setting the numerical value of the corresponding element to be true when the lattice point falls in the layout range; and
and the specifying module is used for specifying all elements with real numerical values as an original layout matrix, and the original layout matrix carries the integrated circuit information.
10. The apparatus of claim 9, further comprising:
a shifting module, configured to shift the original layout matrix to one side on the grid by one grid point to form a first layout matrix; and
an operation module, for:
forming a second layout matrix by bit or the original layout matrix and the first layout matrix; and
and carrying out bitwise exclusive-or on the second layout matrix and the original layout matrix to form a third layout matrix, wherein the third layout matrix carries the geometric outer edge information of the side.
11. The apparatus of claim 10, wherein the shifting module shifts the original layout matrices by one grid point on three other sides, respectively, the arithmetic module performs the bitwise or operation and the bitwise xor operation to form three other third layout matrices, respectively, and bitwise or all of the third layout matrices to form a fourth layout matrix carrying geometric perimeter length information of the circuit layout.
12. The apparatus of claim 10, wherein the shifting module shifts the third layout matrix by one grid point on the grid in a direction opposite to the side to form a fifth layout matrix, the fifth layout matrix carrying geometric inner edge information of the side.
13. The apparatus of claim 12, wherein the shifting module shifts the original layout matrices by one grid point on three other sides respectively, the arithmetic module performs the bitwise or operation and the bitwise xor operation to form three other fifth layout matrices respectively, and bitwise or all of the fifth layout matrices to form a sixth layout matrix carrying geometric inner perimeter length information of the circuit layout.
14. The apparatus of claim 9, further comprising:
and the summation module is used for summing the elements of the original layout matrix to obtain the geometric area information of the circuit layout.
15. The apparatus of claim 9, wherein the grid is one of a process manufacturing grid, a standard cell layout grid, a routing channel grid, and a custom grid.
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