CN114661364A - Starting method and device of co-processing chip, storage medium and electronic device - Google Patents
Starting method and device of co-processing chip, storage medium and electronic device Download PDFInfo
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- 238000004590 computer program Methods 0.000 claims description 21
- 230000005540 biological transmission Effects 0.000 claims description 11
- 238000007726 management method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- 230000006870 function Effects 0.000 description 6
- 238000004891 communication Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
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- 230000004069 differentiation Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
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- 230000001360 synchronised effect Effects 0.000 description 1
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Abstract
The embodiment of the application discloses a starting method, a starting device, a storage medium and an electronic device of a co-processing chip, wherein the embodiment of the application receives a starting program transmitted by an application processing chip and stores the starting program into a memory; determining the storage address of the starting program in the memory, and limiting the writing authority of the starting program according to the storage address; the starting program is operated from the memory to complete the starting of the co-processing chip, the read permission of the first firmware code is still reserved, the operation of the first firmware code is not influenced, the write permission is limited, the starting safety of the co-processing chip is improved, the first firmware code cannot be tampered by an external application processing chip and an internal IP core, and the starting success rate of the co-processing chip is improved.
Description
Technical Field
The present application relates to the field of electronic devices, and in particular, to a method and an apparatus for starting a co-processing chip, a storage medium, and an electronic device.
Background
At present, in order to implement product differentiation, manufacturers of electronic devices such as mobile phones and tablet computers generally choose to add some co-processing chips, for example, multimedia processing chips, in addition to the application processing chip for image processing, and a starting process of the co-processing chip generally needs to load a plurality of firmware codes, for example, including boot code (bootloader), boot loader (bootloader), and firmware code of an operating system. Because the ROM (Read-Only Memory) of the co-processing chip has a limited storage space, Only bootcode can be stored, and other firmware codes are generally stored in the application processing chip, and when the co-processing chip is started, the application processing chip loads the firmware codes into the co-processing chip for operation. However, this manner of start-up is prone to start-up failure.
Disclosure of Invention
The embodiment of the application provides a starting method and device of a co-processing chip, a storage medium and an electronic device, which can improve the starting success rate of the co-processing chip.
In a first aspect, an embodiment of the present application provides a method for starting a co-processing chip, where the method is applied to the co-processing chip, and the method includes:
receiving a starting program transmitted by an application processing chip, and storing the starting program into a memory;
determining the storage address of the starting program in the memory, and limiting the writing authority of the starting program according to the storage address;
and running the starting program from the memory to finish the starting of the co-processing chip.
In a second aspect, an embodiment of the present application further provides a starting apparatus for a co-processing chip, where the apparatus is applied to the co-processing chip, and the apparatus includes:
the data receiving module is used for receiving a starting program transmitted by the application processing chip and storing the starting program to the memory;
the authority management module is used for determining the storage address of the starting program in the memory and limiting the writing authority of the starting program according to the storage address;
and the program running module is used for running the starting program from the memory so as to finish the starting of the co-processing chip.
In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program runs on a computer, the computer is caused to execute the method for starting the co-processing chip provided in any embodiment of the present application.
In a fourth aspect, an embodiment of the present application further provides an electronic apparatus, including a processor and a memory, where the memory has a computer program, and the processor is configured to execute the method for starting the co-processing chip according to any embodiment of the present application by calling the computer program.
According to the technical scheme, when the co-processing chip is started, the starting program is received from the application processing chip and stored in the memory, after transmission is completed, the storage address of the starting program in the memory is determined, the writing authority of the starting program is limited according to the storage address, then the starting program is operated from the memory to complete starting of the co-processing chip, due to the fact that the reading authority of the starting program is still reserved, operation of the starting program is not affected, the writing authority is limited, starting safety of the co-processing chip is improved, the starting program cannot be tampered by an external application processing chip and an internal IP core, and further starting success rate of the co-processing chip is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a first flowchart illustrating a method for starting a co-processing chip according to an embodiment of the present disclosure.
Fig. 2 is a schematic diagram of an architecture of an electronic device in a method for starting a co-processing chip according to an embodiment of the present disclosure.
Fig. 3 is a schematic structural diagram of a starting apparatus of a co-processing chip according to an embodiment of the present disclosure.
Fig. 4 is a first structural schematic diagram of an electronic device according to an embodiment of the present disclosure.
Fig. 5 is a second structural schematic diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without inventive step, are within the scope of the present application.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
A plurality of IP cores (also called Intellectual Property cores or Intellectual Property modules) are disposed in an existing co-processing chip as required, and these IP cores generally have Access rights to a DDR (Double Data Rate Synchronous Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). The application processing chip needs a certain transmission time to transmit the start program to the co-processing chip, and a certain time is also needed to run the start program, during this time, the IP core inside the co-processing chip may tamper with the start program through the bus, and in addition, the application processor may tamper with the start program in the co-processing chip through the SDIO (Secure Digital Input and Output) bus. Once the starting program is tampered, the co-processing chip is difficult to locate to which the starting program is tampered, so that the starting program is difficult to recover, the starting progress of the chip is seriously delayed, and even the starting failure is caused.
In order to solve the problem, an embodiment of the present application provides a starting method of a co-processing chip, where the starting method may be applied to an electronic device, and the electronic device may be a co-processing chip or an electronic device integrated with a co-processing chip.
The execution main body of the starting method of the co-processing chip may be the starting device of the co-processing chip provided in the embodiment of the present application, or an electronic device integrated with the starting device of the co-processing chip, where the starting device of the co-processing chip may be implemented in a hardware or software manner. Among other things, the electronic appliance may be a computing device such as a laptop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular telephone, a media player, or other handheld or portable electronic appliance, a smaller device (such as a wristwatch device, a hanging device, an earpiece or earpiece device, a device embedded in eyeglasses, or other device worn on the head of a user, or other wearable or miniature device), a television, a computer display not containing an embedded computer, a gaming device, a navigation device, an embedded system (such as a system in which the electronic appliance with a display is installed in a kiosk or automobile), a device that implements the functionality of two or more of these devices, or other electronic appliances.
Referring to fig. 1, fig. 1 is a first flowchart illustrating a starting method of a co-processing chip according to an embodiment of the present disclosure. The specific process of the starting method of the co-processing chip provided by the embodiment of the application can be as follows:
in 101, a start-up program transmitted by an application processing chip is received and stored in a memory.
In this embodiment, the application processing Chip is a main control SOC (System on Chip) of the electronic device, such as an application processor AP. A processor and a memory, such as a first processor and a first memory, may be integrated, where the first processor may perform data processing and the first memory may store data, including a first operating system and application programs. The application processing chip can run a first operating system and an application.
The co-processing chip may also integrate a processor and a memory, such as a second processor that may perform data processing and a second memory that may store data, including a second operating system and application programs. The co-processing chip may run a second operating system and applications. Illustratively, the co-processing chip may be a multimedia processing chip for performing enhancement processing on the shooting effect.
In addition, the co-processing chip may further include another IP core (also referred to as an Intellectual Property core or an Intellectual Property module) according to the functional requirements. In the field of chips, some functional modules that are commonly used in digital circuits but are relatively complex are designed as modules that can modify parameters, such as IP cores such as NPU (Neural-network Processing Unit), ISP (Image Signal Processor), DDR (double data rate), and DMA (Direct Memory Access). The IP cores are only examples, and in practical applications, one or more of the IP cores may be set as needed.
The application processing chip is connected with the interface of the co-processing chip, and the starting program which needs to be loaded in the starting process of the co-processing chip is transmitted to the memory of the co-processing chip through the interface. The interface of the co-processing chip may be an SDIO (Secure Digital Input and Output) interface, and the application processing chip is connected to the SDIO interface through an SDIO bus. The SDIO interface adopts a master-slave structure, the application processing chip is a HOST (HOST) end, the coprocessing chip is a DEVICE (DEVICE), the DEVICE end can only passively respond to the operation of the HOST end, and the communication between the DEVICE end and the HOST end is started by the HOST end sending a command. The device side analyzes the command of the host side to communicate with the host side.
The starting program of the co-processing chip is stored in the flash memory of the application processor. After the co-processing chip is started, a bootcode (a boot code) is firstly operated, wherein the bootcode is a code solidified in the chip production, and the boot code is used for guiding the start of the co-processing chip. After the bootcode finishes running, a Central Processing Unit (CPU) is initialized, then a start program sent by the application Processing chip is received through the SDIO interface, and the start program is stored in the memory. The memory in the embodiment of the present application may be DDR or SRAM.
In 102, a storage address of the boot program in the memory is determined, and the write permission of the boot program is restricted according to the storage address.
In 103, the boot program is executed from the memory to complete the boot of the co-processing chip.
After the boot program is stored in the co-processing chip, the storage address of the boot program in the memory is determined, and the write permission of the code segment in the storage address is limited, that is, after the transmission of the boot program is completed, no matter the external application processing chip or other internal IP cores can not modify the code, and only the read operation can be performed. Wherein, the storage address comprises the initial address of the storage space occupied by the starting program in the memory.
The boot loader or the first firmware code of the operating system may be the boot loader or the first firmware code, that is, the boot loader or the first firmware code may limit the write permission after the transfer is completed according to the scheme provided above.
Illustratively, the boot-loader includes a boot loader and a first firmware code of the operating system. Receiving a starting program transmitted by an application processing chip, storing the starting program into a memory, determining a storage address of the starting program in the memory, and limiting the write permission of the starting program according to the storage address, wherein the method comprises the following steps: receiving a boot loader transmitted by an application processing chip, and storing the boot loader into a memory; determining a first storage address of the boot loader in the memory, and limiting the write permission of the boot loader according to the first storage address; receiving a first firmware code of an operating system transmitted by an application processing chip, and storing the first firmware code to a memory; and determining a second storage address of the first firmware code in the memory, and limiting the writing authority of the first firmware code according to the second storage address.
Executing a boot program from memory, comprising: a boot loader is run from the memory and the first firmware code is run based on the boot loader.
In order to distinguish the firmware code of the operating system from the firmware code of the preset IP core, the firmware code of the operating system is referred to as a first firmware code, and the firmware code of the preset IP core is referred to as a second firmware code.
In an embedded operating system, a bootloader (boot loader) is a section of program that runs before the kernel of the operating system runs, and plays a role in booting the operating system to run. The bootloader can initialize hardware equipment and establish a memory space mapping diagram, so as to bring the software and hardware environment of the system to a proper state, load the operating system image or the solidified embedded application program into the memory after the bootloader completes the initialization of the related hardware, then jump to the space where the operating system is located, and start the operating system.
In this embodiment, in addition to the firmware code of the operating system, the access right of the boot loader may be protected, and after the transmission of the boot loader is completed, the write right of the boot loader is limited first, and then the write right of the first firmware code received from the operating system is limited.
Referring to fig. 2, fig. 2 is a schematic diagram of an architecture of an electronic device in a method for starting a co-processing chip according to an embodiment of the present disclosure. In terms of hardware implementation, a Memory Protection Unit (MPU) is added to an internal bus of the co-processing chip. The memory protection unit is used to limit write permission to the first firmware code.
The storage protection unit has a plurality of sets of registers, and can protect the access authority of data in a section of address space by configuring the value of the registers, for example, the access authority is set to be read-only, readable and writable, or not readable and writable, etc.
Exemplarily, the co-processing chip further comprises a memory protection unit, and the memory protection unit and the memory are both connected to the bus of the co-processing chip; the method comprises the steps of determining a second storage address of the first firmware code in a memory, and limiting the write permission of the first firmware code according to the second storage address, and comprises the following steps: determining a second storage address of the first firmware code in the memory; and determining a register corresponding to the second storage address in the storage protection unit, and setting the access right of the second storage address to be read only by configuring the value of the register.
In the embodiment of the application, a group of registers in the storage protection unit is used for protecting the first firmware code. After the first firmware code is transferred, the values of the set of registers are configured, for example, the values of the set of registers are modified to a preset value, and the preset value indicates that the access authority of the second storage address is read-only. After the configuration of the group of registers is completed, if a write request sent by an IP core in the application processing chip or the co-processing chip is received, determining an address field requested by the write request, if the address field of the write request is a storage area where the first firmware code is located, that is, a second storage address, reading a value of the register, determining that the requested address field, that is, the second storage address, is not writable according to the value of the register, and then, returning a prompt message of write-back operation failure to a sending end of the write request.
The register corresponding to the first storage address in the storage protection unit is determined, and in order to distinguish different sets of registers, the set of registers corresponding to the first storage address is denoted as R1, and the set of registers corresponding to the second storage address is denoted as R2.
After the register R1 corresponding to the first memory address is determined, the value of the register R1 is configured to indicate that the access rights for the first memory address are read-only. After the register R1 is configured, if a write request sent by an IP core inside an application processing chip or a co-processing chip is received, an address field requested by the write request is determined, if the requested address field is a first storage address, the value of the register R1 is read, the requested address field, that is, the first storage address is determined to be unwritable according to the value of the register R1, and then prompt information indicating that a write-back operation fails is returned to a sending end of the write request.
In addition, it should be noted that, in order to increase the starting speed, the first firmware code transmitted by the application processing chip is received and configured while the boot loader is running, and the first firmware code is run after the boot loader is run, so as to implement the starting of the co-processing chip.
In this embodiment, the co-processing chip may be provided with a DDR and an SRAM at the same time, where the SRAM is used to store some firmware codes with a smaller occupied space, and the DDR is used to store some firmware codes with a larger occupied space. For example, the boot loader may be stored in SRAM, and the first firmware code of the operating system, the second firmware code of the other IP core may be stored in DDR.
In some embodiments, after the startup of the co-processing chip is completed, the default configuration of the register is restored according to the second storage address, so as to remove the limitation on the write permission of the first firmware code.
Further, code for implementing the scheme of the present application may be provided in bootcode.
In specific implementation, the present application is not limited by the execution sequence of the described steps, and some steps may be performed in other sequences or simultaneously without conflict.
As can be seen from the above, in the starting method of the co-processing chip provided in this embodiment of the application, when the co-processing chip is started, the co-processing chip receives the starting program from the application processing chip, stores the starting program in the memory, determines the storage address of the starting program in the memory after transmission is completed, limits the write permission of the starting program according to the storage address, and then runs the starting program from the memory to complete the starting of the co-processing chip.
In some embodiments, the method may further comprise: after the transmission of a second firmware code of a preset IP core is finished, determining a third storage address of the second firmware code in the memory; and limiting the write permission of the second firmware code according to the storage protection unit and the third storage address.
In this embodiment, the firmware codes of some IP cores inside the co-processing chip may also be protected by the storage protection unit. The following describes the scheme of this embodiment by taking an NPU as an example, and in other embodiments, the preset IP core may also be another IP core, such as an ISP (Image Signal Processing, Image Signal processor), and the like.
The firmware codes in the NPU are generally trained neural network models, the application processing chip can load trained model data into a memory of the co-processing chip, the co-processing chip determines a third storage address of the model data after detecting that the model data is loaded, and the third storage address represents a storage space occupied by the second firmware codes in the memory. The write permission of the second firmware code is restricted in the same principle as above.
Or, in another embodiment, after the third storage address is acquired, the write permission of the application processing chip to the second firmware code is limited.
In this embodiment, for the model data, if there is no special protection, the possibility of being tampered by the application processing chip is relatively high, and other IP cores in the co-processing chip may also access the model data according to the needs of the processing task. And determining a register R3 corresponding to the third storage address, and setting the access authority of the application processing chip to the third storage address to be read only by configuring the value of the register R3. The principle of the method is different from that of the two registers in the above, when a write request for the third storage address is received, whether the write request comes from the application processing chip is determined, and if so, the value of the register corresponding to the third storage address is acquired to determine the access right. It will be appreciated that when the application processing chip needs to modify the model data or update the model data, such permission restrictions may be lifted by restoring the value of the register R3 to the initial value, after which the application processing chip may modify the data of the second firmware code.
In an embodiment, a starting device of the co-processing chip is further provided. Referring to fig. 3, fig. 3 is a schematic structural diagram of a starting device 300 of a co-processing chip according to an embodiment of the present disclosure. The starting device 300 of the co-processing chip is applied to an electronic device, and the starting device 300 of the co-processing chip includes a data receiving module 301, an authority management module 302 and a program running module 303, as follows:
the data receiving module 301 is configured to receive a start program transmitted by an application processing chip, and store the start program in a memory;
the authority management module 302 is configured to determine a storage address of the boot program in the memory, and perform restriction processing on the write authority of the boot program according to the storage address;
a program running module 303, configured to run the startup program from the memory to complete startup of the co-processing chip.
In some embodiments, the boot loader is a boot loader or a first firmware code of an operating system.
In some embodiments, the boot program includes a boot loader and a first firmware code of an operating system; the data receiving module 301 is further configured to: receiving a boot loader transmitted by an application processing chip, and storing the boot loader into the memory;
the rights management module 302 is further operable to: determining a first storage address of the bootstrap loader in the memory, and limiting the write permission of the bootstrap loader according to the first storage address;
the data receiving module 301 is further configured to: receiving a first firmware code of an operating system transmitted by an application processing chip, and storing the first firmware code to a memory;
the rights management module 302 is further operable to: determining a second storage address of the first firmware code in the memory, and performing restriction processing on the write permission of the first firmware code according to the second storage address;
the program execution module 303 is further configured to: the boot loader is executed from the memory, and the first firmware code is executed based on the boot loader.
In some embodiments, the co-processing chip further comprises a memory protection unit, the memory protection unit and the memory are both connected to a bus of the co-processing chip;
the rights management module 302 is further operable to: determining a second storage address of the first firmware code in the memory; and determining a register corresponding to the second storage address in the storage protection unit, and setting the access right of the second storage address to be read-only by configuring the value of the register.
In some embodiments, the rights management module 302 is further for: and after the start of the co-processing chip is finished, restoring the default configuration of the register according to the second storage address so as to remove the limitation of the write permission of the first firmware code.
In some embodiments, rights management module 302 is further configured to: when the transmission of a second firmware code of a preset IP core is finished, determining a third storage address of the second firmware code in the memory; and limiting the write permission of the second firmware code according to the storage protection unit and the third storage address.
It should be noted that the starting apparatus of the co-processing chip provided in the embodiment of the present application and the starting method of the co-processing chip in the foregoing embodiments belong to the same concept, and any method provided in the starting method embodiment of the co-processing chip can be implemented by the starting apparatus of the co-processing chip, and a specific implementation process thereof is described in detail in the starting method embodiment of the co-processing chip, and is not described herein again.
As can be seen from the above, in the starting apparatus of the co-processing chip provided in this embodiment of the application, when the co-processing chip is started, the co-processing chip receives the starting program from the application processing chip, stores the starting program in the memory, determines the storage address of the starting program in the memory after transmission is completed, limits the write permission of the starting program according to the storage address, and then runs the starting program from the memory to complete the start of the co-processing chip.
The embodiment of the application also provides an electronic device. The electronic device is a co-processing chip or an electronic device integrated with the co-processing chip, such as a smart phone, a tablet computer, a palm computer, and the like. Referring to fig. 4, fig. 4 is a first structural schematic diagram of an electronic device according to an embodiment of the present disclosure. In this embodiment, the electronic device may be a co-processing chip. The electronic device 400 comprises a processor 401 and a memory 402. The processor 401 is electrically connected to the memory 402.
The processor 401 is a control center of the electronic device 400, connects various parts of the whole electronic device using various interfaces and lines, performs various functions of the electronic device and processes data by running or calling a computer program stored in the memory 402 and calling data stored in the memory 402, thereby performing overall monitoring of the electronic device.
In this embodiment, the processor 401 in the electronic device 400 loads instructions corresponding to one or more processes of the computer program into the memory 402 according to the following steps, and the processor 401 runs the computer program stored in the memory 402, so as to implement various functions:
receiving a starting program transmitted by an application processing chip, and storing the starting program into a memory;
determining the storage address of the starting program in the memory, and limiting the writing authority of the starting program according to the storage address;
and running the starting program from the memory to finish the starting of the co-processing chip.
In some embodiments, please refer to fig. 5, and fig. 5 is a second structural diagram of an electronic device according to an embodiment of the present disclosure. In this embodiment, the electronic apparatus may be an electronic device integrated with a co-processing chip, and the electronic apparatus 400 further includes: radio frequency circuit 403, display 404, control circuit 405, input unit 406, audio circuit 407, sensor 408, and power supply 409. The processor 401 is electrically connected to the rf circuit 403, the display 404, the control circuit 405, the input unit 406, the audio circuit 407, the sensor 408, and the power source 409.
The radio frequency circuit 403 is used for transceiving radio frequency signals to communicate with a network device or other electronic apparatus through wireless communication.
The display screen 404 may be used to display information input by or provided to the user as well as various graphical user interfaces of the electronic device, which may be made up of images, text, icons, video, and any combination thereof.
The control circuit 405 is electrically connected to the display screen 404, and is configured to control the display screen 404 to display information.
The input unit 406 may be used to receive input numbers, character information, or user characteristic information (e.g., fingerprint), and to generate keyboard, mouse, joystick, optical, or trackball signal inputs related to user settings and function control. The input unit 406 may include a fingerprint recognition module.
The audio circuit 407 may provide an audio interface between the user and the electronic device through a speaker, microphone. Wherein the audio circuit 407 comprises a microphone. The microphone is electrically connected to the processor 401. The microphone is used for receiving voice information input by a user.
The sensor 408 is used to collect external environmental information. The sensors 408 may include one or more of ambient light sensors, acceleration sensors, gyroscopes, etc.
The power supply 409 is used to power the various components of the electronic device 400. In some embodiments, the power source 409 may be logically connected to the processor 401 through a power management system, so that functions of managing charging, discharging, and power consumption are implemented through the power management system.
Although not shown in the drawings, the electronic device 400 may further include a camera, a bluetooth module, and the like, which are not described in detail herein.
In this embodiment, the processor 401 in the electronic device 400 loads instructions corresponding to one or more processes of the computer program into the memory 402 according to the following steps, and the processor 401 runs the computer program stored in the memory 402, so as to implement various functions:
receiving a starting program transmitted by an application processing chip, and storing the starting program into a memory;
determining the storage address of the starting program in the memory, and limiting the writing authority of the starting program according to the storage address;
and running the starting program from the memory to finish the starting of the co-processing chip.
In some embodiments, processor 401 further performs:
receiving a boot loader transmitted by an application processing chip, and storing the boot loader into the memory;
determining a first storage address of the bootstrap loader in the memory, and limiting the write permission of the bootstrap loader according to the first storage address;
receiving a first firmware code of an operating system transmitted by an application processing chip, and storing the first firmware code to a memory;
determining a second storage address of the first firmware code in the memory, and performing restriction processing on the write permission of the first firmware code according to the second storage address;
the boot loader is executed from the memory, and the first firmware code is executed based on the boot loader.
In some embodiments, the co-processing chip further comprises a memory protection unit, the memory protection unit and the memory are both connected to a bus of the co-processing chip; the processor 401 further performs: determining a second storage address of the first firmware code in the memory; and determining a register corresponding to the second storage address in the storage protection unit, and setting the access right of the second storage address to be read-only by configuring the value of the register.
In some embodiments, processor 401 further performs: and after the start of the co-processing chip is finished, restoring the default configuration of the register according to the second storage address so as to remove the limitation of the write permission of the first firmware code.
In some embodiments, processor 401 further performs: after the transmission of a second firmware code of a preset IP core is finished, determining a third storage address of the second firmware code in the memory; and limiting the write permission of the second firmware code according to the storage protection unit and the third storage address.
As can be seen from the above, an embodiment of the present application provides an electronic device, where a co-processing chip of the electronic device receives a start-up program from an application processing chip when being started up, stores the start-up program in a memory, determines a storage address of the start-up program in the memory after transmission is completed, limits a write permission of the start-up program according to the storage address, and then runs the start-up program from the memory to complete start-up of the co-processing chip, where a read permission of the start-up program is still reserved, so that operation of the start-up program is not affected, and the write permission is limited, so that security of start-up of the co-processing chip is improved, and an external application processing chip and an internal IP core cannot tamper with the start-up program, thereby improving a success rate of start-up of the co-processing chip.
An embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program runs on a computer, the computer executes the method for starting the co-processing chip according to any of the above embodiments.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the apparatus and the module described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the embodiments of the present application, it should be understood that the disclosed system, apparatus, and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is merely a logical division, and in actual implementation, there may be other divisions, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed coupling or direct coupling or communication connection between each other may be through some interfaces, indirect coupling or communication connection between devices or modules, and may be in an electrical, mechanical or other form.
In addition, functional modules in the embodiments of the present application may be integrated into one processing module, or each module may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may be stored in a computer readable storage medium.
In the above embodiments, the implementation may be wholly or partly realized by software, hardware, firmware code, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product.
The computer program product includes one or more computer instructions. The procedures or functions described in accordance with the embodiments of the present application are generated in whole or in part when the computer program is loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can store or a data storage device, such as a server, a data center, etc., that is integrated with one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
The technical solutions provided by the embodiments of the present application are introduced in detail, and the principles and implementations of the embodiments of the present application are explained by applying specific examples in the embodiments of the present application, and the descriptions of the embodiments are only used to help understanding the method and core ideas of the embodiments of the present application; meanwhile, for a person skilled in the art, according to the idea of the embodiment of the present application, there may be a change in the specific implementation and application scope, and in summary, the content of the present specification should not be construed as a limitation to the embodiment of the present application.
Claims (10)
1. A starting method of a co-processing chip is applied to the co-processing chip and is characterized by comprising the following steps:
receiving a starting program transmitted by an application processing chip, and storing the starting program into a memory;
determining the storage address of the starting program in the memory, and limiting the writing authority of the starting program according to the storage address;
and running the starting program from the memory to finish the starting of the co-processing chip.
2. The method of claim 1, wherein the boot program is a boot loader or a first firmware code of an operating system.
3. A method of booting a co-processing chip as claimed in claim 1, wherein the boot program includes a boot loader and a first firmware code of an operating system;
the method comprises the following steps of receiving a starting program transmitted by an application processing chip, storing the starting program into a memory, determining a storage address of the starting program in the memory, and limiting the write permission of the starting program according to the storage address, and comprises the following steps:
receiving a boot loader transmitted by an application processing chip, and storing the boot loader into the memory;
determining a first storage address of the bootstrap loader in the memory, and limiting the write permission of the bootstrap loader according to the first storage address;
receiving a first firmware code of an operating system transmitted by an application processing chip, and storing the first firmware code to a memory;
determining a second storage address of the first firmware code in the memory, and performing restriction processing on the write permission of the first firmware code according to the second storage address;
the executing the boot program from the memory includes:
the boot loader is executed from the memory, and the first firmware code is executed based on the boot loader.
4. The method of booting a co-processing chip of claim 3 wherein the co-processing chip further includes a memory protection unit, the memory protection unit and the memory being connected to a bus of the co-processing chip; the determining a second storage address of the first firmware code in the memory, and performing restriction processing on the write permission of the first firmware code according to the second storage address includes:
determining a second storage address of the first firmware code in the memory;
and determining a register corresponding to the second storage address in the storage protection unit, and setting the access right of the second storage address to be read-only by configuring the value of the register.
5. The method for starting up a co-processing chip according to claim 4, further comprising:
and after the start of the co-processing chip is finished, restoring the default configuration of the register according to the second storage address so as to remove the limitation of the write permission of the first firmware code.
6. The method for starting up a co-processing chip according to claim 4, further comprising:
after the transmission of a second firmware code of a preset IP core is finished, determining a third storage address of the second firmware code in the memory;
and limiting the write permission of the second firmware code according to the storage protection unit and the third storage address.
7. A starting device of a co-processing chip is applied to the co-processing chip, and the device comprises:
the data receiving module is used for receiving a starting program transmitted by the application processing chip and storing the starting program to the memory;
the authority management module is used for determining the storage address of the starting program in the memory and limiting the writing authority of the starting program according to the storage address;
and the program running module is used for running the starting program from the memory so as to finish the starting of the co-processing chip.
8. The boot apparatus of a co-processing chip of claim 7, wherein the boot program comprises a boot loader and a first firmware code of an operating system;
the data receiving module is further configured to: receiving a boot loader transmitted by an application processing chip, and storing the boot loader into the memory;
the rights management module is further configured to: determining a first storage address of the bootstrap loader in the memory, and limiting the write permission of the bootstrap loader according to the first storage address;
the data receiving module is further configured to: receiving a first firmware code of an operating system transmitted by an application processing chip, and storing the first firmware code to a memory;
the rights management module is further configured to: determining a second storage address of the first firmware code in the memory, and performing restriction processing on the write permission of the first firmware code according to the second storage address;
the program running module is further configured to: the boot loader is executed from the memory, and the first firmware code is executed based on the boot loader.
9. A computer-readable storage medium, on which a computer program is stored, which, when run on a computer, causes the computer to perform the method of booting a co-processing chip according to any one of claims 1 to 6.
10. An electronic device comprising a processor and a memory, said memory storing a computer program, wherein said processor is adapted to execute the method of booting the co-processing chip according to any of claims 1 to 6 by invoking said computer program.
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|---|---|---|---|
| CN202011539206.3A CN114661364A (en) | 2020-12-23 | 2020-12-23 | Starting method and device of co-processing chip, storage medium and electronic device |
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| CN202011539206.3A CN114661364A (en) | 2020-12-23 | 2020-12-23 | Starting method and device of co-processing chip, storage medium and electronic device |
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