CN114650138A - I2C communication method, system, equipment and medium - Google Patents

I2C communication method, system, equipment and medium Download PDF

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Publication number
CN114650138A
CN114650138A CN202210072883.1A CN202210072883A CN114650138A CN 114650138 A CN114650138 A CN 114650138A CN 202210072883 A CN202210072883 A CN 202210072883A CN 114650138 A CN114650138 A CN 114650138A
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China
Prior art keywords
data
encryption key
transmitted
encryption
register
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Chinese (zh)
Inventor
林宁亚
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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Priority to CN202210072883.1A priority Critical patent/CN114650138A/en
Publication of CN114650138A publication Critical patent/CN114650138A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/14—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using a plurality of keys or algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
    • H04L9/0869—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving random numbers or seeds
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/088—Usage controlling of secret information, e.g. techniques for restricting cryptographic keys to pre-authorized uses, different access levels, validity of crypto-period, different key- or password length, or different strong and weak cryptographic algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

The invention discloses an I2C communication method, which comprises the following steps: a data sender reads a first encryption key in a register and inserts dummy data into data to be transmitted by using the first encryption key; the data sender sends the data to be transmitted with the false data to a data receiver together according to an I2C bus communication rule; and the data receiver reads the first encryption key in the register and extracts real data from the received data according to the first encryption key to obtain the data to be transmitted. The invention also discloses a system, a computer device and a readable storage medium. The scheme provided by the invention can carry out-of-order transmission on the data to be transmitted, namely filling the false data among the real data, and deleting the false data at the data receiving end to obtain the complete data to be transmitted, thereby preventing the data from being stolen.

Description

I2C communication method, system, equipment and medium
Technical Field
The invention relates to the field of I2C, in particular to an I2C communication method, system, equipment and storage medium.
Background
The I2C (Inter-Integrated Circuit) bus is a two-wire serial bus developed by PHILIPS for connecting microcontrollers and their peripherals. Is a bus standard widely adopted in the field of microelectronic communication control. The synchronous communication method is a special form of synchronous communication and has the advantages of few interface lines, simple control mode, small device packaging form, high communication speed and the like.
I2C transfers information between devices connected to a bus through a Serial Data (SDA) line and a Serial Clock (SCL) line. Each device has a unique address identification and can act as either a transmitter or receiver (depending on the function of the device). The host is a device that initiates data transfers of the bus and generates a clock signal that allows the transfers. At this point, any addressed device is considered a slave.
In general, the I2C link is simple, is a master-slave state, has a slow speed, and has many devices mounted on the same link, so there is a great risk of data communication, and common risks include invasion of slave devices on the link by technical means and connection of the I2C link by physical means. Therefore, even after the transmitted data is encrypted by the traditional encryption means, the data packet can be acquired from other slave devices on the link and then decrypted by the decryption means, so that the communication data can be stolen.
Therefore, because the data transmission mode and the data packet of I2C are easy to obtain, and it is not possible to guarantee the real safety and reliability of data, and because the logic of the I2C device is generally simpler and difficult to carry a complex encryption algorithm, a safe and reliable I2C communication method is needed.
Disclosure of Invention
In view of the above, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides an I2C communication method, including the following steps:
a data sending party reads a first encryption key in a register and inserts false data into data to be transmitted by using the first encryption key;
the data sender sends the data to be transmitted with false data to a data receiver together according to an I2C bus communication rule;
and the data receiver reads the first encryption key in the register and extracts real data from the received data according to the first encryption key to obtain the data to be transmitted.
In some embodiments, further comprising:
the data sender acquires a second encryption key and encrypts communication data by using the second encryption key to obtain the data to be transmitted;
and the data receiving party acquires the second encryption key and decrypts the real data by using the second encryption key to obtain the communication data.
In some embodiments, further comprising:
acquiring configuration parameters;
determining whether to encrypt and an encryption level according to the configuration parameters;
in response to determining encryption according to the configuration parameters, a corresponding portion is selected from the generated initial key according to the encryption level to be written into the register as a first encryption key.
In some embodiments, the data sender reads a first encryption key in a register and inserts dummy data in data to be transmitted by using the first encryption key, further comprising:
inserting random dummy data on the left side of corresponding bit data of the data to be transmitted in response to the value of the first encryption key being a first preset value;
and inserting random dummy data on the right side of corresponding bit data of the data to be transmitted in response to the value of the first encryption key being a second preset value.
In some embodiments, the data sender sends the data to be transmitted with dummy data to the data receiver according to the I2C bus communication rule, further comprising:
adjusting a response time threshold of the data receiver;
acquiring a generated random number;
and stretching the clock of the corresponding bit according to the random number to prolong the clock length corresponding to the bit of data, wherein the prolonged time length is less than the time threshold.
In some embodiments, the data sender sends the data to be transmitted with dummy data to the data receiver according to the I2C bus communication rule, further comprising:
acquiring a generated random number;
and transmitting a start signal and an end signal before transmitting the data of the corresponding bit of the random number, and transmitting the data of the corresponding bit of the random number after transmitting the end signal.
In some embodiments, further comprising:
responding to the data receiving party to receive the ending signal, and judging whether the digit of the currently received data is a preset digit or not;
and in response to the bit number of the currently received data not being the preset bit number, ignoring the end signal to continue receiving the next bit of data.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides an I2C communication system, including:
the encryption module is configured to enable a data sender to read a first encryption key in a register and insert false data into data to be transmitted by using the first encryption key;
the sending module is configured to enable the data sending party to send the data to be transmitted together with false data to the data receiving party according to an I2C bus communication rule;
and the decryption module is configured to enable the data receiving party to read the first encryption key in the register and extract real data from the received data according to the first encryption key to obtain the data to be transmitted.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer apparatus, including:
at least one processor; and
a memory storing a computer program operable on the processor, wherein the processor executes the program to perform the steps of:
a data sender reads a first encryption key in a register and inserts dummy data into data to be transmitted by using the first encryption key;
the data sender sends the data to be transmitted with the false data to a data receiver together according to an I2C bus communication rule;
and the data receiver reads the first encryption key in the register and extracts real data from the received data according to the first encryption key to obtain the data to be transmitted.
In some embodiments, further comprising:
the data sender acquires a second encryption key and encrypts communication data by using the second encryption key to obtain the data to be transmitted;
and the data receiving party acquires the second encryption key and decrypts the real data by using the second encryption key to obtain the communication data.
In some embodiments, further comprising:
acquiring configuration parameters;
determining whether to encrypt and an encryption level according to the configuration parameters;
in response to determining encryption according to the configuration parameters, a corresponding portion is selected from the generated initial key according to the encryption level to be written into the register as a first encryption key.
In some embodiments, the data sender reads a first encryption key in a register and inserts dummy data in data to be transmitted by using the first encryption key, further comprising:
inserting random dummy data on the left side of corresponding bit data of the data to be transmitted in response to the value of the first encryption key being a first preset value;
and in response to the value of the first encryption key being a second preset value, inserting random dummy data on the right side of corresponding bit data of the data to be transmitted.
In some embodiments, the data sender sends the data to be transmitted with dummy data to the data receiver according to the I2C bus communication rule, further comprising:
adjusting a response time threshold of the data receiver;
acquiring a generated random number;
and stretching the clock of the corresponding bit according to the random number to prolong the clock length corresponding to the bit of data, wherein the prolonged time length is less than the time threshold.
In some embodiments, the data sender sends the data to be transmitted with dummy data to the data receiver according to the I2C bus communication rule, further comprising:
acquiring a generated random number;
and transmitting start and end signals before transmitting the data of the corresponding bit of the random number, and transmitting the data of the corresponding bit of the random number after transmitting the end signal.
In some embodiments, further comprising:
responding to the data receiving party to receive the ending signal, and judging whether the digit of the currently received data is a preset digit or not;
and in response to the bit number of the currently received data not being the preset bit number, ignoring the end signal to continue receiving the next bit data.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium storing a computer program which, when executed by a processor, performs the steps of:
a data sender reads a first encryption key in a register and inserts dummy data into data to be transmitted by using the first encryption key;
the data sender sends the data to be transmitted with the false data to a data receiver together according to an I2C bus communication rule;
and the data receiver reads the first encryption key in the register and extracts real data from the received data according to the first encryption key to obtain the data to be transmitted.
In some embodiments, further comprising:
the data sender acquires a second encryption key and encrypts communication data by using the second encryption key to obtain the data to be transmitted;
and the data receiving party acquires the second encryption key and decrypts the real data by using the second encryption key to obtain the communication data.
In some embodiments, further comprising:
acquiring configuration parameters;
determining whether to encrypt and an encryption level according to the configuration parameters;
in response to determining encryption according to the configuration parameters, a corresponding portion is selected from the generated initial key according to the encryption level to be written into the register as a first encryption key.
In some embodiments, the data sending side reads the first encryption key in the register and inserts false data in the data to be transmitted by using the first encryption key, further comprising:
inserting random dummy data on the left side of corresponding bit data of the data to be transmitted in response to the value of the first encryption key being a first preset value;
and inserting random dummy data on the right side of corresponding bit data of the data to be transmitted in response to the value of the first encryption key being a second preset value.
In some embodiments, the data sender sends the data to be transmitted with dummy data to the data receiver according to the I2C bus communication rule, further comprising:
adjusting a response time threshold of the data receiver;
acquiring the generated random number;
and stretching the clock of the corresponding bit according to the random number to prolong the clock length corresponding to the bit of data, wherein the prolonged time length is less than the time threshold.
In some embodiments, the data sender sends the data to be transmitted with dummy data to the data receiver according to the I2C bus communication rule, further comprising:
acquiring a generated random number;
and transmitting a start signal and an end signal before transmitting the data of the corresponding bit of the random number, and transmitting the data of the corresponding bit of the random number after transmitting the end signal.
In some embodiments, further comprising:
responding to the data receiving party to receive the ending signal, and judging whether the digit of the currently received data is a preset digit or not;
and in response to the bit number of the currently received data not being the preset bit number, ignoring the end signal to continue receiving the next bit data.
The invention has one of the following beneficial technical effects: the scheme provided by the invention can carry out-of-order transmission on the data to be transmitted, namely filling the false data among the real data, and deleting the false data at the data receiving end to obtain the complete data to be transmitted, thereby preventing the data from being stolen.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic flowchart of an I2C communication method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an I2C link structure provided by an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating stretching of a clock corresponding to one bit of data;
FIG. 4 is a schematic diagram of the generation of a transient Start/Stop signal prior to one of the bits of data;
fig. 5 is a schematic structural diagram of a communication system I2C according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a computer device provided in an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In an embodiment of the invention, the Master is the Master, i.e., the party initiating the communication in the I2C communication. The Slave is the party that receives communications from the device, i.e., the I2C bus.
According to an aspect of the present invention, an embodiment of the present invention proposes an I2C communication method, as shown in fig. 1, which may include the steps of:
s1, the data sender reads the first encryption key in the register and inserts false data in the data to be transmitted by using the first encryption key;
s2, the data sender sends the data to be transmitted with false data to the data receiver according to the I2C bus communication rule;
s3, the data receiving side reads the first encryption key in the register and extracts real data from the received data according to the first encryption key to obtain the data to be transmitted.
The scheme provided by the invention can carry out-of-order transmission on the data to be transmitted, namely, filling the false data among the real data, and deleting the false data at the data receiving end to obtain the complete data to be transmitted, so that the data receiving end without the secret key can not obtain a complete data packet, and the data is prevented from being stolen.
In some embodiments, when data reading is performed, the reading flow due to I2C is:
master sends I2C addr (7bit) and w operation 1(1bit), waits for ACK;
the Slave sends ACK;
master sends regaddr (8bit), waits for ACK;
the Slave sends ACK;
master initiates START;
master sends I2Caddr (7bit) and r operation 1(1bit), waits for ACK;
the Slave sends ACK;
the Slave sends data (8bit), namely the value in the register;
9, Master sends ACK;
10. steps 8 and 9 may be repeated a plurality of times, i.e. reading a plurality of registers sequentially.
Thus, the master device may act as a data receiver and the slave device as a data sender.
When data writing is performed, the writing flow of I2C is:
master initiated START
Master sends I2Caddr (7bit) and w operation 0(1bit), waits for ACK
Slave sending ACK
Master sends regaddr (8bit), waits for ACK
Slave sending ACK
Master sends data (8bit), i.e. data to be written into register, waiting for ACK
Slave sending ACK
8. Steps 6 and 7 may be repeated multiple times, i.e., writing multiple registers sequentially
Master initiated STOP 9
Thus, the master device may act as a data sender and the slave device as a data receiver.
In some embodiments, further comprising:
the data sender acquires a second encryption key and encrypts communication data by using the second encryption key to obtain the data to be transmitted;
and the data receiving party acquires the second encryption key and decrypts the real data by using the second encryption key to obtain the communication data.
Specifically, the communication data can be encrypted by using the first key before transmission, and then dummy data is filled in the encrypted data by using the second key, so that even if the data to be transmitted is stolen, a real data packet cannot be obtained because the dummy data is filled in the data to be transmitted.
In some embodiments, further comprising:
acquiring configuration parameters;
determining whether to encrypt and an encryption level according to the configuration parameters;
in response to determining encryption according to the configuration parameters, a corresponding portion is selected from the generated initial key according to the encryption level to be written into the register as a first encryption key.
Specifically, as shown in fig. 2, the master device and the slave device may be connected to an encryption unit through a link other than I2C, where the encryption unit includes a key processing unit, a key generator, and a configuration unit. The key generator may be a secure trusted device such as TCM or TPM of the server. The configuration unit contains some basic functions such as encryption function on or off, encryption level. The key processing unit is responsible for processing data into data conforming to the I2C communication. After initialization, the key generator generates a set of random numbers, assuming 16 bits, and assuming 0100000011011011, the key processing unit reads the configuration parameters of the configuration unit to determine whether the encryption function is enabled and the encryption level. Assuming that the configuration item is the encryption function on, the encryption level is either one, i.e. one of two numbers is selected. The key processing unit intercepts the data of the key generator from the first half segment, i.e. 01100000. After processing is complete, the data is stored in registers and can be read by the I2C master and slave devices.
In some embodiments, the data sender reads a first encryption key in a register and inserts dummy data in data to be transmitted by using the first encryption key, further comprising:
inserting random dummy data on the left side of corresponding bit data of the data to be transmitted in response to the value of the first encryption key being a first preset value;
and inserting random dummy data on the right side of corresponding bit data of the data to be transmitted in response to the value of the first encryption key being a second preset value.
Specifically, the master device encrypts and transmits the data according to the data transmitted by the encryption unit.
For example, 11110101 is the data to be transmitted, where the value 0 or 1 of each bit of the key corresponds to two bits of real data before or after the key, and the first bit of the key is 0, the 1 st bit of the transmitted data is real data. The second bit of the key is 1, and the 4 th bit of the transmitted data is real data. By analogy, the data stream transmitted by I2C is 1X X1X 11X 0X 1X, and X is randomly filled with dummy data.
When a write request from the master device is received from the slave device at address 0101011, the received data is decrypted according to the key, the received data is 1011011000110110, and the data is processed by using the key to obtain data 011110101.
In some embodiments, the data sender sends the data to be transmitted with dummy data to the data receiver according to the I2C bus communication rule, further comprising:
adjusting a response time threshold of the data receiver;
acquiring a generated random number;
and stretching the clock of the corresponding bit according to the random number to prolong the clock length corresponding to the bit of data, wherein the prolonged time length is less than the time threshold.
Specifically, the clock may be scrambled to increase the clock length of the response signal, and since I2C transmits 8 bits of data each time when transmitting data, a random number is set each time, and the clock corresponding to one bit of data is randomly stretched, for example, as shown in fig. 3, the clock of the 12 th bit of data (corresponding to the 3 rd bit of data) is stretched, so that other slave devices cannot receive data because the response time threshold is not extended by other slave devices.
In some embodiments, the data sending side sends the data to be transmitted with dummy data to the data receiving side according to the I2C bus communication rule, further comprising:
acquiring a generated random number;
and transmitting start and end signals before transmitting the data of the corresponding bit of the random number, and transmitting the data of the corresponding bit of the random number after transmitting the end signal.
In some embodiments, further comprising:
responding to the data receiving party to receive the ending signal, and judging whether the digit of the currently received data is a preset digit or not;
and in response to the bit number of the currently received data not being the preset bit number, ignoring the end signal to continue receiving the next bit data.
Specifically, a Start/Stop signal is generated for the data line, a slave device with encryption and decryption functions automatically filters the short Start/Stop signal in the communication process, and a normal slave device is disturbed. Each time a random number can be generated, the Start and end signals are transmitted before the data of the corresponding bit of said random number is transmitted, so that other slave devices cannot ignore the short Start/Stop signal and are disturbed, and the slave devices in communication can automatically filter the Start/Stop signal because the received data does not reach the preset number of bits. For example, as shown in fig. 4, the Start/Stop signal is generated before the 12 th bit data (corresponding to the 3 rd bit data at one time), so that other slave devices are disturbed.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides an I2C communication system 400, as shown in fig. 5, including:
the encryption module 401 is configured to enable a data sending party to read a first encryption key in a register and insert dummy data into data to be transmitted by using the first encryption key;
a sending module 402, configured to enable the data sender to send the data to be transmitted together with dummy data to a data receiver according to an I2C bus communication rule;
the decryption module 403 is configured to enable the data receiving side to read the first encryption key in the register and extract real data from the received data according to the first encryption key to obtain the data to be transmitted.
In some embodiments, a second cryptographic model is also included, configured such that:
the data sender acquires a second encryption key and encrypts communication data by using the second encryption key to obtain the data to be transmitted;
and the data receiving party acquires the second encryption key and decrypts the real data by using the second encryption key to obtain the communication data.
In some embodiments, the system further comprises an initialization module configured to:
acquiring configuration parameters;
determining whether to encrypt and an encryption level according to the configuration parameters;
in response to determining encryption according to the configuration parameters, a corresponding portion is selected from the generated initial key according to the encryption level to be written into the register as a first encryption key.
In some embodiments, the encryption module 401 is further configured to:
inserting random dummy data on the left side of corresponding bit data of the data to be transmitted in response to the value of the first encryption key being a first preset value;
and inserting random dummy data on the right side of corresponding bit data of the data to be transmitted in response to the value of the first encryption key being a second preset value.
In some embodiments, the sending module 402 is further configured to:
adjusting a response time threshold of the data receiver;
acquiring a generated random number;
and stretching the clock of the corresponding bit according to the random number to prolong the clock length corresponding to the bit of data, wherein the prolonged time length is less than the time threshold.
In some embodiments, the sending module 402 is further configured to:
acquiring a generated random number;
and transmitting a start signal and an end signal before transmitting the data of the corresponding bit of the random number, and transmitting the data of the corresponding bit of the random number after transmitting the end signal.
In some embodiments, the sending module 402 is further configured to:
responding to the data receiving party to receive the ending signal, and judging whether the digit of the currently received data is a preset digit or not;
and in response to the bit number of the currently received data not being the preset bit number, ignoring the end signal to continue receiving the next bit data.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 6, an embodiment of the present invention further provides a computer apparatus 501, including:
at least one processor 520; and
a memory 510, the memory 510 storing a computer program 511 executable on the processor, the processor 520 executing the program to perform the steps of:
s1, the data sender reads the first encryption key in the register and inserts false data in the data to be transmitted by using the first encryption key;
s2, the data sender sends the data to be transmitted with false data to the data receiver according to the I2C bus communication rule;
s3, the data receiving side reads the first encryption key in the register and extracts real data from the received data according to the first encryption key to obtain the data to be transmitted.
In some embodiments, further comprising:
the data sender acquires a second encryption key and encrypts communication data by using the second encryption key to obtain the data to be transmitted;
and the data receiving party acquires the second encryption key and decrypts the real data by using the second encryption key to obtain the communication data.
In some embodiments, further comprising:
acquiring configuration parameters;
determining whether to encrypt and an encryption level according to the configuration parameters;
in response to determining encryption according to the configuration parameters, a corresponding portion is selected from the generated initial key according to the encryption level to be written into the register as a first encryption key.
In some embodiments, the data sender reads a first encryption key in a register and inserts dummy data in data to be transmitted by using the first encryption key, further comprising:
inserting random dummy data on the left side of corresponding bit data of the data to be transmitted in response to the value of the first encryption key being a first preset value;
and inserting random dummy data on the right side of corresponding bit data of the data to be transmitted in response to the value of the first encryption key being a second preset value.
In some embodiments, the data sender sends the data to be transmitted with dummy data to the data receiver according to the I2C bus communication rule, further comprising:
adjusting a response time threshold of the data receiver;
acquiring the generated random number;
and stretching the clock of the corresponding bit according to the random number to prolong the clock length corresponding to the bit of data, wherein the prolonged time length is less than the time threshold.
In some embodiments, the data sender sends the data to be transmitted with dummy data to the data receiver according to the I2C bus communication rule, further comprising:
acquiring a generated random number;
and transmitting a start signal and an end signal before transmitting the data of the corresponding bit of the random number, and transmitting the data of the corresponding bit of the random number after transmitting the end signal.
In some embodiments, further comprising:
responding to the data receiving party to receive the ending signal, and judging whether the digit of the currently received data is a preset digit or not;
and in response to the bit number of the currently received data not being the preset bit number, ignoring the end signal to continue receiving the next bit data.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 7, an embodiment of the present invention further provides a computer-readable storage medium 601, where the computer-readable storage medium 601 stores computer program instructions 610, and the computer program instructions 610, when executed by a processor, perform the following steps:
s1, the data sender reads the first encryption key in the register and inserts false data in the data to be transmitted by using the first encryption key;
s2, the data sender sends the data to be transmitted with false data to the data receiver according to the I2C bus communication rule;
s3, the data receiving side reads the first encryption key in the register and extracts real data from the received data according to the first encryption key to obtain the data to be transmitted.
In some embodiments, further comprising:
the data sender acquires a second encryption key and encrypts communication data by using the second encryption key to obtain the data to be transmitted;
and the data receiving party acquires the second encryption key and decrypts the real data by using the second encryption key to obtain the communication data.
In some embodiments, further comprising:
acquiring configuration parameters;
determining whether to encrypt and an encryption level according to the configuration parameters;
in response to determining encryption according to the configuration parameters, a corresponding portion is selected from the generated initial key according to the encryption level to be written into the register as a first encryption key.
In some embodiments, the data sending side reads the first encryption key in the register and inserts false data in the data to be transmitted by using the first encryption key, further comprising:
inserting random dummy data on the left side of corresponding bit data of the data to be transmitted in response to the value of the first encryption key being a first preset value;
and inserting random dummy data on the right side of corresponding bit data of the data to be transmitted in response to the value of the first encryption key being a second preset value.
In some embodiments, the data sender sends the data to be transmitted with dummy data to the data receiver according to the I2C bus communication rule, further comprising:
adjusting a response time threshold of the data receiver;
acquiring a generated random number;
and stretching the clock of the corresponding bit according to the random number to prolong the clock length corresponding to the bit of data, wherein the prolonged time length is less than the time threshold.
In some embodiments, the data sender sends the data to be transmitted with dummy data to the data receiver according to the I2C bus communication rule, further comprising:
acquiring the generated random number;
and transmitting a start signal and an end signal before transmitting the data of the corresponding bit of the random number, and transmitting the data of the corresponding bit of the random number after transmitting the end signal.
In some embodiments, further comprising:
responding to the data receiving party to receive the ending signal, and judging whether the digit of the currently received data is a preset digit or not;
and in response to the bit number of the currently received data not being the preset bit number, ignoring the end signal to continue receiving the next bit data.
Finally, it should be noted that, as understood by those skilled in the art, all or part of the processes in the methods of the embodiments described above may be implemented by instructing relevant hardware by a computer program, and the program may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims (10)

1. An I2C communication method, comprising the steps of:
a data sender reads a first encryption key in a register and inserts dummy data into data to be transmitted by using the first encryption key;
the data sender sends the data to be transmitted with false data to a data receiver together according to an I2C bus communication rule;
and the data receiver reads the first encryption key in the register and extracts real data from the received data according to the first encryption key to obtain the data to be transmitted.
2. The method of claim 1, further comprising:
the data sender acquires a second encryption key and encrypts communication data by using the second encryption key to obtain the data to be transmitted;
and the data receiving party acquires the second encryption key and decrypts the real data by using the second encryption key to obtain the communication data.
3. The method of claim 1, further comprising:
acquiring configuration parameters;
determining whether to encrypt and an encryption level according to the configuration parameters;
in response to determining encryption according to the configuration parameters, a corresponding portion is selected from the generated initial key according to the encryption level to be written into the register as a first encryption key.
4. The method of claim 1, wherein a data sender reads a first encryption key in a register and inserts dummy data in data to be transmitted using the first encryption key, further comprising:
inserting random dummy data on the left side of corresponding bit data of the data to be transmitted in response to the value of the first encryption key being a first preset value;
and inserting random dummy data on the right side of corresponding bit data of the data to be transmitted in response to the value of the first encryption key being a second preset value.
5. The method of claim 1, wherein the data sender sends the data to be transmitted with the dummy data to a data receiver according to an I2C bus communication rule, further comprising:
adjusting a response time threshold of the data receiver;
acquiring a generated random number;
and stretching the clock of the corresponding bit according to the random number to prolong the clock length corresponding to the bit of data, wherein the prolonged time length is less than the time threshold.
6. The method of claim 1, wherein the data sender sends the data to be transmitted with the dummy data to a data receiver according to an I2C bus communication rule, further comprising:
acquiring the generated random number;
and transmitting a start signal and an end signal before transmitting the data of the corresponding bit of the random number, and transmitting the data of the corresponding bit of the random number after transmitting the end signal.
7. The method of claim 6, further comprising:
responding to the data receiving party to receive the ending signal, and judging whether the digit of the currently received data is a preset digit or not;
and in response to the bit number of the currently received data not being the preset bit number, ignoring the end signal to continue receiving the next bit data.
8. An I2C communication system, comprising:
the encryption module is configured to enable a data sender to read a first encryption key in a register and insert false data into data to be transmitted by using the first encryption key;
the sending module is configured to enable the data sending party to send the data to be transmitted together with the false data to the data receiving party according to an I2C bus communication rule;
and the decryption module is configured to enable the data receiving party to read the first encryption key in the register and extract real data from the received data according to the first encryption key to obtain the data to be transmitted.
9. A computer device, comprising:
at least one processor; and
memory storing a computer program operable on the processor, wherein the processor executes the program to perform the steps of the method according to any of claims 1-7.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the method according to any one of claims 1 to 7.
CN202210072883.1A 2022-01-21 2022-01-21 I2C communication method, system, equipment and medium Pending CN114650138A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116501680A (en) * 2023-06-21 2023-07-28 苏州浪潮智能科技有限公司 I2C bus communication method, slave device, master device and I2C network system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116501680A (en) * 2023-06-21 2023-07-28 苏州浪潮智能科技有限公司 I2C bus communication method, slave device, master device and I2C network system
CN116501680B (en) * 2023-06-21 2023-09-12 苏州浪潮智能科技有限公司 I2C bus communication method, slave device, master device and I2C network system

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