CN114650079A - Inverse modulation method for contactless communication, and corresponding transponder - Google Patents

Abstract

Embodiments of the present disclosure relate to a method of inverse modulation for contactless communication, and a corresponding transponder. A contactless communication method includes inversely modulating a carrier signal received at a terminal of an antenna in alternation of a modulated state and an unmodulated state. The modulation state includes modulating a load at the antenna terminal with zero impedance and controlling a transition from the modulated state to the unmodulated state at a time determined by the first delay.

Description

Inverse modulation method for contactless communication, and corresponding transponder

Cross Reference to Related Applications

The present application claims the benefit of french application No. 2013523 filed on 12/17/2020, which is incorporated herein by reference.

Technical Field

Implementations and embodiments relate to contactless communications, and more particularly to contactless communications using amplitude back modulation of a carrier signal.

Background

Contactless communication, for example communication according to a technology called "near field communication" (generally "NFC"), and communication according to a technology called "radio frequency identification" (generally "RFID"), is a wireless connection technology that allows short-range (for example 10cm) communication between electronic devices, for example between a contactless integrated circuit card or tag and a reader.

The NFC technology is an open technology platform, and is standardized in ISO-14443, EMVCo, and NFC forum standards, but incorporates other existing compatible communication standards. RFID technology is standardized in particular by the ISO-18092 standard and also incorporates other existing compatible communication standards.

Contactless communication can be implemented between two contactless peer-to-peer communication devices, in particular devices compatible with NFC technology, such as a multifunctional phone (commonly referred to as "smartphone"); or between a reader device and a transponder device, such as an NFC or RFID card or tag or a multifunctional phone emulated in card mode.

When transmitting information between the reader and the transponder, the reader generates a magnetic field with an antenna, which is typically a 13.56MHz sine wave (referred to as a carrier wave or carrier signal).

In order to transmit information from the reader to the transponder, the reader uses amplitude modulation of the carrier wave, and the transponder is able to demodulate the received carrier wave to obtain the data transmitted by the reader.

In order to transmit information from the transponder to the reader, the reader generates a magnetic field (carrier wave) without modulation. The transponder then modulates the field generated by the reader according to the information to be transmitted. The frequency of this modulation corresponds to the sub-carriers of the carrier. The frequency of this subcarrier depends on the communication protocol used and may for example be equal to 848 kHz.

The modulation is performed by modifying the load connected to the antenna terminals of the transponder.

Two modes of operation, passive or active, are then possible.

In the active mode of operation, both the reader and the active transponder generate an electromagnetic field. This mode of operation is typically used when the active transceiver has its own power source (e.g., a battery).

In particular, a passive transponder has no power source and uses the energy transmitted by the carrier from the reader to power its integrated circuit.

In the passive mode, the transponder back modulates the wave from the reader to transmit information, and does not integrate the actual transmitter used to transmit the information, e.g., a transmitter capable of generating its own magnetic field during transmission.

A passive transponder modifies the impedance connected to its antenna by means of an inductive coupling by means of a back modulation visible on the reader side to transmit data frames.

During frame transmission, reverse modulation is limited to an unmodulated state when a reverse modulation load is not connected to the antenna, or to a modulated state when the reverse modulation load is connected to the transponder antenna.

The greater the change in impedance generated by the transponder (i.e., the difference in load between the modulated and unmodulated states), the greater the impedance seen from the reader side, and therefore the easier it is for the reader to demodulate the data. One of the main performance criteria of a transponder is the load modulation amplitude "LMA". The way of measuring the LMA is to measure the difference in the current amplitude in the antenna Lc of the transponder CRD between the modulated state and the unmodulated state.

One difficulty encountered in the design of contactless transponders is to optimize the LMA while maintaining a coherent frame, that is to say synchronization with the carrier signal of the reader, regardless of the condition of the electromagnetic field (in particular the distance between the reader and the transponder).

In conventional contactless transponders, the load modulation is designed such that the carrier signal on the transponder antenna is available in both the modulated and unmodulated state. This allows keeping the clock extraction from the carrier active and clocking the transmission on the clock cycle of the extracted signal as the only time reference, in particular defining the moment of transition between the unmodulated state and the modulated state.

A disadvantage of these conventional solutions is that the impedance at the antenna terminals is in principle prohibited from being zero or too low due to the need to extract the clock signal. Thus, the conventional solution provides to adjust the impedance value in the modulation state according to the effective level of the electromagnetic field, which complicates the design of the inverse modulation and limits the load modulation amplitude LMA.

There is a need to increase the load modulation amplitude LMA of contactless transponders, in particular passive contactless transponders.

Disclosure of Invention

According to one aspect, there is provided a contactless communication method, the method comprising: the carrier signal received at the antenna terminals is inversely modulated with alternating modulated and unmodulated states. According to a general feature of the aspect, the unmodulated state comprises modulation at a non-zero impedance of the load at the antenna terminals, the modulated state comprises modulation at a zero impedance or a near-zero impedance of the load at the antenna terminals, and the transition from the modulated state to the unmodulated state is controlled at a time determined by the first delay.

"zero or almost zero impedance" refers to an impedance that is as low as possible in view of the material constraints to achieve it, e.g., a transistor that is considered to be in an on-state has zero or almost zero impedance at its conduction terminals. For example, in particular, "near-zero impedance" refers to an impedance that is at most a few percent (e.g., 2%) of the non-zero impedance value in the unmodulated state.

In other words, delays are used in the modulation state to maintain precise synchronization of the frame transmission to provide full zero impedance back modulation. The first delay is therefore used to define the time of the modulation state, since the clock signal cannot be extracted from the modulated carrier signal with zero impedance.

Thus, the load modulation amplitude LMA is maximized (strictly speaking, the modulation state component of the LMA is optimized), which allows in particular to increase the range of the contactless communication.

According to one implementation, the transition from the unmodulated state to the modulated state is controlled at a time determined by a duration measured on a clock cycle generated by a clock signal extracted from the carrier signal, the duration measurement starting at a time determined by a second delay, the time determined by the second delay following the time of the transition to the unmodulated state.

In other words, the second delay allows avoiding the use of the clock signal extracted when restarting the clock extraction at the beginning of the modulation state, allowing avoiding instability in the clock signal extracted when it generates a restart.

In particular, this allows the timing of the transitions to be very precisely defined over time and can be adapted to different conditions.

According to one embodiment, the measurement of the second delay and the measurement of the first delay start at a time coordinated with a modulation control signal initiating a control transition to a modulation state, the second delay being greater than the first delay.

For example, the modulation control signal is located at the origin of the modulation state control and may typically be generated by a digital controller. The start of the measurement of the first delay and the second delay is controlled based on the modulation control signal and is for example offset by half a clock period from each other to ensure robust operation of the system.

The difference between the second delay and the first delay is advantageously designed to be just long enough to ensure that the clock signal extraction has restarted and is stable at the beginning of the measurement of the clock cycle.

According to one embodiment, a mask signal is generated that blocks the extracted clock signal at a constant reference level during the second delay duration.

According to an embodiment, the second delay is obtained by loading the second capacitive element with a second reference current for a time.

According to one embodiment, the load modulation at the antenna terminals with the modulation state impedance being zero or almost zero is controlled by a reverse modulation signal generated for a duration determined by the first delay.

According to one embodiment, the first delay is obtained by loading the first capacitive element with a first reference current for a time.

According to another aspect, there is provided a contactless communication transponder, such as a tag, comprising: an antenna intended to receive a carrier signal, and a modulator configured to inversely modulate the carrier signal in alternation of a modulated state and an unmodulated state. According to a general feature of the aspect, the modulator comprises a first delay circuit configured to generate a first delay, and the modulator is configured to modulate the load at the antenna terminal to a non-zero impedance in an unmodulated state, to modulate the load at the antenna terminal to a zero or near zero impedance in a modulated state, and to control the transition from the modulated state to the unmodulated state at a time determined by the first delay.

According to one embodiment, the transponder further comprises a clock extraction circuit configured to generate a clock signal extracted from the carrier signal, and the modulator comprises a second delay circuit configured to generate a second delay, and a control circuit configured to measure a duration on the clock cycle from the extracted clock signal from a time determined by the second delay, the time determined by the second delay being subsequent to a time of transition to the unmodulated state, and to generate the modulation control signal controlling the transition from the unmodulated state to the modulated state at the time determined by the measured duration.

According to one embodiment, the first delay circuit and the second delay circuit are configured to begin measurement of a first delay and measurement of a second delay at a time coordinated with a modulation control signal generated by the digital controller, the modulation control signal for initiating control of the transition to the modulation state, the second delay being greater than the first delay.

According to one embodiment, the second delay circuit is configured to generate a mask signal adapted to block the extracted clock signal at a constant reference level for the duration of the second delay.

According to one embodiment, the second delay circuit comprises a second capacitive element and a second current generator adapted to generate a second reference current adapted to obtain the second delay at a time when the second reference current is loaded by the second capacitive element.

According to one embodiment, the first delay circuit is configured to generate an inverse modulation signal adapted to modulate the load at the antenna terminal to zero or almost zero impedance in the modulation state for the duration of the first delay.

According to one embodiment, the first delay circuit comprises a first capacitive element and a first current generator adapted to generate a first reference current, the first delay circuit being configured to obtain the first delay when loading the first capacitive element with the first reference current.

Drawings

Further advantages and features of the invention will become apparent upon examination of the detailed description of examples and embodiments, which are not limiting of the attached drawings, wherein:

fig. 1 shows a contactless communication system;

FIG. 2 shows a timing diagram of the transponder;

FIG. 3 shows a first delay circuit and digital controller incorporated in a modulator;

FIG. 4 shows details of some of the timing diagrams of FIG. 2;

FIG. 5 shows a second delay circuit incorporated in the modulator; and

fig. 6 shows details of some of the timing diagrams of fig. 2.

Detailed Description

Fig. 1 shows a contactless communication system SYS, for example compatible with the near field communication technology "NFC" or the radio frequency identification technology "RFID".

The system SYS comprises a card reader RDR and a passive transponder CRD, for example an integrated circuit card (such as a bank card) or a tag.

The reader includes an antenna Lr and a magnetic field generator, and the reader contains a carrier signal on the antenna Lr, typically a sine wave at 13.56 MHz.

The passive transponder CRD comprises an antenna Lc intended to be inductively coupled with the antenna Lr of the reader RDR, and an electronic circuit, for example generated in an integrated manner. The total impedance of the electronic circuit of the transponder CRC on the terminal of the antenna Lc is represented by the load LD.

The term "passive" in the general meaning in the field of contactless communication means, in particular, that the NFC or RFID type, and more specifically the transponder is passive, i.e. the reference clock signal it uses to clock the contactless communication is exclusively based on a carrier signal provided by the reader.

In this respect, the transponder CRD comprises a clock extraction circuit CLK EXTR configured to generate a clock signal RF CLK extracted from the carrier signal received at the terminal of its antenna Lc.

The transponder CRD comprises a modulator MMOD configured to amplitude-inversely modulate the carrier signal in alternation in the modulated and unmodulated state. The modulator MMOD is configured to generate an inverse modulation signal so as to control whether the modulation load LDMOD is coupled or not to the terminal of the antenna Lc.

In the unmodulated state, the modulating load LDMOD is not coupled to the terminals of the antenna Lc, the impedance at the antenna terminals being defined by the (non-zero) impedance of the transponder CRD circuit, referred to as the total load LD. In the modulated state, the modulation load LDMOD is additionally coupled to a terminal of the antenna Lc in parallel with the total load LD, and the impedance at the antenna terminal is mainly defined by the impedance of the modulation load LDMOD.

The modulation load LDMOD has zero impedance and is represented by a switch diagram coupled to the terminal of the antenna Lc. However, modulating the load LDMOD may be performed by a transistor controlled by an inverse modulation signal or alternatively a resistive or capacitive circuit with zero impedance.

A zero or almost zero impedance refers to an impedance which is negligible compared to the impedance of the total load LD of the transponder CRD circuit coupled to the antenna Lc, in particular the impedance considered at the carrier signal frequency. For example, the zero or almost zero impedance may be considered to be limited to a maximum of a few percent (e.g. 2%) of the non-zero impedance at the antenna terminals in the unmodulated state, i.e. a few percent of the total load LD.

The total load LD of the electronic circuit at the terminal of the antenna Lr comprises the impedance of the clock extraction circuit CLK EXTR and the modulator MMOD, as well as typical circuits such as a power manager (not shown) of the limiting and rectifying circuit type.

Fig. 2-6 illustrate exemplary embodiments and implementations of the modulator MMOD.

Fig. 2 illustrates timing diagrams G1-G6 of the main signals involved in the transponder CRD, in particular the modulator MMOD, during transmission of a data frame.

The graph G1 shows a sinusoidal carrier signal from the reader RDR, with two components AC0, AC1, located on the two terminals of the transponder antenna Lc.

The graph G2 shows the clock signal RF _ CLK extracted from the carrier signal by the clock extraction circuit CLK _ EXTR.

Fig. G3 shows the masked clock signal RF _ CLK _ MSK, described below in conjunction with fig. 5 and 6.

The graph G4 shows the modulation control signal mod _ dig at the origin of the control of the transition from the unmodulated state endod to the modulated state EMOD (before resynchronization).

The graph G5 shows the generation of the masking signal MSK (solid line), in particular the second delay t2 generated by the load VC2 of the second capacitive circuit (dashed line), as described below with respect to fig. 5 and 6.

Graph G6 shows the inverse modulation signal retromod (solid line) generated by the first delay t1 generated by the load VC1 of the first capacitance circuit (dashed line), as described below with respect to fig. 3 and 4.

The transmission of the data frame takes place by means of bursts of alternately modulated states EMOD and unmodulated states ENMOD, for example in a manchester type of coding.

The rising edge of the modulation control signal mod _ dig controls the generation of the backward modulation signal tromod to high level "1".

The high level "1" inverse modulation signal controls the modulation state EMOD, that is to say the modulation of the load LDMOD at the terminal of the antenna Lc to zero impedance. Therefore, when the inverse modulation signal retromod is at "1", the amplitudes of the carrier signals AC0, AC1 decrease to a substantially zero value, and the clock extraction circuit CLK _ EXTR is no longer able to detect the period of the carrier signal, and the clock signal RF _ CLK is maintained at a constant level.

When the load VC1 of the first capacitance circuit MF1, C1 (fig. 3) switches the CMOS inverter circuit (fig. 3), i.e., exceeds half of the high level, the generation duration of the inverse modulation signal is determined by the first delay t 1.

The switching CMOS inverter circuit may control the falling edge of the inverse modulation signal retromod to a low level "0" resulting in a transition from the modulated state EMOD to the unmodulated state ENMOD.

In the unmodulated state ENMOD, the load LDMOD at the terminal of the antenna Lc is no longer modulated to zero impedance, the carrier signals AC0, AC1 have their original amplitude, and the extraction of the clock signal RF _ CLK is resumed.

Refer to fig. 3.

Fig. 3 shows that the first delay circuit MF1 and the digital controller DIG _ CNT generate the modulation control signal mod _ DIG, and the first delay circuit MF1 and the digital controller DIG _ CNT are incorporated in the modulator MMOD.

In this example, the first delay circuit MF1 has a "one-shot" or "monostable latch" type architecture, including a CMOS input inverter component P1-N1, the output of which reaches the input of a CMOS output inverter component P2-N2, powered by a high reference voltage Vdd and a low reference voltage gnd.

A first synchronization control signal MF1_ in derived from the modulation control signal mod _ dig is provided to the input of the CMOS input inverter component P1-N1 through an inverter INV _ in.

Capacitive element C1 is coupled between the output of the first CMOS inverter assembly P1-N1 and the terminal at the low reference voltage gnd.

Current source Igen1 applies a first current I1, e.g., a maximum current, in the conduction terminal of P-type transistor P1 of CMOS input inverter assembly P1-N1 through current mirror assembly P3-P4.

Therefore, when the control signal MF1_ in is at a low level, the capacitive element C1 is short-circuited by the transistor N1 in a conductive state, and the delay circuit MF1 directly sends the high reference level Vdd on its output MF1_ out. When the control signal MF1_ in is at a high level, the capacitive element C1 is loaded by the current I1 via the transistor P1 which is in a conducting state, the voltage VC1 (fig. 2, G6) has the shape of a rising slope at the input of the CMOS output inverter component P2-N2, and the delay circuit MF1 transmits a low reference level gnd on its output MF1_ out with a delay of the duration t1 taken by the voltage VC1 to reach the threshold voltage of the transistor N2.

The and gate between the control signal MF1_ in and the output MF1_ out of the first delay circuit MF1 allows generating a clear falling edge on the modulation signal retromod at the switching instant defined by the delay t 1.

Thus, the duration of the modulation state is precisely defined at the time instant determined by the first delay t1 after receipt of the modulation control signal mod _ dig.

In fact, the first synchronization control signal MF1_ in originates from the modulation control signal mod _ dig, and in a simple exemplary embodiment, the modulation control signal mod _ dig may directly control the input on the inverter INV _ in of the delay circuit MF 1.

However, in this exemplary embodiment, the first synchronization control signal MF1_ in is derived from the modulation control signal mod _ dig, and further, its transitions on the falling edge of the masking clock signal RF _ CLK _ MSK and the rising edge of the extraction clock signal RF _ CLK are synchronized by the corresponding flip-flop D.

The signal generated by synchronously modulating the control signal mod _ dig on the falling edge of the mask clock signal RF _ CLK _ MSK is referred to as a second control signal (inverse latch) and is used to control a second delay circuit (MF2) described below in connection with fig. 5 and 6.

Thus, the first control signal MF1_ in and the second control signal retro _ latch are coordinated from the modulation control signal mod _ dig to be shifted from each other. This allows to ensure a robust operation of the contactless communication, avoiding spurious effects in the generation of signals of the clock cycle desynchronization type.

Fig. 4 shows details of G1, G2, and G6 of fig. 2, and G41 shows synchronization control signal MF1_ in.

Thus, it can be seen in fig. 4 that the rising edge of the synchronization control signal MF1_ in is synchronized with the rising edge of the clock signal RF _ CLK, and the rising edge is generated directly in the signal retromod (so that the received values MF1_ in ═ 1 "and MF1_ out ═ 1") by the action of the and gate at the output of the first delay circuit MF 1.

After a duration t1, when the voltage slope VC1 at the terminal of capacitive element C1 switches transistor P2, the and gate generates a falling edge in signal retromod (MF1_ in ═ 1 "and MF1_ out ═ 0").

The falling edge of the control signal MF1_ in occurs after the falling edge of the inverse modulation signal retromod, and directly switches the output of the first delay circuit MF1_ out to "1", and the output of the and gate is held at 0(MF1_ in ═ 0 "and MF1_ out ═ 1").

The falling edge of the inverse modulation signal retromod marks the end of the modulated state EMOD and the moment of transition from the modulated state to the unmodulated state ENMOD.

In summary, the modulator MMOD comprises a first delay circuit MF1 configured to generate a first delay t1 and an inverse modulation signal retromod. The inverse modulation signal retromod controls, on the one hand, the modulation of the load LDMOD at the terminal of the antenna Lc at zero impedance in the modulated state and, on the other hand, the transition from the modulated state EMOD to the unmodulated state ENMOD at the instant determined by the first delay t 1.

At the beginning of the unmodulated state ENMOD, the carrier signals AC0, AC1 at the terminals of the transponder antenna Lc may have an unstable phase, in which a settling time STB is required to restore a level of sufficient amplitude to guarantee the correct extraction of the signal RF _ clock, depending on the nature of the total load RD and on the distance between the reader RDR and the transponder CRD.

During the settling time, the extraction of the clock signal RF _ CLK may be disturbed, which may introduce a risk of errors in the timing based on the extracted clock signal RF _ CLK.

Reference is made in this respect to fig. 5 and 6.

Fig. 5 shows a second delay circuit MF2 integrated in the modulator MMOD, which is configured to generate the masking signal MSK masking the clock signal RF _ CLK during the settling time STB.

Like the first delay circuit MF1, the second delay circuit MF2 has a "one-shot" or "monostable latch" type architecture. Common elements between the first delay circuit MF1 and the second delay circuit MF2 have the same reference numerals and will not be described in full detail.

It should be noted, however, that in the second delay circuit MF2, the current generator Igen2 generates a current I2 different from the current I1, and/or the second capacitive element C2 has a different capacitance value from the first capacitive element C1.

The input of the second delay circuit MF2 is at the input of the inverter INV _ in, and the output signal MF2_ out of the second delay circuit MF2 is provided by the inverter INV _ out connected to the CMOS output inverter components P2-N2.

The signal provided at the input of the inverter INV _ in that controls the second delay circuit MF2 comes from the output RS _ out of the nor gate latch RS.

The initialization input ("set") of the latch RS receives the pulse retrolatchjpulse generated by the pulse generator PLSGEN on the rising edge of the modulation control signal mod _ dig or, advantageously, in the framework of the exemplary embodiments described in relation to fig. 2 to 6, on the rising edge of the second synchronization control signal.

The reset input of latch RS receives the output signal MF2_ out from the second delay circuit MF 2.

Further, the output RS _ out of the latch RS provides the mask signal MSK through the inverter INV _ MSK. The mask signal controls the follower amplifier GT CLK so that if the mask signal is "1" (hence, if the signal on RS out is "0"), the follower amplifier retransmits the extracted clock signal RF CLK on its output RF CLK MSK, and if the mask signal is "0" (hence, if the signal on RS out is "1"), the constant signal which is retransmitted and at low level "0" on its output RF CLK MSK.

In other words, the mask signal MSK is adapted to block the extracted clock signal RF _ CLK _ MSK at a constant reference level.

Refer to fig. 6.

Fig. 6 shows details of fig. G2 and G3 in fig. 2, a diagram G41 shows the second synchronization control signal retrolatch, a diagram G42 shows the pulse retrolatch _ pulse, a diagram G51 shows the output MF2_ out (solid line) of the second delay circuit MF2 and the voltage at the terminal of the second capacitive element C2 (dashed line), and a diagram G52 shows the signal at the output RS _ out of the latch RS.

Therefore, referring to fig. 5 and 6, when the modulation control signal (retrolatch) is at the high level "1", the pulse retrolatch _ pulse initializes the output RS _ out to "1". The use of a pulse retrolatch pulse instead of the signal retrolatch avoids the conflict between the initialization and reset inputs of the latch RS.

On the one hand, the mask signal MSK is at "0" and the mask clock signal RF _ CLK _ MSK is blocked at "0" regardless of the behavior of the extracted clock signal RF _ CLK.

On the other hand, the output RS _ out at "1" controls the loading mechanism of the second capacitive element C2 according to the voltage slope VC 2. The duration t2 required for the voltage slope VC2 to reach half of the high level "1" is configured to be greater than the duration of the first delay t 1.

After a second delay t2, the output MF2_ out of the second delay circuit switches to "1", and the output RS _ out of the latch RS is reset to "0".

On the one hand, the output MF2_ out of the delay circuit MF2 immediately switches to "0".

On the other hand, the mask signal MSK returns to "1", and the follower amplifier GT _ CLK retransmits the clock signal RF _ CLK on its output RF _ CLK _ MSK.

The first delay t1 determines the transition to the unmodulated state and the etching to recover the extracted clock signal, and the second delay t2 determines the end of the clock signal RF _ CLK _ MSK masking, the difference between the first delay t1 and the second delay t2 being selected to mask the extracted clock signal RF _ CLK during the settling time STB.

Thus, after the second delay t2, the operation of control circuit DIG _ CNT (fig. 4) may be clocked using the masking clock signal RF _ CLK _ MSK without risk.

In particular, the control circuit DIG _ CNT is configured to generate a modulation control signal mod _ DIG controlling the transition from the unmodulated state to the modulated state at instants defined by measuring the duration over a clock cycle of the masking clock signal RF _ CLK _ MSK.

Knowing the duration of the delays t1 and t2, the count of clock cycles is adapted to count the number remaining after the difference t2-t 1.

In summary, the modulator MMOD advantageously comprises a second delay circuit MF2, which second delay circuit MF2 is configured to generate a second delay t2 at the origin of the control transition to the modulation state from the modulation control signal mod _ dig, which second delay t2 starts from a time coordinated with the start of the measurement of the first delay t 1. The control circuit DIG _ CNT is configured to measure the remaining time of the unmodulated state on a clock cycle of the mask clock signal RF _ CLK _ MSK derived from the extracted clock signal RF _ CLK after a second delay t 2. Thus, the control circuit DIG _ CNT may initiate the next control of the transition from the unmodulated state to the modulated state by modulating the control signal mod _ DIG in a manner coherent and precisely synchronized with the carrier signals AC0, AC1, although this signal is lost in the modulated state.

Furthermore, whereas the first and second delays t1, t2 are defined by the strength of the constant currents I1, I2 and the capacitance values of the first and second capacitive elements C1, C2, the examples and embodiments may provide for calibration of the delays t1, t2 according to the actual extracted clock signal.

This calibration can be carried out, for example, before the data transmission, for example at the start of the transponder CRD, or during the "emd" (for "electromagnetic interference") time provided by the customary contactless communication standards before the data transmission of the transponder, during which the transponder must have a constant impedance.

Adjusting the intensity of the first current I1 and the second current I2, and adjusting the capacitance values of the first capacitive element C1 and the second capacitive element C2, the duration of the first delay t1 and the second delay t2 can be conveniently and accurately calibrated.

Thus, the above-described embodiments and implementations allow the use of zero impedance in the modulated state TX to improve the performance of the transponder, thereby increasing the communication distance. This improvement is possible by using a mechanism that compensates for the fact that the clock is not available in the modulated state using a delay. This ensures the consistency of the clock frequency of the frame TX with the carrier RF.

Claims (20)

1. A contactless communication method, comprising:

receiving a carrier signal at a terminal of an antenna; and

-inverse modulating the carrier signal in alternation between modulated and unmodulated states, the inverse modulation comprising:

modulating a load at a terminal of the antenna with a non-zero impedance in the unmodulated state;

modulating a load at a terminal of the antenna with zero or nearly zero impedance in the modulated state; and

controlling a transition from the modulated state to the unmodulated state at a first time determined by a first delay.

2. The method of claim 1, further comprising: controlling the transition from the unmodulated state to the modulated state at a second time instant, the second time instant being determined by a duration measured on a clock cycle generated by a clock signal extracted from the carrier signal, the measurement of the duration being started from a third time instant determined by a second delay, the third time instant determined by the second delay being subsequent to the first time instant of the transition to the unmodulated state.

3. The method of claim 2, further comprising coordinating the measurement of the second delay and the measurement of the first delay starting at respective times with a modulation control signal that initiates controlling the transition to the modulation state, the second delay being greater than the first delay.

4. The method of claim 2, further comprising generating a mask signal that blocks the extracted clock signal at a constant reference level for the duration of the second delay.

5. The method of claim 2, further comprising obtaining the second delay by loading a time of a second capacitive element with a second reference current.

6. The method of claim 1, further comprising controlling the load modulation at the terminals of the antenna with zero or near zero impedance of the modulation state by an inverse modulation signal generated for a duration determined by the first delay.

7. The method of claim 1, further comprising obtaining the first delay by loading a time of a first capacitive element with a first reference current.

8. A contactless communication transponder, comprising:

an antenna comprising a terminal and configured to receive a carrier signal; and

a modulator comprising a first delay circuit configured to generate a first delay, the modulator configured to inverse modulate the carrier signal in alternation of modulated and unmodulated states, the inverse modulation comprising configuring the modulator to:

modulating a load at a terminal of the antenna with a non-zero impedance in the unmodulated state;

modulating a load at a terminal of the antenna with zero or nearly zero impedance in the modulated state; and

controlling a transition from the modulated state to the unmodulated state at a first time instant determined by the first delay.

9. The transponder of claim 8, further comprising a clock extraction circuit configured to generate a clock signal extracted from the carrier signal, wherein the modulator further comprises:

a second delay circuit configured to generate a second delay; and

a control circuit configured to:

measuring a duration of a clock cycle of the extracted clock signal from a third time instant determined by the second delay, the third time instant determined by the second delay being subsequent to the first time instant of the transition to the unmodulated state; and

generating a modulation control signal at a second time instant determined by the measured duration, the modulation control signal controlling the transition from the unmodulated state to the modulated state.

10. The transponder of claim 9, wherein the first delay circuit and the second delay circuit are configured to begin measurement of the first delay and measurement of the second delay, respectively, at respective times coordinated with a modulation control signal generated by the control circuit to control the transition to the modulation state, wherein the second delay is greater than the first delay.

11. The transponder of claim 9, wherein the second delay circuit is configured to generate a mask signal for the duration of the second delay to block the extracted clock signal at a constant reference level.

12. The transponder of claim 9, wherein the second delay circuit comprises:

a second capacitance element; and

a second current generator configured to generate a second reference current;

wherein the second delay circuit is configured to obtain the second delay from a time that the second capacitive element is loaded with the second reference current.

13. The transponder of claim 8, wherein the first delay circuit is configured to generate an inverse modulation signal to control modulation of the load at the terminals of the antenna to zero impedance or nearly zero impedance in the modulation state for the duration of the first delay.

14. The transponder of claim 8, wherein the first delay circuit comprises:

a first capacitive element; and

a first current generator configured to generate a first reference current;

wherein the first delay circuit is configured to obtain the first delay from a time that the first capacitive element is loaded with the first reference current.

15. A contactless communication transponder, comprising:

an antenna comprising a terminal and configured to receive a carrier signal;

a clock extraction circuit configured to generate a clock signal extracted from the carrier signal; and

a modulator configured to inversely modulate the carrier signal in alternation of a modulated state and an unmodulated state, the modulator comprising:

a first delay circuit configured to generate a first delay,

a second delay circuit configured to generate a second delay; and

a control circuit configured to:

modulating a load at a terminal of the antenna with a non-zero impedance in the unmodulated state;

modulating a load at a terminal of the antenna with zero or nearly zero impedance in the modulated state;

controlling a transition from the modulated state to the unmodulated state at a first time determined by the first delay;

measuring a duration of a clock cycle of the extracted clock signal from a third time instant determined by the second delay, the third time instant determined by the second delay being subsequent to the first time instant of the transition to the unmodulated state; and

generating a modulation control signal at a second time instant determined by the measured duration, the modulation control signal controlling the transition from the unmodulated state to the modulated state.

16. The transponder of claim 15, wherein the first delay circuit is configured to generate an inverse modulation signal to control modulation of the load at the terminals of the antenna to zero impedance or near zero impedance in the modulation state for the duration of the first delay.

17. The transponder of claim 15, wherein the first delay circuit and the second delay circuit are configured to begin measurement of the first delay and measurement of the second delay, respectively, at respective times coordinated with a modulation control signal generated by the control circuit to control the transition to the modulation state, wherein the second delay is greater than the first delay.

18. The transponder of claim 15 wherein the second delay circuit is configured to generate a mask signal for the duration of the second delay to block the extracted clock signal at a constant reference level.

19. The transponder of claim 15 wherein the second delay circuit comprises:

a second capacitance element; and

a second current generator configured to generate a second reference current;

wherein the second delay circuit is configured to obtain the second delay from a time that the second capacitive element is loaded with the second reference current.

20. The transponder of claim 15, wherein the first delay circuit comprises:

a first capacitive element; and

a first current generator configured to generate a first reference current;

wherein the first delay circuit is configured to obtain the first delay from a time that the first capacitive element is loaded with the first reference current.

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