CN114647595A - Solid state disk and data processing method - Google Patents
Solid state disk and data processing method Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0871—Allocation or management of cache space
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
- G06F2212/1021—Hit rate improvement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
- G06F2212/1024—Latency reduction
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/20—Employing a main memory using a specific memory technology
- G06F2212/202—Non-volatile memory
- G06F2212/2022—Flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/21—Employing a record carrier using a specific recording technology
- G06F2212/214—Solid state disk
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Abstract
The invention provides a solid state disk and a data processing method, wherein the solid state disk comprises a peripheral interface, a control chip, a flash memory chip set and a cache chip set, and the solid state disk is connected with an external bus through the peripheral interface, wherein: the flash memory chip set comprises a plurality of data storage blocks, the flash memory chip set comprises a mapping table storage area, and the control chip obtains the data to be read from the flash memory chip set and writes all data in the data storage block where the data to be read is located into the cache chip set when the peripheral interface receives a read data command and the cache chip set does not have the data to be read corresponding to the read data command. The invention can directly write the data in the cache chipset into the flash chipset when updating the data by taking the block as the minimum unit to move the data from the flash chipset to the cache chipset, thereby avoiding multiple times of reading and writing of the data and greatly improving the data processing speed of the solid state disk.
Description
Technical Field
The invention relates to the field of computer equipment, in particular to a solid state disk and a data processing method.
Background
The solid state disk is a hard disk made of a solid state electronic storage chip array and mainly comprises a control unit and a storage unit (a FLASH chip and a DRAM chip). Due to the advantages of the solid state disk in the aspects of data reading, environment application and the like, the solid state disk is widely applied to the fields of military affairs, vehicle-mounted, industrial control, video monitoring, network terminals, electric power, medical treatment, aviation, navigation equipment and the like.
The conventional solid state disk usually employs NAND FLASH chips as main storage units, and the minimum read-write unit is a data Page (Page), while most data pages are 4KB in size, i.e. the minimum read-write unit of NAND FLASH chips is 4KB in size.
However, NAND FLASH chips typically perform erase operations in units of data storage blocks (blocks), each of which typically includes several pages of data. When a part of data pages in the data storage block are updated, all data in the data storage block need to be moved, so that the operation speed is slow. Moreover, when the system performs data processing, the probability that adjacent commands are processed simultaneously is often higher, and the conventional manner of reading and writing data in units of data pages also affects the speed of command response.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a new solid state disk and a data processing method, aiming at the problem that the overall read-write speed and response speed of the solid state disk are affected by reading and writing data with a data page as the minimum unit.
The technical solution for solving the above technical problem is to provide a solid state disk, which includes a peripheral interface, a control chip, a flash memory chip set and a cache chip set, and the solid state disk is connected to an external bus through the peripheral interface, wherein:
the flash memory chip set comprises a plurality of data storage blocks, and the control chip is respectively connected with the flash memory chip set, the cache chip set and the peripheral interface;
the flash memory chip set comprises a mapping table storage area, when the peripheral interface receives a read data command and the cache chip set does not have to-be-read data corresponding to the read data command, the control chip acquires the to-be-read data from the flash memory chip set, writes all data in a data storage block where the to-be-read data is located into the cache chip set, establishes a mapping relation according to the physical position of the data storage block and the physical position of the to-be-read data in the cache chip set, and writes the mapping relation into the mapping table storage area.
As a further improvement of the present invention, the cache chipset comprises a plurality of logical memory blocks, and the logical memory blocks and the data memory blocks have the same memory capacity;
when the peripheral interface receives a read data command and the cache chipset does not have data to be read corresponding to the read data command, the control chip acquires the data to be read from the flash chipset, writes all data in a data storage block where the data to be read is located into one logic storage block of the cache chipset, establishes a mapping relation according to the physical position of the data storage block and the physical position of the logic storage block, and writes the mapping relation into the mapping table storage area.
As a further improvement of the present invention, a block maintenance table is stored in the control chip, and the block maintenance table includes a state of each data storage block in the flash memory chip set;
when the control chip writes the updated data in the cache chipset into the flash memory chipset, writing all the data of the logic storage block where the data to be written in the cache chipset is located into a free data storage block of the flash memory chipset according to the block maintenance table in the cache chipset, erasing the data in the data storage block corresponding to the logic storage block according to the mapping relation in the mapping table storage area, and updating the block maintenance table.
The invention also provides a data processing method which is applied to a solid state disk, wherein the solid state disk comprises a peripheral interface, a control chip, a flash memory chip set and a cache chip set, the solid state disk is connected with an external bus through the peripheral interface, the flash memory chip set comprises a plurality of data storage blocks, and the control chip is respectively connected with the flash memory chip set, the cache chip set and the peripheral interface; the method comprises the following steps performed by the control chip:
receiving a data processing command from the external bus through the peripheral interface;
when the data processing command is a read data command, retrieving the cache chip set, and when the cache chip set does not have to-be-read data corresponding to the read data command, acquiring the to-be-read data from the flash memory chip set and writing all data in a data storage block where the to-be-read data is located into the cache chip set;
and establishing a mapping relation according to the physical position of the data storage block and the physical position of the data to be read in the cache chip set, and writing the mapping relation into the mapping table.
As a further improvement of the present invention, the cache chipset comprises a plurality of logical memory blocks, and the logical memory blocks and the data memory blocks have the same memory capacity;
the writing all the data in the data storage block where the data to be read is located into the cache chipset includes: writing all data in the data storage block where the data to be read is located into a logic storage block of the cache chipset;
the establishing of the mapping relationship according to the physical location of the data storage block and the physical location of the data to be read in the cache chipset includes: and establishing a mapping relation according to the physical position of the data storage block and the physical position of the logic storage block and writing the mapping relation into the mapping table storage area.
As a further improvement of the present invention, a block maintenance table is stored in the control chip, and the block maintenance table includes a state of each data storage block in the flash memory chip set; the method further comprises the following steps:
when the updated data in the cache chipset is written into the flash memory chipset, writing all the data of a logic storage block where the data to be written in the cache chipset is located into a free data storage block of the flash memory chipset according to a block maintenance table in the cache chipset, and updating the block maintenance table;
and erasing the data in the data storage block corresponding to the logic storage block according to the mapping relation in the mapping table storage area, and updating the block maintenance table.
As a further improvement of the present invention, the writing all data of the logic storage block in which the data to be written in the cache chipset is located into an idle data storage block of the flash memory chipset includes:
generating a plurality of data pages according to all data of a logic storage block where data to be written are located, wherein each data page comprises an ECC (error correction code) check code;
writing a plurality of the data pages into the same free data storage block of the flash memory chip set.
As a further improvement of the present invention, the acquiring the data to be read from the flash memory chip set and writing all data in the data storage block where the data to be read is located into the cache chip set includes:
retrieving the flash memory chip set to acquire the data to be read;
reading each data page from a data storage block where the data to be read is located, and checking each data page according to an ECC (error correction code) check code of each data page;
after the verification is passed, writing each data page into the flash memory chip set.
As a further improvement of the present invention, the method further comprises the following steps performed by the control chip:
when a preset condition is reached, selecting a plurality of logic storage blocks which are hit by the read data command within a preset time from the cache chip set;
writing all data of the logic storage blocks with the least hit frequency into a plurality of idle data storage blocks of the flash memory chip set according to a block maintenance table in the cache chip set, and updating the block maintenance table;
and erasing the data in the data storage block corresponding to the logic storage block according to the mapping relation in the mapping table storage area, and updating the block maintenance table.
As a further improvement of the present invention, the preset conditions are: the cache chipset is full or reaches a preset time.
According to the solid state disk and the data processing method, the data are moved from the flash memory chip set to the cache chip set by taking the block as the minimum unit, so that the data in the cache chip set can be directly written into the flash memory chip set when the data are updated, multiple times of reading and writing of the data are avoided, and the data processing speed of the solid state disk is greatly improved. Meanwhile, data with higher hit rate is moved to the cache chip set in advance, so that the response speed of the solid state disk is greatly improved.
Drawings
Fig. 1 is a schematic diagram of a solid state disk provided in an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a principle of a data caching operation of a solid state disk according to an embodiment of the present invention;
FIG. 3 is a flow chart of a data processing method according to an embodiment of the present invention;
fig. 4 is a schematic flowchart of a more-line block maintenance table in the data processing method according to the embodiment of the present invention;
fig. 5 is a schematic flowchart illustrating a process of writing data in a cache chipset into a flash memory chipset in a data processing method according to an embodiment of the present invention;
fig. 6 is a schematic flow chart illustrating a process of transferring data stored in a flash memory chipset to a cache chipset in a data processing method according to an embodiment of the present invention;
fig. 7 is a schematic flowchart illustrating another process of moving data stored in a flash memory chipset to a cache chipset in the data processing method according to the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Fig. 1 is a block diagram of a solid state disk of the present invention, which is applicable to a computer system, such as a personal computer, a server, etc., and is used for data storage. The solid state disk of the embodiment includes a peripheral interface 11, a control chip 12, a flash memory chip set 13, and a cache chip set 14. In the present embodiment, the peripheral interface 11 is used for connecting to an external bus (e.g., PCIe bus) of the computer system to perform data interaction with a central processing unit of the computer system. Specifically, the peripheral interface 11 may adopt a SATA interface, a mSATA interface, an NGFF interface, a PCLE interface, an ATA interface, a SCSI interface, or the like.
The FLASH memory chip set 13 is used for data storage and includes one or more FLASH memory (FLASH) chips, which may specifically employ NAND FLASH memory chips, etc., which have relatively large storage capacity, relatively low cost, and relatively slow data access speed, and can store data in a power-off state. As shown in fig. 2, the flash chipset 13 includes a plurality of data storage blocks (blocks) 131 with the same storage capacity, each data storage Block 131 can store a plurality of pages (pages), and the flash chipset 13 uses a Block as a minimum erase unit, that is, when any data stored in the data storage Block 131 changes, the data stored in the entire data storage Block 131 needs to be erased (the erase operation can be performed during idle time), and the data updated before the erase and the data in the data storage Block 131 that has not changed are stored in a new data storage Block 131.
The cache chipset 14 includes one or more DRAM chips, and the DRAM chips may specifically adopt memory chips such as DDR, DDR2, DDR3, DDR4, DDR5, or phase change memory, which have relatively small memory capacity, relatively high cost, and relatively high data access speed, and cannot retain stored data when the power is off. Since the data access speed of the flash chipset 13 is much slower than the high speed devices of the computer system (e.g., the memory of the computer system), the cache chipset 14 may have a speed difference between the two. That is, the cache chipset 14 may temporarily store the data to be stored in the flash memory chipset 13 and then slowly store the data in the flash memory chipset 13. In this embodiment, the flash memory chip set includes a mapping table storage area and a data storage area (for example, the mapping table storage area may be located at a starting position of a physical address of the cache chip set 14), and the mapping table storage area stores a corresponding relationship between storage data in the record data storage area and storage data in the flash memory chip set 13.
The control chip 12 is connected to the peripheral interface 11, the flash memory chip set 13 and the cache chip set 14, respectively, and performs data processing and transceiving. For example, the control chip 12 may be connected to the flash chipset 13 through a NAND flash bus, to the cache chipset 14 through a DRAM bus, and to the peripheral interface 11 through a PCIe bus. In this embodiment, when the peripheral interface 11 receives a read data command (for example, from a central processing unit of a computer system in which the solid state disk is located), the control chip 12 retrieves data to be read corresponding to the read data command from the cache chipset 14, and when the data to be read is not retrieved (i.e., the data to be read does not exist in the cache chipset 14), the control chip 12 obtains the data to be read from the flash chipset 13 and writes all data in the data storage block 131 in which the data to be read is located into the data storage area of the cache chipset 14, and establishes a mapping relationship with a physical location (i.e., an address) of the data storage block 131 and a physical location of the data to be read in the cache chipset 14 and writes the mapping relationship into the storage area.
Thus, the central processing unit (or DMA) of the computer system where the solid state disk is located can directly write updated data (for example, an instruction execution result) into the cache chipset 14, and the control chip 12 directly writes data (updated) corresponding to the storage capacity of the data storage block 131 in the cache chipset 14 into a new data storage block 131 of the flash memory chipset 13 according to an instruction or a set rule, erases data in the data storage block 131 originally used for storing the corresponding data, and updates the mapping relationship in the cache chipset 14.
The solid state disk transfers data from the flash memory chip set 13 to the cache chip set 14 by taking the block as the minimum unit, so that the data in the cache chip set 14 can be directly written into the flash memory chip set 13 when the data is updated, multiple times of reading and writing of the data are avoided (namely, other data in the data storage block 131 do not need to be read from the flash memory chip set and transferred), and the data processing speed of the solid state disk is greatly improved. Meanwhile, since the data with higher hit rate (i.e. the data stored in other data pages in the same data storage block 131, due to the continuity of data processing, the possibility that this part of data is often read by the central processing unit is higher) is moved to the cache chipset in advance, the response speed of the solid state disk (i.e. the speed of responding to the read data command of the central processing unit) is also greatly improved.
In an embodiment of the present invention, as shown in fig. 2, the data storage area of the cache chipset 14 includes a plurality of logical storage blocks 141 with the same storage capacity, and the logical storage blocks 141 have the same storage capacity as the data storage blocks 131 of the flash memory chipset 13.
Correspondingly, when the external interface 11 receives a read data command and the cache chipset 14 does not have data to be read corresponding to the read data command, the control chip 12 obtains the data to be read from the flash chipset 13, writes all data in the data storage block 131 where the data to be read is located into one logical storage block 141 of the cache chipset 14, and establishes a mapping relationship with the physical location of the data storage block 131 according to the physical location (address) of the logical storage block 141 and writes the mapping relationship into a mapping table storage area.
By providing the logical storage block 141 in the cache chipset 14 to store data read by the flash memory chipset 13, the data structure of the cache chipset 14 can be simplified. Moreover, in order to improve the data access efficiency, each of the above logical memory blocks 141 may be formed by a memory space with continuous physical addresses in the cache chipset 14.
In an embodiment of the present invention, the solid state disk may also adopt an Open Channel (Open Channel) structure, that is, the data storage structure in the flash memory chipset 13 is directly performed by the central processing unit of the computer system. At this time, the control chip 12 stores therein a block maintenance table, which includes the status of each data storage block 131 in the flash memory chipset 13, wherein the status of the data storage block in the block maintenance table includes occupied, free, bad block, and the like. Specifically, the block maintenance table may be stored in the flash memory chipset 13, and the control chip 12 is loaded when the computer system where the solid state disk is located is started, and is maintained by the control chip 12, for example, when a certain data storage block in the flash memory chipset 13 fails, the control chip 12 modifies the state of the corresponding data storage block 131 in the block maintenance table to be a bad block.
When the peripheral interface 11 receives a write data command, the control chip 12 writes all data in the logic storage block 141 where the to-be-written data corresponding to the write data command in the cache chipset 14 is located in a free data storage block 131 of the flash memory chipset 13 according to the block maintenance table in the cache chipset 14, erases the data in the data storage block corresponding to the logic storage block according to the mapping relationship in the storage area of the mapping table, and updates the block maintenance table (for example, the state of the data storage block in which data is newly written in the block maintenance table is modified to be occupied, and the state of the data storage block in which data is erased is free).
In practical applications, the control chip 12 may also write the storage data of a part of the logic storage blocks 141 in the cache chipset 14 into the free data storage blocks 131 in the flash memory chipset 13 according to a preset rule when the storage space of the cache chipset 14 is full, and empty the original logic storage blocks 141 for use in subsequent operations. For example, the preset rule may be that the logical storage block 141 has not been accessed within a preset time, or the data storage block 131 that has not been accessed for the longest time from the current time, and the like.
With reference to fig. 3, an embodiment of the present invention further provides a data processing method, where the method is applicable to a solid state disk, where the solid state disk includes a peripheral interface, a control chip, a flash memory chip set, and a cache chip set, the solid state disk is connected to an external bus through the peripheral interface, the flash memory chip set includes multiple data storage blocks, and the control chip is connected to the flash memory chip set, the cache chip set, and the peripheral interface respectively. The specific structure of the solid state disk can refer to the embodiment corresponding to fig. 1, and is not described herein again.
The data processing method of the embodiment is executed by a control chip in a solid state disk, and the method comprises the following steps:
step S31: data processing commands are received from an external bus (e.g., a central processing unit of a computer system in which the solid state disk resides) through the peripheral interface.
Step S32: whether the data processing command received through the peripheral interface is a read data command is determined, step S34 is executed if the data processing command is a read data command, and step S33 is executed if the data processing command is another command (e.g., a write data command, a return operation result).
Step S33: the control unit writes the relevant data in the data processing command into the cache chip set.
Step S34: and retrieving the data to be read corresponding to the read data command in the cache chip set.
Step S35: and judging whether the data to be read corresponding to the read data command is retrieved from the cache chipset, and executing the step S37 when the data to be read is not retrieved (namely, the data to be read does not exist in the cache chipset), otherwise, executing the step S36.
Step S36: and returning the data to be read corresponding to the read data command to the external bus through the external interface.
Step S37: and acquiring the data to be read from the flash memory chip set, writing all the data in the data storage block where the data to be read is located into the cache chip set, and then respectively executing the step S36 and the step S38.
The data storage area of the cache chipset of the solid state disk may include a plurality of logic storage blocks, and the logic storage blocks and the data storage blocks of the flash memory chipset have the same storage capacity, and each logic storage block may occupy a storage area with continuous addresses. In the step, all data in the data storage block where the data to be read is located are directly written into one logic storage block of the cache chip set.
Step S38: and establishing a mapping relation according to the physical position of the data storage block and the physical position of the data to be read in the cache chip set, and writing the mapping relation into a mapping table. The mapping table may be located at the beginning of the physical address in the cache chipset.
When the data processing method is applied to an Open Channel (Open Channel) solid state disk, a block maintenance table is stored in a control chip, the block maintenance table comprises the state of each data storage block in a flash memory chip set, and the states of the data storage blocks in the block maintenance table comprise occupied blocks, idle blocks, bad blocks and the like. Specifically, the block maintenance table may be stored in the flash memory chip set, and the control chip is loaded when the computer system where the solid state disk is located is started, and is maintained by the control chip, for example, when a certain data storage block in the flash memory chip set fails, the control chip modifies the state of the corresponding data storage block in the block maintenance table to be a bad block.
Accordingly, as shown in FIG. 4, the data processing method of the present invention includes the following steps performed by the control chip in addition to the steps S31-S38:
step S41: writing all data in a logic storage block where data to be written in the cache chipset is located into a free data storage block of the flash memory chipset, and updating the block maintenance table (for example, modifying the state of a data storage block in which data is newly written in the block maintenance table to be occupied).
Step S42: and erasing the data in the data storage block corresponding to the logical storage block according to the mapping relation in the mapping table storage area, and updating the block maintenance table (for example, modifying the state of the data storage block with the erased data in the block maintenance table to be free).
In order to avoid data storage errors, in step S41 in fig. 4, writing all data in the logic storage block where the data to be written in the cache chipset is located into a free data storage block of the flash memory chipset, which may specifically include, as shown in fig. 5:
step S411: and generating a plurality of data pages (pages) according to all data of the logic storage block where the data to be written is located, wherein each data Page comprises an ECC check code. The ECC check code is obtained by performing error checking and correction calculation on all data of the data page where the ECC check code is located. When the data in the data page of the flash memory chip set is wrong, the correct data in the data page can be recovered through the ECC check code.
Step S412: and writing a plurality of data pages respectively comprising the ECC check code into the same free data storage block of the flash memory chip set.
Correspondingly, referring to fig. 6, step S37 in fig. 3 is to obtain the data to be read from the flash memory chipset and write all data in the data storage block where the data to be read is located into the cache chipset, and may specifically include the following steps executed by the control chip:
step S371: and searching the flash memory chip set to acquire the data to be read corresponding to the data reading command.
Step S372: reading each data page from a data storage block where data to be read is located, and checking each data page according to an ECC (error correction code) of each data page;
step S373: after the check passes, each page of data is written to the cache chipset. When the error is checked, the data can be recovered according to the ECC check code, so that the accuracy of the read data is improved.
Referring to FIG. 7, in another embodiment of the present invention, the following steps performed by the control chip are included in addition to the steps S31-S38:
step S71: and when a preset condition is reached, selecting a plurality of logic storage blocks which are hit by the read data command within a preset time from the cache chip set. Specifically, the preset condition may be: the cache chipset is full, or reaches a preset time, etc.
Step S72: according to the block maintenance table in the cache chipset, all data of a plurality of logic storage blocks with the least number of hits are written into a plurality of free data storage blocks of the flash memory chipset, and the block maintenance table is updated (for example, the state of the data storage block in which data is newly written is modified to be occupied).
Step S73: and erasing the data in the data storage block corresponding to the logical storage block according to the mapping relation in the mapping table storage area, and updating the block maintenance table (for example, modifying the state of the data storage block of the erased data to be free) for subsequent operation.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. The utility model provides a solid state hard drives, its characterized in that includes peripheral hardware interface, control chip, flash memory chipset and cache chipset, just solid state hard drives passes through peripheral hardware interface and external bus are connected, wherein:
the flash memory chip set comprises a plurality of data storage blocks, and the control chip is respectively connected with the flash memory chip set, the cache chip set and the peripheral interface;
the flash memory chip set comprises a mapping table storage area, when the peripheral interface receives a read data command and the cache chip set does not have to-be-read data corresponding to the read data command, the control chip acquires the to-be-read data from the flash memory chip set, writes all data in a data storage block where the to-be-read data is located into the cache chip set, establishes a mapping relation according to the physical position of the data storage block and the physical position of the to-be-read data in the cache chip set, and writes the mapping relation into the mapping table storage area.
2. The solid state disk of claim 1, wherein the cache chipset comprises a plurality of logical memory blocks, and the logical memory blocks have the same memory capacity as the data memory blocks;
when the peripheral interface receives a read data command and the cache chipset does not have data to be read corresponding to the read data command, the control chip acquires the data to be read from the flash chipset, writes all data in a data storage block where the data to be read is located into one logic storage block of the cache chipset, establishes a mapping relation according to the physical position of the data storage block and the physical position of the logic storage block, and writes the mapping relation into the mapping table storage area.
3. The solid state disk of claim 2, wherein the control chip stores a block maintenance table, the block maintenance table including a status of each data storage block in the flash memory chipset;
when the control chip writes the updated data in the cache chipset into the flash memory chipset, writing all the data of the logic storage block where the data to be written in the cache chipset is located into a free data storage block of the flash memory chipset according to the block maintenance table in the cache chipset, erasing the data in the data storage block corresponding to the logic storage block according to the mapping relation in the mapping table storage area, and updating the block maintenance table.
4. A data processing method is applied to a solid state disk and is characterized in that the solid state disk comprises a peripheral interface, a control chip, a flash memory chip set and a cache chip set, the solid state disk is connected with an external bus through the peripheral interface, the flash memory chip set comprises a plurality of data storage blocks, and the control chip is respectively connected with the flash memory chip set, the cache chip set and the peripheral interface; the method comprises the following steps performed by the control chip:
receiving a data processing command from the external bus through the peripheral interface;
when the data processing command is a read data command, retrieving the cache chip set, and when the cache chip set does not have to-be-read data corresponding to the read data command, acquiring the to-be-read data from the flash memory chip set and writing all data in a data storage block where the to-be-read data is located into the cache chip set;
and establishing a mapping relation according to the physical position of the data storage block and the physical position of the data to be read in the cache chipset, and writing the mapping relation into the mapping table.
5. The data processing method according to claim 4, wherein the cache chipset comprises a plurality of logical memory blocks, and the logical memory blocks have the same memory capacity as the data memory blocks;
the writing all the data in the data storage block where the data to be read is located into the cache chipset includes: writing all data in the data storage block where the data to be read is located into a logic storage block of the cache chip set;
the establishing a mapping relationship according to the physical location of the data storage block and the physical location of the data to be read in the cache chipset includes: and establishing a mapping relation according to the physical position of the data storage block and the physical position of the logic storage block and writing the mapping relation into the mapping table storage area.
6. The data processing method of claim 5, wherein the control chip has a block maintenance table stored therein, the block maintenance table including a status of each data storage block in the flash memory chipset; the method further comprises the following steps:
when the updated data in the cache chipset is written into the flash memory chipset, writing all the data of a logic storage block where the data to be written in the cache chipset is located into a free data storage block of the flash memory chipset according to a block maintenance table in the cache chipset, and updating the block maintenance table;
and erasing the data in the data storage block corresponding to the logic storage block according to the mapping relation in the mapping table storage area, and updating the block maintenance table.
7. The data processing method according to claim 6, wherein writing all data in the logic storage block in which the data to be written in the cache chipset is located into a free data storage block of the flash memory chipset comprises:
generating a plurality of data pages according to all data of a logic storage block where data to be written are located, wherein each data page comprises an ECC (error correction code) check code;
writing a plurality of the data pages into the same free data storage block of the flash memory chip set.
8. The data processing method according to claim 7, wherein the obtaining the data to be read from the flash memory chipset and writing all data in the data storage block where the data to be read is located into the cache chipset comprises:
retrieving the flash memory chip set to acquire the data to be read;
reading each data page from a data storage block where the data to be read is located, and checking each data page according to an ECC (error correction code) check code of each data page;
after the verification is passed, writing each data page into the flash memory chip set.
9. The data processing method of claim 5, further comprising the following steps performed by the control chip:
when a preset condition is reached, selecting a plurality of logic storage blocks which are hit by the read data command within a preset time from the cache chip set;
writing all data of the logic storage blocks with the least hit frequency into a plurality of idle data storage blocks of the flash memory chip set according to a block maintenance table in the cache chip set, and updating the block maintenance table;
and erasing the data in the data storage block corresponding to the logic storage block according to the mapping relation in the mapping table storage area, and updating the block maintenance table.
10. The data processing method according to claim 9, wherein the preset condition is: the cache chipset is full or reaches a preset time.
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