CN114647445A - Reverse engineering detection method on a processor and corresponding integrated circuit - Google Patents

Abstract

Embodiments of the present disclosure relate to a reverse engineering detection method on a processor and a corresponding integrated circuit. A method of detecting linear extraction of information in a processor using an instruction register for storing instructions includes operation code. The method includes monitoring instructions stored consecutively in an instruction register, including decoding an opcode, determining a number of consecutive opcodes encoding incremental branches, and generating a detection signal if the number is greater than or equal to a detection threshold.

Description

Reverse engineering detection method on a processor and corresponding integrated circuit

Cross Reference to Related Applications

This application claims priority to french application No. 2013625 filed on 18/12/2020, which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates generally to microelectronic devices and, in particular embodiments, to preventing reverse engineering.

Background

Reverse engineering can be used to study and potentially clone the behavior of microcontrollers. A microcontroller typically comprises at least one processor and a memory connected via a data bus. Reverse engineering on a microcontroller may include a "linear code fetch" type of technique in which a processor may be forced to execute an incremental branch instruction that requires the processor's address retrieval circuitry to sequentially read addresses in memory (i.e., traverse all addresses in memory one after the other).

Examples include a hardware analysis stage, using de-formatting and advanced microscopy techniques to identify hardware elements carrying secret information. The hardware analysis stage makes it possible to identify the logic that controls the Instruction Register (IR) of the processor.

The data extraction stage using a Focused Ion Beam (FIB) or fault implantation technique may include modifying the current instructions stored in the instruction register. The current instruction may be forced to include an operation code corresponding to an increment branch whose addressing mode includes an increment of the address currently being read in the processor.

Thus, the data fetch technique includes the step of applying an incremental branch instruction to force the processor to operate in a linear execution mode (i.e., an operating mode in which the processor reads from memory in address order).

The processor will read the entire memory contents sequentially and wherein the contents read by the processor are fetched using microsensor technology. For example, data may be fetched from a data bus via which each item of address is temporarily communicated from memory to an instruction register.

Based on the secret content extracted by reverse engineering, the software embedded in the microcontroller can be reconstructed and a cloned product can be produced.

Conventional solutions to prevent reverse engineering using a generic hardware protection layer or inter-operation (inter-operation) technique between two processors are known and alternatives have been developed to bypass them.

It would be advantageous to detect an attempt to fetch the source code contained in memory. Moreover, it would be beneficial to respond to such attempts. Furthermore, it would be helpful to complicate the design of possible variants by making detection and response solutions difficult to identify.

Disclosure of Invention

In an embodiment, the present disclosure presents a method of detecting linear extraction of information in a processor using an instruction register for storing instructions including an operation code. The method includes monitoring instructions stored consecutively in an instruction register including decoding an opcode, determining a number of consecutive opcodes encoding incremental branch instructions, and generating a detection signal if the number is greater than or equal to a detection threshold.

"monitoring instructions stored consecutively in an instruction register includes decoding an opcode" is understood to mean, for example, systematic and routine reading and decoding of the opcode of the instruction stored in the instruction register.

The monitoring advantageously does not affect the regular use of the instruction register as a store for the current instruction being processed in the processor.

An "incremental branch instruction" is understood to mean, for example, an instruction that, once it has been processed by a processor, automatically causes the next instruction stored at a memory address immediately consecutive to the memory address of the current instruction to be read.

However, the linear code fetch step of the reverse engineering method produces a number of incremental branch instructions that may be higher than normal (i.e., higher than the detection threshold chosen in this regard).

Thus, according to this aspect, instructions stored continuously in the instruction register are monitored and detection signals are generated, allowing detection and reporting of the reverse engineering method, in particular the linear code extraction step, being performed on the processor.

Also, the current instruction is conventionally stored in an instruction register located inside the processor.

Thus, the method according to this aspect may be implemented by direct integration into a processor, which makes identification challenging in reverse engineering. This adds complexity to the reverse engineering process and tends to make this type of process unprofitable as a whole.

In an embodiment, determining the number of consecutive operation codes encoding the incremental branch comprises comparing the decoded operation code to a list of operation codes encoding the skip branch.

For example, an exhaustive list of operation codes encoding skip branches may be provided to the processor. However, providing an exhaustive list of opcodes for the incremental branch instruction is not necessary, as the processor may be configured to default to the incremental branch instruction when no opcode is identified.

Thus, by comparing the decoded operation code to the list of operation codes encoding skipped branches, it can be determined whether the operation code corresponds to an incremental branch instruction, and thus the continuity of a series of incremental branches is monitored to detect linear code fetches.

A "skip branch instruction" is understood to mean a branch instruction that is not an incremental branch, such as a jump, call, or return instruction.

Thus, the list of operation codes may include: encoding an operation code of a jump instruction, and calling the operation code of the instruction in an encoding process; and an operation code encoding a procedure return instruction.

This corresponds to a list that may be exhaustive or non-exhaustive, depending on the language of the code of the processor, including encoding the main operation code of the skip branch.

In an embodiment, determining the number of consecutive operation codes encoding the incremental branch further comprises: decrementing a value of a counter previously set to a detection threshold when an operation code encoding an increment branch instruction in the operation code is decoded; resetting the value of the counter to a detection threshold when the operation code in the decoded operation codes includes an operation code of an encoding skip branch; the detection signal is generated when the value of the counter is zero.

By design, it is more robust to use decrementing than incrementing in the event that the register containing the detection threshold is forced back to its starting point in an attempt to bypass the detection method.

More specifically, the down counter is set to the value of a threshold that is a priori unknown by the person performing the reverse engineering; instead, the incremental counter is set a priori to a value of zero.

As a result, the reverse engineering process will require additional work to identify the starting point of the counter, which increases the complexity of the implementation process with the aim of making it unprofitable as a whole.

In an embodiment, the value of the detection threshold is selected in conjunction with an implementation of the source code to allow for execution of successive incremental branch instructions during normal execution of the source code by the processor.

Thus, the joint selection of the detection threshold and the implementation of the source code achieves a good compromise between the desired security level and the execution performance of the source code. By jointly providing the implementation of the source code and the value of the detection threshold, any detection signal may be prevented from being generated during normal operation of the processor.

In an embodiment, the source code must comply with the threshold. If normal execution of the source code triggers a detection signal, a skip branch instruction may be introduced into the source code to interrupt its linearity.

Since the selection of the detection threshold limits the number of instructions that can be fetched in the reverse engineering process, the detection threshold should advantageously be minimized, potentially by adapting the implementation of the source code in this regard.

In an embodiment, the present disclosure proposes a method for preventing linear extraction of information, the method comprising the detection method defined above and comprising the step of forcing the memory address of the next read operation of the processor to point to a memory location whose content is non-secret in response to the generation of the detection signal.

For example, the steps include resetting the instruction pointer to the value of the instruction pointer taken prior to generating the detection signal or command to access the memory location whose original content was not secret.

"non-confidential original content" is understood to mean, for example, information originally intended for transmission to a third party.

Thus, forcing the processor to read the non-secret content after generating the detection signal ensures that the information extracted during the linear information extraction attempt is not available within the scope of the reverse engineering method.

Moreover, forcing the processor to continue reading memory during the attempt makes the detection method difficult to identify, as the processor continues to operate a priori in a linear information extraction mode that does not reflect the reverse engineered detection.

The alternative of resetting the instruction pointer (a term for a pointer to the address of the current instruction well known to those skilled in the art) alternatively to a previous value makes it possible to force the processor to read only the contents in the memory that have been read during the linear extraction (i.e. before the detection signal was generated).

In an embodiment, the present disclosure presents a detection integrated circuit including a processor. The processor includes an instruction register for storing instructions having an operation code. The detection integrated circuit includes: a monitoring circuit configured to monitor instructions stored consecutively in the instruction register and decode an operation code of the instructions; a counter circuit configured to determine a number of consecutive operation codes encoding the increment branch; and a generator circuit configured to generate the detection signal if the number is greater than or equal to the detection threshold.

In an embodiment, the counter circuit is configured to compare the operation code decoded by the monitoring circuit with the list of operation codes of the encoding skip branches.

In an embodiment, the opcode list includes an opcode encoding a jump instruction, an opcode encoding a procedure call instruction, and an opcode encoding a procedure return instruction.

In an embodiment, the counter circuit is configured to decrement a value of the counter when the operation code encoding the increment branch instruction among the decoded operation codes, the value of the counter being intended to be previously set as the detection threshold, and to reset the value of the counter as the detection threshold when the operation code encoding the skip branch is included among the decoded operation codes, and wherein the generator circuit is configured to generate the detection signal when the value of the counter is zero.

In an embodiment, the selection of the value of the detection threshold and the implementation of the source code are jointly adapted to allow successive incremental branch instructions to be executed by the processor during normal execution of the source code.

In an embodiment, the integrated circuit as defined above further comprises a response circuit configured to force, in response to transmission of the detection signal, a memory address of a next read operation of the processor to point to a location of the memory whose content is non-secret.

In an embodiment, the response circuit is configured such that it resets the instruction pointer to the value of the instruction pointer taken prior to generating the detection signal or command to access the memory location whose original content is non-secret.

In an embodiment, the detector circuit and the response circuit include logic circuits located in a glue logic type logic circuit area of the processor.

Drawings

Other advantages and features of the present disclosure will become apparent upon review of the detailed description of implementations and embodiments which are in no way limiting and the accompanying drawings, in which:

FIG. 1 is a diagram of an embodiment of a microcontroller;

FIG. 2 is a diagram of an address fetch circuit, instruction pointer register and detector circuit of the microcontroller of FIG. 1; and

FIG. 3 is a flow chart of an embodiment method.

Detailed Description

Fig. 1 illustrates a block diagram of an embodiment microcontroller (PE) during a "linear code extraction" (LCE) type reverse engineering attempt. The microcontroller (PE) shown comprises a processor (CPU) connected via a data bus (B) to at least one memory MEM1, MEMn. For simplicity, at least one of the memory designated memories MEM1, …, MEMn should be used.

The processor (CPU) includes a controller Circuit (CU) and a circuit (IDEX) for decoding and executing instructions. In an embodiment, the controller Circuit (CU) comprises an address fetch circuit (FA), an Instruction Register (IR) and an instruction pointer register (PC) containing the memory address of the instruction being executed.

During a normal operating cycle of a processor (CPU), an Instruction Register (IR) contains the current instruction containing an operation code, which is well known by the technical term "opcode". The Instruction Register (IR) is coupled to the circuit (IDEX).

The operation code is a portion of machine language instructions that specify operations to be performed by the processor. In addition to the operation code, most instructions specify data to be processed, called operands.

The operation code of the current instruction is decoded by the decode circuitry to determine which operation to implement. The decode circuitry is coupled to address fetch circuitry (FA) which calculates the address of the next instruction to be read from the operation code of the current instruction. The cycle restarts with the next instruction replacing the current instruction in the Instruction Register (IR).

The linear code extraction attempt may include changing an operation cycle of a processor (CPU) through an attack Instruction Register (IR). A linear code fetch attempt may include a step in which an Instruction Register (IR) is forced to store corrupted instructions.

Corrupted instructions include, for example, "hacking" operation code (i.e., operation code that is imposed during a reverse engineering process) that allows for linear code fetching (i.e., operation code configured to encode an incremental branch instruction).

An "incremental branch instruction" is understood as a current instruction that, once processed by the processor, automatically causes the next instruction stored at a memory address immediately consecutive to the memory address of the current instruction to be read. The increment branch instruction uses an addressing mode in which the next address read by the processor is defined relative to the address being read, e.g., specifying the number by which the address being read must be incremented.

The multiple incremental branch instructions executed in a row are referred to as a linear read of memory by the CPU.

An increment branch instruction is in contrast to a skip branch instruction, which causes a skip to a memory address unrelated to the current address or the last address read by the processor (CPU).

Jump branch instructions are, for example, instructions in assembly language, such as jump instructions, procedure call instructions, and post-procedure return instructions.

An exhaustive list of operation codes encoding skip branches may be provided to a processor (CPU). In contrast, an exhaustive list of operation codes encoding the incremental branches is typically not provided.

More specifically, when the operation code does not belong to the operation code list of the encoding skip branch, the processor (CPU) is configured to read by default the next instruction stored at a memory address directly consecutive to the memory address of the current instruction.

Thus, the hacker operating the code aims to put the processor (CPU) in a default operating mode, so that the processor (CPU) reads all addresses of the memories MEM1, …, MEMn in sequence.

Indeed, a linear code extraction attempt may include the first implementation a1, imposing a hacking operation code using, for example, a Focused Ion Beam (FIB) on an Instruction Register (IR).

Alternatively, implementation a1 may include an error injection technique that forces an Instruction Register (IR) to force hacker operation codes. This fault injection technique is provided for physically modifying the circuit (e.g., by adding/removing connections) to force hacking operation code in the Instruction Register (IR).

Moreover, the attempting may also include using the second implementation a2 for extracting the logical value from the memory. The second implementation a2 uses micro sensors arranged on a channel on which data flows from the memory to the Instruction Register (IR), for example directly on a data bus (B) coupling the Instruction Register (IR) to the memory. Thus, it is conventionally possible to read source code that is linearly fetched from memory and temporarily stored in an Instruction Register (IR).

Fig. 2 illustrates a block diagram of an embodiment of the address circuit (FA), the Instruction Register (IR), the circuit (IDEX), and the detector circuit (DIR) for detecting corruption of the Instruction Register (IR) of the Microcontroller (MC) described with reference to fig. 1.

In an embodiment, the detector circuit (DIR) is configured to report attempted Linear Code Extraction (LCE), as described with reference to fig. 1. During a linear code fetch attempt, the first implementation a1 forces a corrupted instruction containing hacked operation code into an Instruction Register (IR). As a result of this corruption, the decoder separates the hacked operation code and operands. The hacking code is transmitted to a selector of a Multiplexer (MUX) that generates an output address of the address fetch circuit (FA) according to the hacking code. The hacker operation code forces the multiplexer to select the address of the instruction that directly follows the address of the current instruction.

For example, the multiplexer selects an address whose value is equal to the address of the current instruction (AD) plus the size Cst of the current instruction (i.e., the number of memory addresses occupied by the current instruction).

The address of the next instruction is forced to be linearly related to the address of the current instruction, other instruction addresses AD1, …, ADn could also theoretically be selected and output from a Multiplexer (MUX) at the expense of other instruction addresses AD1, …, ADn. Forcing the hacker to manipulate the code into the Instruction Register (IR) results in a linear read of the code from the memory.

To implement the detection of the linear code extraction attempt, the detector circuit (DIR) comprises a monitoring circuit configured to monitor the instructions stored consecutively in the Instruction Register (IR) and to decode the operation codes of the instructions. For example, the monitoring circuit is integrated into a portion of a decode circuit that receives an instruction and decodes an operation code (IDEX) in the circuit.

Furthermore, the detector circuit (DIR) further comprises a counter circuit configured to determine a number of consecutive operation codes encoding the incremental branch. To this end, the counter circuit may, for example, comprise a counter whose current value represents the number of consecutive increasing branch instructions.

For example, when the value of the counter indicates a number of consecutive incremented branch instructions that is greater than or equal to a detection threshold, a linear fetch attempt is detected, and a detection signal is generated as a result.

In an embodiment, the detector circuit (DIR) comprises a generator circuit configured to output a detection signal if the number of consecutive incremental branch instructions is greater than or equal to a detection threshold.

Further, the value of the detection threshold may be selected in connection with a particular implementation of the source code contained in the memory. In an embodiment, the selection of the value of the detection threshold and the implementation of the source code are configured to allow a "normal" number of consecutively executed incremental branch instructions without triggering the detection signal.

In an embodiment, normal operation of the microcontroller uses a normal number of incremental branch instructions that do not trigger a detection signal. Normal operation of a microcontroller is understood to mean its designed operation, for example as specified in the manufacturer's user manual (often referred to as a data sheet).

To minimize the value of the threshold, a skip branch instruction may be introduced during implementation of the source code to adapt the selected detection threshold, thereby reducing the normal number of incremental branch instructions present in a line in the code.

The constant amount of normally incremented numbers can be obtained by simulating the execution of the source code by the processor (CPU) or automatically upon reading the source code.

Furthermore, a response to the detection of the linear source code extraction attempt is advantageously provided to protect the contents of the memory that have not been read during the linear code extraction attempt.

For example, a response circuit included in a detector circuit (DIR) is configured to force a processor (CPU) to read a memory address that includes non-secret content.

"non-confidential content" is understood to mean information intended to be sent to a third party, which does not provide information that can be used within the scope of the reverse engineering method. The response circuit may, for example, have a control terminal of a direct access Multiplexer (MUX) and be configured to force the address ADn of the next instruction computed by the fetch address circuit (FA).

Also, the detector circuit (DIR) and the response circuit may be integrated and "hidden" within the processor (CPU), for example.

In an embodiment, the detector circuit and the response circuit are advantageously in a "glue logic" type area. More specifically, techniques for hiding logic circuits in such areas are known.

Thus, one particular advantage of integrating the detector circuit (DIR) between elements of a bonded logic-type region is that it makes the detector circuit (DIR) difficult to destroy.

Fig. 3 illustrates a flow diagram of an embodiment method implemented by the detector circuit (DIR) described with reference to fig. 2. Step S1 includes monitoring instructions stored consecutively in the instruction register and decoding the operation code OpC for each stored new current instruction. The monitoring of the consecutively stored instructions and the decoding of the operation code OpC may be implemented, for example, by a decoding circuit of the processor.

Step S2 includes generating a comparison Comp between the decoded opcode OpC and the list of opcodes encoding the skip branch. The comparison Comp is used to determine whether the current instruction is an increment branch or a skip branch instruction.

For example, if the opcode of the current instruction belongs to the list of opcodes, the comparison Comp may change the comparison result to a logical value of 1. Otherwise, comparing Comp may change the comparison result to a logical value of 0. The operation code list may include, for example, operation codes corresponding to a jump instruction Jmp, a procedure call instruction Cll, or a procedure return instruction Rtn.

Step S3 comprises two different actions depending on the comparison result Comp of the previous step S2. On the one hand, if the opcode encoding of the current instruction increments the branch instruction (i.e. if the result of the comparison Comp is equal to 0), then step S3 includes decrementing the value of the counter Cnt previously set to the detection threshold Th.

Alternatively, the counter Cnt may be incremented to the value of the detection threshold Th, in which case the value of the counter Cnt is previously set to zero.

On the other hand, if, conversely, the opcode encoding of the current instruction skips the branch instruction (i.e. if the result of the comparison Comp is equal to 1), step S3 comprises resetting the value of the counter to the detection threshold Th.

Step S4 includes reading the value of the counter Cnt. If the value of the counter Cnt is comprised between 0 and the detection threshold Th, the method returns to step S1 and waits for the next instruction to be stored in the Instruction Register (IR).

If the counter is decremented, when the value of the counter Cnt is equal to zero, then step S4 includes generating a detection signal LCEdetec, where the value of the detection signal LCEdetec changes, for example, from a logical value 0 to a logical value 1.

Alternatively, if the counter is incremented, the detection signal LCEdetec changes from a logical value 0 to a logical value 1 when the value of the counter Cnt is equal to the detection threshold Th.

In both cases, the counter Cnt is reset when the detection signal LCEdetec is generated.

Alternatively, the down-counting (or up-counting) of the counter Cnt may be implemented within a range of values included between two limits arbitrarily offset from the zero point.

More specifically, a non-zero offset value may be advantageously selected to offset both boundaries of the counter Cnt. This ensures that neither the start nor the end of the counter Cnt can be known in advance.

For example, the upper limit of the range may be selected such that it equals the detection threshold plus the offset value, and the lower limit of the range may be selected such that it equals the offset value. In this example, the counter is decremented from the upper limit to the lower limit, or incremented from the lower limit to the upper limit.

Also in this alternative embodiment, the detection signal LCEdetec may also be generated if the value of the counter Cnt is not comprised between a lower limit and an upper limit. Such a generation can be used to counter attempts to force the value of the counter Cnt beyond two limits.

This creates additional work that must be performed by the reverse engineering process and increases the complexity of the process, with the aim of making it unprofitable as a whole.

Although the present specification has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the disclosure as defined by the appended claims. Like elements in the various figures are denoted by like reference numerals. Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments described herein, as one of ordinary skill in the art will readily appreciate from the present disclosure that processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Accordingly, the specification and figures are to be regarded only as illustrative of the present disclosure as defined by the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the present disclosure.

Claims (20)

1. A method, comprising:

monitoring instructions stored continuously in an instruction pointer register of a processor, the monitoring including systematic and routine reading and decoding of an operation code of the instructions;

during the monitoring, determining a number of encoded consecutive operation codes corresponding to an incremental branch instruction;

generating a detection signal in response to determining that the number of consecutive operation codes is greater than or equal to a threshold; and

detecting a linear extraction of an information attack on the processor in response to the generation of the detection signal.

2. The method of claim 1, wherein determining the number of consecutive operation codes comprises: the decoded operation code is compared to a list including operation codes corresponding to skip branch instructions.

3. The method of claim 2, wherein the list comprising operation codes corresponding to skip branch instructions comprises: a jump instruction, an operation code of an encoding procedure call instruction, and an operation code of an encoding procedure return instruction.

4. The method of claim 1, wherein determining the number of consecutive operation codes comprises:

determining that a first decoded operation code corresponds to an encoding of an increment branch instruction during the monitoring;

responsive to determining that the first decoded opcode corresponds to the encoding of the incremental branch instruction, decrementing a value of a counter, the value of the counter initially set to the value of the threshold, the generating the detection signal responsive to determining that the number of consecutive opcodes is greater than or equal to the threshold comprises: generating the detection signal in response to the value of the counter being equal to zero;

during the monitoring of the instruction, determining that a second decoded operation code corresponds to an encoding of a skip branch instruction; and

in response to determining that the second decoded operation code corresponds to the encoding of the skip branch instruction, resetting the value of the counter to the threshold.

5. The method of claim 1, wherein a value of the threshold is selected in connection with an implementation of source code such that consecutive incremental branch instructions are executed during normal execution of the source code by the processor.

6. The method of claim 1, further comprising: forcing a memory address of a next read operation of the processor to be directed to a location of a memory having non-secret content in response to the generation of the detection signal.

7. The method of claim 6, further comprising: resetting a value of the instruction pointer register to a value of the instruction pointer register prior to the generation of the detection signal or prior to a command to access a memory location having the non-secret content.

8. An integrated circuit comprising a processor, the processor comprising:

an instruction pointer register configured to store instructions, one or more instructions including an operation code;

a detector circuit configured to monitor instructions stored consecutively in the instruction pointer register, the monitoring including systematic and routine reading and decoding of an operation code of the instruction;

a counter circuit configured to determine a number of encoded consecutive operation codes corresponding to an incrementing branch instruction during the monitoring; and

a generator circuit configured to generate a detection signal in response to determining that the number of consecutive operation codes is greater than or equal to a threshold, wherein the processor is configured to detect a linear extraction of an information attack on the processor in response to the generation of the detection signal.

9. The integrated circuit of claim 8, wherein determining, by the counter circuit, the number of consecutive operation codes comprises: the decoded operation code is compared to a list including operation codes corresponding to skip branch instructions.

10. The integrated circuit of claim 9, wherein the list comprising operation codes corresponding to skip branch instructions comprises: a jump instruction, an operation code of an encoding procedure call instruction, and an operation code of an encoding procedure return instruction.

11. The integrated circuit of claim 8, wherein determining the number of consecutive operation codes comprises:

determining that a first decoded operation code corresponds to an encoding of an increment branch instruction during the monitoring;

responsive to determining that the first decoded opcode corresponds to the encoding of the incremental branch instruction, decrementing a value of a counter, the value of the counter initially set to the value of the threshold, the generating the detection signal responsive to determining that the number of consecutive opcodes is greater than or equal to the threshold comprises: generating the detection signal in response to the value of the counter being equal to zero;

during the monitoring of the instruction, determining that a second decoded operation code corresponds to an encoding of a skip branch instruction; and

in response to determining that the second decoded operation code corresponds to the encoding of the skip branch instruction, resetting the value of the counter to the threshold.

12. The integrated circuit of claim 8, wherein a value of the threshold is selected in conjunction with an implementation of source code such that consecutive incremental branch instructions are executed during normal execution of the source code by the processor.

13. The integrated circuit of claim 12, wherein the processor further comprises a response circuit configured to: forcing a memory address of a next read operation of the processor to be directed to a location of a memory having non-secret content in response to the generation of the detection signal.

14. The integrated circuit of claim 13, wherein the response circuit is further configured to: resetting a value of the instruction pointer register to a value of the instruction pointer register prior to the generation of the detection signal or prior to a command to access a memory location having the non-secret content.

15. The integrated circuit of claim 13, wherein the detector circuit and the response circuit comprise logic circuits located in a glue logic type logic circuit area of the processor.

16. A processor, comprising:

an instruction pointer register configured to store instructions, one or more instructions including an operation code;

a detector circuit configured to monitor instructions stored consecutively in the instruction pointer register, the monitoring including systematic and routine reading and decoding of an operation code of the instruction;

a counter circuit configured to determine a number of encoded consecutive operation codes corresponding to an incrementing branch instruction during the monitoring; and

a generator circuit configured to generate a detection signal in response to determining that the number of consecutive operation codes is greater than or equal to a threshold, wherein the processor is configured to monitor a linear extraction of information attacks on the processor in response to the generation of the detection signal.

17. The processor of claim 16, wherein determining, by the counter circuit, the number of consecutive operation codes comprises: the decoded operation code is compared to a list including operation codes corresponding to skip branch instructions.

18. The processor of claim 17, wherein the list comprising operation codes corresponding to skip branch instructions comprises: a jump instruction, an operation code of an encoding procedure call instruction, and an operation code of an encoding procedure return instruction.

19. The processor of claim 16, wherein determining the number of consecutive operation codes comprises:

determining that a first decoded operation code corresponds to an encoding of an increment branch instruction during the monitoring;

responsive to determining that the first decoded opcode corresponds to the encoding of the incremental branch instruction, decrementing a value of a counter, the value of the counter initially set to the value of the threshold, the generating the detection signal responsive to determining that the number of consecutive opcodes is greater than or equal to the threshold comprises: generating the detection signal in response to the value of the counter being equal to zero;

during the monitoring of the instruction, determining that a second decoded operation code corresponds to an encoding of a skip branch instruction; and

in response to determining that the second decoded operation code corresponds to the encoding of the skip branch instruction, resetting the value of the counter to the threshold.

20. The processor of claim 16, wherein a value of the threshold is selected in conjunction with an implementation of source code such that consecutive incremental branch instructions are executed during normal execution of the source code by the processor.

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