CN114646824A - Measuring circuit and method for device output high-resistance state - Google Patents

Abstract

The invention provides a measuring circuit and a method for outputting a high-resistance state by a device.A external test system is connected with the input end of a device to be tested in the measuring circuit through a GPIO port and is connected with the output end GPIO1 of the external test system, an enabling end is connected with a control end GPIO2 of the external test system, and the output end is connected with an acquisition end GPIO4 of the external test system; the input end of a testing device in the high-resistance testing loading circuit is connected with the output end GPIO3 of an external testing system, the enabling end is connected with the control end GPIO2 of the external testing system through an inverter, and the output end is connected with the acquisition end GPIO4 of the external testing system. The invention can carry out high resistance measurement by simple GPIO port acquisition, and can greatly improve the device testing efficiency.

Description

Measuring circuit and method for device output high-resistance state

Technical Field

The invention relates to the technical field of test circuits, in particular to a circuit and a method for measuring a device output high-resistance state.

Background

When the chip is subjected to function verification, part of devices have a high-impedance output state, when the output is high-impedance, the output state is neither high level nor low level but between the high level and the low level, the output state cannot be judged through simple logic state acquisition, the output state is judged to be in the high-impedance state by means of AD acquisition or an oscilloscope, and the like, but the number of the oscilloscope or the AD acquisition channels is often limited, and for some multi-bit bus driver devices, the problem that the acquisition channels are not enough exists, and the high-impedance state measurement of all the channels of the devices cannot be finished at one time.

Therefore, how to provide a measurement circuit capable of improving the efficiency of high-resistance state test of a device and a measurement method thereof is a problem that needs to be solved by those skilled in the art.

Disclosure of Invention

In view of this, the invention provides a circuit and a method for measuring a device output high-resistance state, which can perform high-resistance measurement by simple GPIO port acquisition, and can greatly improve the device test efficiency.

In order to achieve the purpose, the invention adopts the following technical scheme:

one aspect of the present invention provides a measurement circuit for outputting a high impedance state by a device, wherein an external test system is connected to the measurement circuit through a GPIO port, and the measurement circuit includes: the device under test testing circuit comprises a tested device testing circuit and a high-resistance testing loading circuit; wherein the content of the first and second substances,

the device under test circuit includes: a device under test; the input end of the tested device is connected with the output end GPIO1 of the external test system, the enabling end is connected with the control end GPIO2 of the external test system, and the output end is connected with the acquisition end GPIO4 of the external test system;

the high resistance test loading circuit includes: an inverter, a test device; the input end of the testing device is connected with the output end GPIO3 of the external testing system, the enabling end is connected with the control end GPIO2 of the external testing system through the phase inverter, and the output end is connected with the acquisition end GPIO4 of the external testing system.

Preferably, the device under test and the test device comprise unidirectional, bidirectional drivers/buffers.

Preferably, the output end of the test device is connected with the external test system acquisition end GPIO4 through a resistor. The resistor is used for controlling the connection and disconnection between the tested device testing circuit and the high-resistance testing loading circuit.

The invention provides a measuring method of a device output high impedance state measuring circuit based on the first aspect, which respectively controls the states of GPIO1, GPIO2 and GPIO3, compares the logic states of GPIO4, GPIO1 and GPIO2, and judges whether the output of a device to be tested is in a high impedance state, and comprises the following steps:

when the GPIO2 signal received by the enable end of the device under test is in a low level, the GPIO4 signal of the acquisition end of the external test system changes along with the change of the GPIO1 signal, and the device under test works normally;

when the GPIO2 signal received by the enable end of the device under test is in a high level, the GPIO4 signal of the acquisition end of the external test system changes along with the change of the GPIO3 signal, and the device under test is in a high impedance state regardless of the GPIO1 signal.

Through the technical scheme, compared with the prior art, the invention has the beneficial effects that:

the invention can make the test system finish the judgment of the high-resistance output state only by using the GPIO port through the circuit design, and has the characteristics of simple test method and capability of finishing the high-resistance test of all channels of the bus driver at one time. The method can measure 8-bit and 16-bit unidirectional and bidirectional buffers/drivers at one time, and can also test high resistance tests of a plurality of similar devices, thereby greatly improving the test efficiency.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts;

FIG. 1 is a schematic block diagram of a measurement circuit for outputting a high impedance state of a device according to an embodiment of the present invention;

fig. 2 is a logic circuit diagram of a measurement circuit for outputting a high impedance state by a device according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The embodiment of the invention provides a measuring circuit for a device output high-resistance state.

The device under test D2 test circuit includes: device under test D2; the input end of the device under test D2 is connected with the output end GPIO1 of the external test system, the enabling end is connected with the control end GPIO2 of the external test system, and the output end is connected with the acquisition end GPIO4 of the external test system.

The high resistance test loading circuit includes: inverter D1, test device D3; the input end of the testing device D3 is connected with the output end GPIO3 of the external testing system, the enabling end is connected with the control end GPIO2 of the external testing system through the inverter D1, and the output end is connected with the acquisition end GPIO4 of the external testing system;

the device under test D2 and the testing device D3 may be the same device or different devices;

in one embodiment, the device under test D2 and the test device D3 include unidirectional, bidirectional drivers/buffers.

In one embodiment, the output terminal of the testing device D3 is connected to the external testing system acquisition terminal GPIO4 through a resistor R1. When the output end of the tested device is in a non-high resistance state, the testing device outputs the high resistance state, due to the existence of the resistor, the GPIO4 of the acquisition end of the testing system and the testing device are equivalent to open circuit, and the state of the GPIO4 of the acquisition end of the testing system is determined by the testing circuit; when the tested device outputs high resistance, the output of the testing device is not high resistance, due to the existence of the resistor, the GPIO4 at the acquisition end of the testing system and the testing device are equivalently conducted, and the state of the GPIO4 at the acquisition end of the testing system is determined by a high resistance testing loading circuit.

The embodiments of the present invention will be further described with reference to specific working principles.

As shown in fig. 1 and 2, the device under test D2 has a high impedance output function, whose logic function is as follows: the high-impedance output is determined by the enable end \ OE of D2, when the GPIO2 signal received by \ OE is low level, the output GPIO4 of the device under test changes along with the change of GPIO1, and when the GPIO2 signal received by \ OE is high level, the output GPIO4 of the device under test is in high-impedance state.

According to the logic function of the tested device, when the input GPIO2 of the D2 enable terminal is at a low level, the output GPIO4 of the D2 changes along with the change of the GPIO1, at this time, because the input GPIO2 of the inverter D1 is at a low level, the output of the inverter is at a high level, the enable terminal of the testing device D3 inputs a high level, at this time, the output of the D3 is in a high impedance state, and therefore, when the D2 device normally works, the output of the high impedance test loading circuit is in a high impedance state, and the acquisition of the output GPIO4 of the D2 by the testing system is not influenced.

When the input GPIO2 of the D2 enabling end is in a high level, the output GPIO4 of the D2 is in a high impedance state, because the input end of the inverter D1 is in a high level, the output of the inverter is in a low level, the enabling end of the testing device is enabled, the output of the testing device is changed along with the change of the input loading control input GPIO3 of the testing system, the output is loaded to the GPIO4 after passing through the first resistor R1, because the output of the tested device D2 is in a high impedance state, at the moment, the GPIO4 is changed along with the change of the GPIO3 and is irrelevant to the state of the GPIO 1.

Therefore, when GPIO2 is low, the device under test D1 is operating normally, and its output GPIO4 is related to the test system input GPIO1 and not to GPIO 3; when the GPIO2 is at high level, the device under test D1 enters a high impedance state, and its output GPIO4 is related to the test system input GPIO3 and not to GPIO1, so the test system can determine whether the device under test output is at a high impedance state by controlling the states of GPIO1, GPIO2, and GPIO3, respectively, and comparing the logic states of GPIO4 with GPIO1 and GPIO 2.

The embodiment enables an external test system to finish high-impedance output state judgment only by using a GPIO port, and particularly relates to one-time test of bus driver devices. The method has the characteristics of simple test method and capability of completing high resistance test of all channels of the bus driver at one time.

The circuit and the method for measuring the output high-resistance state of the device provided by the invention are described in detail, a specific example is applied in the circuit to explain the principle and the implementation mode of the invention, and the description of the embodiment is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (4)

1. A measuring circuit for outputting a high-resistance state by a device, wherein an external test system is connected with the measuring circuit through a GPIO port, and the measuring circuit comprises: the device under test testing circuit comprises a tested device testing circuit and a high-resistance testing loading circuit; wherein the content of the first and second substances,

the device under test circuit includes: a device under test; the input end of the tested device is connected with the output end GPIO1 of the external test system, the enabling end is connected with the control end GPIO2 of the external test system, and the output end is connected with the acquisition end GPIO4 of the external test system;

the high resistance test loading circuit includes: an inverter, a test device; the input end of the test device is connected with the output end GPIO3 of the external test system, the enabling end is connected with the control end GPIO2 of the external test system through the inverter, and the output end is connected with the acquisition end GPIO4 of the external test system.

2. The device-out-of-high impedance state measurement circuit of claim 1, wherein the device under test and the test device comprise unidirectional, bidirectional buffer/drivers.

3. The device output high-impedance state measuring circuit according to claim 1, wherein the output end of the testing device is connected with an external testing system acquisition end GPIO4 through a resistor.

4. A method for measuring a measurement circuit of a device output high impedance state according to any one of claims 1-3, wherein the method comprises the following steps of respectively controlling the states of GPIO1, GPIO2 and GPIO3, comparing the logic states of GPIO4 with the logic states of GPIO1 and GPIO2, and judging whether the device output to be tested is in the high impedance state:

when the GPIO2 signal received by the enable end of the device under test is in a low level, the GPIO4 signal of the acquisition end of the external test system changes along with the change of the GPIO1 signal, and the device under test works normally;

when the GPIO2 signal received by the enable end of the device under test is in a high level, the GPIO4 signal of the acquisition end of the external test system changes along with the change of the GPIO3 signal, and the device under test is in a high impedance state regardless of the GPIO1 signal.

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