CN114639404A

CN114639404A - Charge cancellation circuit module, MRAM memory cell readout circuit, and memory system

Info

Publication number: CN114639404A
Application number: CN202210232804.9A
Authority: CN
Inventors: 叶乐; 薛畅; 张奕涵; 陈沛毓; 朱明伟; 武蒙; 黄如
Original assignee: Peking University; Huawei Technologies Co Ltd
Current assignee: Peking University; Huawei Technologies Co Ltd
Priority date: 2022-02-22
Filing date: 2022-03-11
Publication date: 2022-06-17

Abstract

The invention discloses a charge elimination circuit module, an MRAM memory cell reading circuit and a memory system. The reading circuit comprises a first bit line capacitor, a second bit line capacitor, a bit line charge eliminating module, a coupling amplifying module, a coupling charge eliminating module and a comparison latching module, wherein the bit line charge eliminating module can discharge two bit lines to be compared to the same low level or charge the two bit lines to the same high level, the coupling amplifying module can discharge two input ends of the coupling amplifying module to the same low level and can amplify signals of the input ends, and the coupling charge eliminating module can discharge two output ends of the coupling amplifying module to the same low level or charge the two output ends of the coupling amplifying module to the same high level, so that the charge difference on the two pre-charged node capacitors, the mismatch error of two branches connecting the two node capacitors and the influence of residual charges on the node capacitors after the last reading on the reading accuracy are prevented.

Description

Charge cancellation circuit module, MRAM memory cell readout circuit, and memory system

Technical Field

The invention relates to the technical field of MRAM (magnetic random Access memory) reading and writing, in particular to a charge elimination circuit module, an MRAM storage unit reading circuit and a storage system.

Background

The core structure of an MRAM Memory cell is a Magnetic Tunneling Junction (MTJ), which is formed by two Magnetic layers sandwiching an extremely thin non-Magnetic isolation layer, where the two Magnetic layers are a free layer and a fixed layer, respectively, and the fixed layer has a strong coercive force, so that the Magnetic moment is not changed, and the Magnetic moment of the free layer is switched under the influence of an external current. The MTJ has mainly two states, a high resistance state and a low resistance state, and when the magnetic moments of the free layer and the fixed layer are aligned, electrons easily pass through the two magnetic layers, and the MTJ shows the low resistance state, we consider the stored data to be '0'. When the magnetic moments of the free layer and the fixed layer are opposite, electrons are scattered between the two layers and are not easy to pass through the two magnetic layers, the MTJ shows a high resistance state, and the stored data is considered to be '1'.

The most basic operation for an MRAM memory cell is the writing and reading of data. The existing reading circuit is a charge type sensitive amplifier and comprises two node capacitors with the same size, one end of each node capacitor is respectively connected with a bit line of a unit to be read and a bit line of a reference unit, one bit line can control one node capacitor to release charges, the other end of each node capacitor is respectively connected with two input ends of a comparison circuit, a direct current path of the sensitive amplifier can be eliminated by arranging the node capacitors, and in addition, the data of the unit to be read can be read by comparing the voltage of the node capacitors.

Specifically, such a sense amplifier needs to precharge the two node capacitances and charge to the same voltage before accessing the bit line signal. And then, accessing a bit line signal, discharging the charges stored on the corresponding node capacitors through the two bit lines, generating a comparison result by the comparison circuit when the voltage difference between the two node capacitors is expanded to a certain degree, and accessing the comparison result into a latch to latch and output, thereby finishing the reading of the data of the unit to be read.

Although the sense amplifier can realize comparison latch under the condition of no direct current path and low reading voltage, the dependence degree on the charge quantity is too high, and the charge difference on two node capacitors after precharging, the mismatch error of two branches connecting the two node capacitors and the residual charge on the node capacitor after the last reading is finished can generate great influence on the next reading, thereby causing the error of the reading result.

Disclosure of Invention

The invention provides a charge eliminating circuit module, an MRAM memory cell reading circuit and a memory system, which are used for overcoming the technical problems in the prior art and improving the accuracy of the reading result of the MRAM memory cell.

The invention provides a charge elimination circuit module, which is used for eliminating the voltage difference between a first end and a second end of the circuit module, and comprises: a charge-return-to-zero cell and a charge-averaging cell,

the charge zeroing unit consists of three MOS transistors and is used for pulling the voltages of the first end and the second end to the same low level when three grids controlled by a discharge signal are opened;

the charge averaging unit is composed of three transfer gates for raising the voltages of the first terminal and the second terminal to the same high level when a transfer gate control signal is enabled.

The present invention also provides a MRAM memory cell readout circuit, comprising: the device comprises a first bit line capacitor, a second bit line capacitor, a bit line charge elimination module, a coupling amplification module, a coupling charge elimination module and a comparison latch module; the bit line charge eliminating module and the coupling charge eliminating module comprise the charge eliminating circuit module; the first end of the bit line charge elimination module is connected with a bit line of a unit to be read and the anode of a first bit line capacitor so as to acquire a bit line signal to be read from the bit line of the unit to be read, and the second end of the bit line charge elimination module is connected with a bit line of a reference unit and the anode of a second bit line capacitor so as to acquire a reference bit line signal from the bit line of the reference unit; the bit line charge elimination module comprises a first charge return-to-zero unit and a first pre-charge averaging unit, wherein the first charge return-to-zero unit is used for discharging the positive pole of the first bit line capacitor and the positive pole of the second bit line capacitor to the same low level; the first pre-charge averaging unit is used for charging the positive pole of the first bit line capacitor and the positive pole of the second bit line capacitor to the same high level; a first input end of the coupling amplification module is connected with a negative electrode of the first bit line capacitor, a second input end of the coupling amplification module is connected with a negative electrode of the second bit line capacitor, and the coupling amplification module is used for amplifying a difference value between a first signal of the bit line signal to be read after passing through the first bit line capacitor and a second signal of the reference bit line signal after passing through the second bit line capacitor so as to generate a third signal and a fourth signal; the first end of the coupled charge eliminating module and the first input end of the comparison latch module are connected with the first output end of the coupled amplifying module, the second end of the coupled charge eliminating module and the second input end of the comparison latch module are connected with the second output end of the coupled amplifying module, the coupled charge eliminating module comprises a second charge return-to-zero unit and a second pre-charge averaging unit, and the second charge return-to-zero unit is used for discharging the first output end and the second output end of the coupled amplifying module to the same low level; the second pre-charge averaging unit is used for charging the first output end and the second output end of the coupling amplification module to the same high level; the comparison latch module is configured to compare the third signal obtained from the first output terminal of the coupling amplifier module with the fourth signal obtained from the second output terminal of the coupling amplifier module, and then generate and latch a comparison result positive signal and a comparison result negative signal, where the first output terminal of the comparison latch module is configured to output the comparison result positive signal, and the second output terminal of the comparison latch module is configured to output the comparison result negative signal.

Further, the bit line charge cancellation module includes: a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor constituting the first charge zeroing unit, and a first transmission gate, a second transmission gate, and a third transmission gate constituting the first pre-charge averaging unit; the drain electrode of the first NMOS transistor, the output end of the second transmission gate, the drain electrode of the third NMOS transistor and the input end of the first transmission gate are connected with the first end of the bit line charge elimination module; the output end of the first transmission gate, the output end of the third transmission gate, the source electrode of the third NMOS transistor and the drain electrode of the second NMOS transistor are connected with the second end of the bit line charge elimination module; the source electrodes of the first NMOS transistor and the second NMOS transistor are grounded; the input ends of the second transmission gate and the third transmission gate are connected with a bit line precharge voltage; positive control ends of the first transmission gate, the second transmission gate and the third transmission gate are connected with a pre-charging control signal, and negative control ends of the first transmission gate, the second transmission gate and the third transmission gate are connected with a reverse signal of the pre-charging control signal; and the grids of the first NMOS transistor, the second NMOS transistor and the third NMOS transistor are connected with a charge return-to-zero signal.

Further, the coupling amplifying module includes a coupling charge zeroing unit for discharging a cathode of the first bit line capacitor and a cathode of the second bit line capacitor to a same low level.

Optionally, the coupled charge zeroing unit includes: a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; the drain electrode of the fourth NMOS transistor and the drain electrode of the sixth NMOS transistor are connected with the first input end of the coupling amplification module; the source electrode of the sixth NMOS transistor and the drain electrode of the fifth NMOS transistor are connected with the second input end of the coupling amplification module; the sources of the fourth NMOS transistor and the fifth NMOS transistor are grounded.

Further, the coupling amplifying module further comprises a seventh NMOS transistor, an eighth NMOS transistor, a first node capacitor, and a second node capacitor; the source electrode of the seventh NMOS transistor is connected with the first input end of the coupling amplification module, and the source electrode of the eighth NMOS transistor is connected with the second input end of the coupling amplification module; the grid electrode of the seventh NMOS transistor, the drain electrode of the eighth NMOS transistor, the positive electrode of the second node capacitor and the second output end of the coupling amplification module are connected; the grid electrode of the eighth NMOS transistor, the drain electrode of the seventh NMOS transistor, the positive electrode of the first node capacitor and the first output end of the coupling amplification module are connected; the negative electrodes of the first node capacitor and the second node capacitor are grounded.

Optionally, the coupling charge elimination module comprises: a ninth NMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor constituting the second charge zeroing unit, and a fourth transfer gate, a fifth transfer gate, and a sixth transfer gate constituting the second pre-charge averaging unit; the drain of the ninth NMOS transistor, the output end of the fifth transmission gate, the drain of the eleventh NMOS transistor and the input end of the fourth transmission gate are connected with the first end of the coupled charge elimination module; the output end of the fourth transmission gate, the output end of the sixth transmission gate, the source electrode of the eleventh NMOS transistor and the drain electrode of the tenth NMOS transistor are connected with the second end of the coupled charge eliminating module; the sources of the ninth NMOS transistor and the tenth NMOS transistor are grounded; the input ends of the fifth transmission gate and the sixth transmission gate are coupled with a precharge voltage; positive control ends of the fourth transmission gate, the fifth transmission gate and the sixth transmission gate are connected with a pre-charging control signal, and negative control ends of the fourth transmission gate, the fifth transmission gate and the sixth transmission gate are connected with a reverse signal of the pre-charging control signal; and the gates of the ninth NMOS transistor, the tenth NMOS transistor and the eleventh NMOS transistor are connected with a charge return-to-zero signal.

Optionally, the comparison latch module includes: the comparator comprises a comparison latch unit, a positive output buffer unit and a negative output buffer unit; the first input end of the comparison latch unit is connected with the first input end of the comparison latch module, the second input end of the comparison latch unit is connected with the second input end of the comparison latch module, and the comparison latch unit is used for comparing the third signal acquired from the first output end of the coupling amplification module with the fourth signal acquired from the second output end of the coupling amplification module to generate a fifth signal and an inverted signal of the fifth signal; the input end of the positive output buffer unit is connected with the first output end of the comparison latch unit and is used for outputting a comparison result positive signal from the output end of the positive output buffer unit after the fifth signal is buffered; the input end of the negative output buffer unit is connected with the second output end of the comparison latch unit and used for outputting a comparison result negative signal from the output end of the negative output buffer unit after the inverted signal of the fifth signal is buffered.

Further, the comparison latch unit includes: a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a twelfth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, and a seventeenth NMOS transistor; the gate of the fifteenth NMOS transistor is connected to the first input end of the comparison latch unit, and the gate of the seventeenth NMOS transistor is connected to the second input end of the comparison latch unit; the source electrode of the fifteenth NMOS transistor and the source electrode of the seventeenth NMOS transistor are connected with the drain electrode of the twelfth NMOS transistor; the source of the twelfth NMOS transistor is grounded; the drain of the fifteenth NMOS transistor is connected with the source of the fourteenth NMOS transistor, and the drain of the seventeenth NMOS transistor is connected with the source of the sixteenth NMOS transistor; the gate of the fourteenth NMOS transistor, the gate of the third PMOS transistor, the drain of the fourth PMOS transistor, the drain of the fifth PMOS transistor and the drain of the sixteenth NMOS transistor are connected to the second output terminal of the comparison latch unit; the gate of the sixteenth NMOS transistor, the gate of the fourth PMOS transistor, the drain of the third PMOS transistor, the drain of the second PMOS transistor, and the drain of the fourteenth NMOS transistor are connected to the first output terminal of the comparison latch unit; the sources of the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor and the fifth PMOS transistor are connected with a comparison latch voltage; and the gates of the second PMOS transistor, the fifth PMOS transistor and the twelfth NMOS transistor are connected with an output control signal.

Optionally, the positive output buffer unit includes: a first PMOS transistor and a thirteenth NMOS transistor; the grid electrodes of the first PMOS transistor and the thirteenth NMOS transistor are connected with the input end of the positive output buffer unit; the drains of the first PMOS transistor and the thirteenth NMOS transistor are connected with the output end of the positive output buffer unit; the source electrode of the first PMOS transistor is connected with the comparison latch voltage, and the source electrode of the thirteenth NMOS transistor is grounded.

Optionally, the negative output buffer unit includes: a sixth PMOS transistor and an eighteenth NMOS transistor; the grid electrodes of the sixth PMOS transistor and the eighteenth NMOS transistor are connected with the input end of the negative output buffer unit; the drains of the sixth PMOS transistor and the eighteenth NMOS transistor are connected with the output end of the negative output buffer unit; the source electrode of the sixth PMOS transistor is connected with the comparison latch voltage, and the source electrode of the eighteenth NMOS transistor is grounded.

The invention also provides an MRAM storage system, which comprises the MRAM storage unit reading circuit and an MRAM storage array consisting of a plurality of MRAM storage units.

In the circuit provided by the embodiment of the invention, the bit line charge eliminating module can charge the positive electrodes of the bit line capacitors respectively connected with the bit line of the cell to be read and the bit line of the reference cell to the same high level or discharge the positive electrodes to the same low level, meanwhile, the coupled charge zeroing unit connected with the cathodes of the two bit line capacitors can discharge the cathodes of the two bit line capacitors to the same low level, the same high level or low level enables the charge difference on the two bit line capacitors to be zero, mismatch errors of two branches connected with the two bit line capacitors cannot influence the charges on the bit line capacitors, residual charges after the last reading is finished are eliminated through discharging, and then the bit line signal to be read and the reference bit line signal form a first signal and a second signal through the bit line capacitor accurately, and the first signal and the second signal are respectively transmitted to the coupling amplification module for amplification processing to generate a third signal and a fourth signal.

And the first output end and the second output end of the coupling amplification module are connected with a coupling charge elimination module, two output ends of the coupling amplification module can be charged to the same high level or discharged to the same low level, similarly, the same high level or low level enables the charge error on the two output ends to be zero, the mismatch error of two branches connected with the two output ends cannot influence the charge on the output ends, the residual charge after the last reading is finished is eliminated through discharging, and then the amplified third signal and the amplified fourth signal are accurately transmitted to the comparison latch module without error, so that an accurate comparison result is generated and latched and output, and the accuracy of the reading result of the MRAM storage unit is finally improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a charge cancellation circuit module according to an embodiment of the present invention;

FIG. 2 is a block diagram of a MRAM memory cell readout circuit according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of a bit line charge cancellation module according to an embodiment of the present invention;

fig. 4 is a circuit diagram of a coupling amplifying module according to an embodiment of the present invention;

FIG. 5 is a circuit diagram of a coupling charge cancellation module according to an embodiment of the present invention;

FIG. 6 is a circuit diagram of a comparison latch module according to an embodiment of the present invention;

fig. 7 is a circuit diagram of the MRAM memory cell sensing circuit of fig. 3-6 connected together.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to make the technical solution of the present invention clearer, embodiments of the present invention are described in detail below with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a charge cancellation circuit module according to an embodiment of the present invention, where the circuit module of the embodiment shown in fig. 1 is used to cancel a voltage difference between two terminals, that is, a voltage difference between a first terminal 30 and a second terminal 40 of the circuit module is cancelled, and the circuit module of the embodiment includes: the charge-zero circuit comprises a charge-zero unit 10 and a charge-averaging unit 20, wherein the charge-zero unit 10 is composed of three MOS transistors and is used for pulling the voltages of a first end and a second end to the same low level when three gates controlled by a discharge signal are opened; the charge averaging unit 20 is composed of three transfer gates for raising the voltages of the first terminal and the second terminal to the same high level when the transfer gate control signal is enabled.

In this embodiment, all of the three MOS transistors constituting the charge zeroing unit 10 may be NMOS transistors, all of the three MOS transistors may be PMOS transistors, some of the three MOS transistors may be NMOS transistors, and some of the three MOS transistors may be PMOS transistors. In the example of fig. 1, all three MOS transistors are NMOS transistors, and the following embodiments are also described.

When the three MOS transistors of the charge zeroing unit 10 are all NMOS transistors, gates of the three NMOS transistors are connected to the same discharge signal DISCH, drains of the two NMOS transistors are correspondingly connected to the first terminal 30 and the second terminal 40, sources of the two NMOS transistors are all grounded, and a source and a drain of the other NMOS transistor are correspondingly connected to the first terminal and the second terminal. In this embodiment, by the charge zeroing unit, when the discharge signal DISCH is at a high level, the three NMOS transistors are all turned on, so that the voltages of the first terminal 30 and the second terminal 40 are pulled to the same low level and grounded, that is, the voltage difference between the two terminals is eliminated. When the transmission gate control signal of the charge averaging unit 20, even if the enable signals PRE and PRE _ P are asserted, the three transmission gates are all turned on, so that the voltages at the first terminal 30 and the second terminal 40 are all pulled up to VDD, and the voltage difference between the two terminals is eliminated. In practical application, the voltages of the first end and the second end can be maintained by the charges of the capacitors, so that the charge difference on the capacitors at the two ends can be eliminated by eliminating the voltage difference at the two ends, the refreshing of the reading circuit of the memory unit can be realized by eliminating the charge difference at the two ends, the influence of the residual charge after the previous reading on the reading is avoided, and meanwhile, the error generated when the circuits at the two ends are mismatched is also avoided, thereby being beneficial to improving the accuracy of the reading result.

FIG. 2 is a block diagram of a read circuit of an MRAM memory cell according to an embodiment of the present invention, and FIG. 3 is a circuit diagram of a bit line charge eliminating module according to an embodiment of the present invention; fig. 4 is a circuit diagram of a coupling amplifying module according to an embodiment of the present invention; FIG. 5 is a circuit diagram of a coupling charge cancellation module according to an embodiment of the present invention; FIG. 6 is a circuit diagram of a comparison latch module according to an embodiment of the present invention; fig. 7 is a circuit diagram of the MRAM memory cell sensing circuit of fig. 3-6 connected together. As shown in fig. 2-, the MRAM memory cell read-out circuit comprises: the circuit comprises a first bit line capacitor 11, a second bit line capacitor 12, a bit line charge elimination module 13, a coupling amplification module 14, a coupling charge elimination module 15 and a comparison latch module 16. The bit line charge cancellation module 13 and the coupled charge cancellation module 15 may adopt the charge cancellation circuit structure of the embodiment shown in fig. 1.

The first end 131 of the bit line charge cancellation module 13 is connected to the bit line 132 of the cell to be read and the positive pole of the first bit line capacitor 11 to obtain the bit line signal VBL from the bit line 132 of the cell to be read, and the second end 133 of the bit line charge cancellation module 13 is connected to the bit line 134 of the reference cell and the positive pole of the second bit line capacitor 12 to obtain the bit line signal VB from the bit line 134 of the reference cell.

The bit line charge elimination module 13 includes a first charge zero unit 135 and a first pre-charge averaging unit 136, the first charge zero unit 135 is used for discharging the positive pole of the first bit line capacitor 11 and the positive pole of the second bit line capacitor 12 to the same low level; the first pre-charge averaging unit 136 is used for charging the positive electrode of the first bit line 11 capacitor and the positive electrode of the second bit line capacitor 12 to the same high level.

The first input terminal 141 of the coupling amplifying module 14 is connected to the cathode of the first bit line capacitor 11, the second input terminal 142 of the coupling amplifying module 14 is connected to the cathode of the second bit line capacitor 12, and the coupling amplifying module is configured to amplify a difference between a first signal X1 of the bit line signal VBL to be read after passing through the first bit line capacitor 11 and a second signal X2 of the reference bit line signal VB after passing through the second bit line capacitor 12, so as to generate a third signal INBL and a fourth signal INB with a larger difference. The coupling amplifying block 14 includes a coupling charge zeroing unit 143 for discharging the cathode of the first bit line capacitor 11 and the cathode of the second bit line capacitor 12 to the same low level.

The first terminal 151 of the coupled charge cancellation block 15 and the first input terminal 161 of the comparison latch block 16 are connected to the first output terminal 144 of the coupled amplification block 14, and the second terminal 152 of the coupled charge cancellation block 15 and the second input terminal 162 of the comparison latch block 16 are connected to the second output terminal 145 of the coupled amplification block 14. The coupling charge eliminating module 15 includes a second charge zeroing unit 153 and a second pre-charge averaging unit 154, the second charge zeroing unit 153 is used for discharging the first output terminal 144 and the second output terminal 145 of the coupling amplifying module 14 to the same low level; the second pre-charge averaging unit 154 is used to charge the first output terminal 144 and the second output terminal 145 of the coupled amplifying module 14 to the same high level.

The comparison latch module 16 is configured to compare the third signal INBL obtained from the first output terminal 144 coupled to the amplifying module 14 with the fourth signal INB obtained from the second output terminal 145 coupled to the amplifying module 14, and then generate and latch a positive comparison result signal QB and a negative comparison result signal QBL, wherein the first output terminal 163 of the comparison latch module 16 is configured to output the positive comparison result signal QB, and the second output terminal 164 of the comparison latch module 16 is configured to output the negative comparison result signal QBL.

When the MRAM memory cell sensing circuit operates, the bit line 132 of the cell to be read and the bit line 134 of the reference cell to be compared pass through the bit line charge eliminating module 13 and are coupled to the coupling amplifying module 14 through the first bit line capacitor 11 and the second bit line capacitor 12. The bit line charge cancellation module 13 includes a first pre-charge averaging unit 136 and a first charge zeroing unit 135, the first pre-charge averaging unit 136 is used to ensure that the two bit lines maintain the same pre-charge voltage during pre-charging, and the first charge zeroing unit 135 is used to ensure that both bit lines are pulled to the same and sufficiently small voltage during discharging.

The coupling amplifying module 14 includes a coupling charge zeroing unit therein to ensure that the charge stored in the device of the coupling amplifying module 14 can be fully discharged to the ground when discharging. The voltage signals (the third signal INBL and the fourth signal INB) amplified by the coupling amplifying module 14 pass through the coupling charge eliminating module 15 and then are connected to the comparing latch module 16. The coupling charge eliminating module 15 is also divided into a second pre-charge averaging unit 154 and a second charge zeroing unit 153, the second pre-charge averaging unit 154 is used to ensure that the two output nodes of the coupling amplifying module 14 maintain the same pre-charge voltage during pre-charging, and the second charge zeroing unit 153 is used to ensure that the two output nodes of the coupling amplifying module 14 can be pulled to the same and sufficiently small voltage during discharging.

The comparison latch module 16 is mainly configured to receive two output voltage signals (the third signal INBL and the fourth signal INB) of the coupling amplification module 14, perform comparison, obtain a result, and latch the result. The result is divided into positive and negative two (comparison result positive signal QB and comparison result negative signal QBL) outputs.

In the MRAM memory cell readout circuit according to the embodiment of the present invention, the bit line charge eliminating module 13 may charge the positive electrodes of the bit line capacitors respectively connected to the bit line 132 and the reference bit line 134 of the cell to be read to the same high level or discharge the positive electrodes to the same low level, and at the same time, the coupling charge zeroing unit 143 connected to the negative electrodes of the two bit line capacitors may discharge the negative electrodes of the two bit line capacitors to the same low level, the same high level or low level may cause the charge difference between the two bit line capacitors to be zero, the mismatch error between the two branches connected to the two bit line capacitors may not affect the charge on the bit line capacitors, and the residual charge after the last reading is eliminated through the discharging, so that the bit line signal VBL to be read and the reference bit line signal VB accurately form the first signal X1 and the second signal X2 through the bit line capacitors, and are respectively transmitted to the coupling amplifying module for amplification, a third signal INBL and a fourth signal INB are generated.

Moreover, the first output end 144 and the second output end 145 of the coupling amplifying module 14 are connected to the coupling charge eliminating module 15, which can charge the two output ends of the coupling amplifying module 14 to the same high level or discharge to the same low level, and similarly, the same high level or low level makes the charge error on the two output ends zero, the mismatch error of the two branches connecting the two output ends will not affect the charge on the output ends, the residual charge after the last reading is also eliminated through discharging, and further the amplified third signal INBL and the fourth signal INB are accurately transmitted to the comparing latch module 16, so as to generate and latch and output an accurate comparison result, and finally improve the accuracy of the reading result of the MRAM memory cell.

In the MRAM memory cell readout circuit described above, the bit line charge cancellation module 13 has the charge cancellation circuit structure shown in fig. 1, and the bit line charge cancellation module 13 may specifically be, as shown in fig. 3, including: a first NMOS transistor N1, a second NMOS transistor N2, and a third NMOS transistor N3 constituting the first charge zeroing unit 135, and a first transfer gate T1, a second transfer gate T2, and a third transfer gate T3 constituting the first precharge charge averaging unit 136;

wherein, the drain of the first NMOS transistor N1, the output of the second transmission gate T2, the drain of the third NMOS transistor N3 and the input of the first transmission gate T1 are connected to the first end 131 of the bit line charge cancellation module 13; the output terminal of the first transmission gate T1, the output terminal of the third transmission gate T3, the source of the third NMOS transistor N3 and the drain of the second NMOS transistor N2 are connected to the second terminal 133 of the bit line charge cancellation module 13.

The sources of the first NMOS transistor N1 and the second NMOS transistor N2 are grounded GND; the input ends of the second transmission gate N2 and the third transmission gate T3 are connected with the bit line precharge voltage VBL _ RD; positive control terminals of the first transmission gate T1, the second transmission gate T2 and the third transmission gate T3 are connected with the PRE-charging control signal PRE, and negative control terminals of the first transmission gate T1, the second transmission gate T2 and the third transmission gate T3 are connected with the inverted signal PRE _ P of the PRE-charging control signal; the gates of the first NMOS transistor N1, the second NMOS transistor N2, and the third NMOS transistor N3 are connected to the charge return to zero signal DISCH.

When the bit line charge eliminating module 13 is in operation, the cell bit line 132 to be read and the reference cell bit line 134 are connected to the cell to be read and the reference cell, respectively. In the embodiment of the present application, the connection between the bit line and the MRAM cell is not limited by the name of the bit line, and if the data stored in the cell connected to the left bit line 132 to be read needs to be read, the reference cell is accessed to the right bit line 134. If it is desired to read the data stored by the cell connected to the right reference cell bitline 134, the reference cell accesses the left cell bitline 132 to be read.

The cell bit line 132 and the reference cell bit line 134 are also connected to the bit line charge elimination module 13, which is divided into a first pre-charge averaging unit 136 and a first charge return-to-zero unit 135. The "first" is for the purpose of descriptive distinction from the charge-zeroing unit and the pre-charge-averaging unit in the coupled charge-cancellation module 15 described below.

In the bit line charge elimination module 13, the first PRE-charge averaging unit 136 is composed of three CMOS transmission gates, which are respectively connected to two bit lines, the bit line 132 of the cell to be read and the bit line PRE-charge voltage VBL _ RD, the bit line 134 of the reference cell and the bit line PRE-charge voltage VBL _ RD, and controlled by the PRE-charge control signal PRE and its inverse signal PRE _ P, when PRE is high, the module is turned on and the bit line is PRE-charged to the preset voltage value. The first charge zeroing unit 135 is composed of three NMOS transistors, respectively turns on two bit lines, the bit line 132 of the cell to be read and the ground GND, the bit line 134 of the reference cell and the ground GND, and is controlled by a charge zeroing signal DISCH, which turns on the module and discharges when high.

The bit line 132 and the reference bit line 134 are also connected to one end of two bit line capacitors, which are used to store and discharge the charges of two accessed MRAM memory cells while blocking the dc paths of the two bit lines.

In the MRAM memory cell readout circuit, the coupling amplifying module 14 can be as shown in fig. 4, wherein the coupling zeroing unit 143 includes: a fourth NMOS transistor N4, a fifth NMOS transistor N5, and a sixth NMOS transistor N6; the drain of the fourth NMOS transistor N4 and the drain of the sixth NMOS transistor N6 are coupled to the first input 141 of the amplifying block 14; the source of the sixth NMOS transistor N6 and the drain of the fifth NMOS transistor N5 are coupled to the second input 142 of the amplifying block 14; the sources of the fourth NMOS transistor N4 and the fifth NMOS transistor N5 are grounded GND.

The coupling amplifying module 14 may further include a seventh NMOS transistor N7, an eighth NMOS transistor N8, a first node capacitor C1 and a second node capacitor C2, as shown in fig. 4.

The source of the seventh NMOS transistor N7 is coupled to the first input 141 of the amplifying block 14, and the source of the eighth NMOS transistor N8 is coupled to the second input 142 of the amplifying block 14; the gate of the seventh NMOS transistor N7, the drain of the eighth NMOS transistor N8, the anode of the second node capacitor C2 and the second output end 145 of the coupling amplification module 14 are connected; the gate of the eighth NMOS transistor N8, the drain of the seventh NMOS transistor N7, the anode of the first node capacitor C1, and the first output terminal 144 of the coupling amplification block 14 are connected. The cathodes of the first node capacitor C1 and the second node capacitor C2 are grounded GND.

In operation of the coupled amplifier module 14, the input terminals (the first input terminal 141 and the second input terminal 142) are connected to the negative terminal of the bit line capacitance, and also connected to the source terminals of the cross-coupled pair transistor 146 (the seventh NMOS transistor N7 and the eighth NMOS transistor N8). The input terminal is also connected to a coupled charge zeroing unit 143. The cell is composed of three NMOS transistors, and two input terminals of the coupling amplification module 14, the first input terminal 141, and the ground GND, the second input terminal, and the ground GND are respectively turned on, and controlled by a charge return-to-zero signal DISCH, which is high level to turn on the cell and perform discharge.

The gates of a pair of cross-coupled NMOS transistors in the coupled amplifier module 14 are connected to the drain of the other NMOS transistor, i.e. the output terminals (the first output terminal 144 and the second output terminal 145) of the coupled amplifier module 14, and the source terminals are connected to the first input terminal 141 and the second input terminal 142. In order to increase the ability of the coupling amplifying module 14 to store charge at the first output terminal 144 and the second output terminal 145, and to balance the speed of discharging the charge, the first output terminal 144 and the second output terminal 145 are respectively added with a node capacitor (a first node capacitor C1 and a second node capacitor C2).

In the MRAM memory cell readout circuit described above, the coupling charge elimination module 15 may also adopt a charge elimination circuit structure as shown in fig. 1, and the coupling charge elimination module 15 may specifically be as shown in fig. 5, and includes: the ninth NMOS transistor N9, the tenth NMOS transistor N10, and the eleventh NMOS transistor N11 constituting the second charge zeroing unit 153, and the fourth transfer gate T4, the fifth transfer gate T5, and the sixth transfer gate T6 constituting the second pre-charge averaging unit 154.

The drain of the ninth NMOS transistor N9, the output of the fifth transmission gate T5, the drain of the eleventh NMOS transistor N11, and the input of the fourth transmission gate T4 are connected to the first end 151 of the coupled charge cancellation module 15; the output terminal of the fourth transmission gate T4, the output terminal of the sixth transmission gate T6, the source of the eleventh NMOS transistor N11, and the drain of the tenth NMOS transistor N10 are connected to the second terminal 152 of the coupled charge cancellation module 15.

The sources of the ninth NMOS transistor N9 and the tenth NMOS transistor N10 are grounded GND; the input ends of the fifth transmission gate T5 and the sixth transmission gate T6 are coupled with the precharge voltage VDD 1; positive control terminals of the fourth transmission gate T4, the fifth transmission gate T5 and the sixth transmission gate T6 are connected with the precharge control signal PRE, and negative control terminals of the fourth transmission gate T4, the fifth transmission gate T5 and the sixth transmission gate T6 are connected with the inverted signal PRE _ P of the precharge control signal; the gates of the ninth NMOS transistor N9, the tenth NMOS transistor N10, and the eleventh NMOS transistor N11 are connected to the charge return to zero signal DISCH.

When the coupled charge cancellation module 15 is operated, the first output terminal 144 and the second output terminal 145 of the coupled amplifying module 14 are connected to the coupled charge cancellation module 15, which is divided into a second pre-charge averaging unit 154 and a second charge zeroing unit 153. In this module, the second PRE-charge averaging unit 154 is composed of three CMOS transmission gates, which respectively turn on the two outputs of the coupling amplifying module 14, the first output 144 and the coupling PRE-charge voltage VDD1 of the coupling amplifying module 14, the second output 145 and the coupling PRE-charge voltage VDD1 of the coupling amplifying module 14, and is controlled by the PRE-charge control signal PRE and its inverted signal PRE _ P, and turns on and PRE-charges the module when PRE is high.

The second charge zeroing unit 153 is composed of three NMOS transistors, and respectively turns on two output terminals of the coupling amplification module 14, the first output terminal 144 and the ground GND of the coupling amplification module 14, and the second output terminal 145 and the ground GND of the coupling amplification module 14, and is controlled by a charge zeroing signal DISCH, and turns on the module and discharges when DISCH is at a high level.

In the MRAM memory cell readout circuit, the comparison latch module 16 may include, as shown in fig. 6: a comparison latch unit 51, a positive output buffer unit 52, and a negative output buffer unit 53; the first input terminal 511 of the comparison latch unit 51 is connected to the first input terminal 161 of the comparison latch module 16, the second input terminal 512 of the comparison latch unit 51 is connected to the second input terminal 162 of the comparison latch module 16, and the comparison latch unit is configured to compare the third signal INBL obtained from the first output terminal 144 of the coupled amplifying module 14 with the fourth signal INB obtained from the second output terminal 145 of the coupled amplifying module 14, so as to generate a fifth signal Q1 and an inverted signal Q2 of the fifth signal.

The positive output buffer unit 52 has an input end 521 connected to the first output end 513 of the comparison latch unit 51, and is configured to output the comparison result positive signal QB from the output end of the positive output buffer unit 52, i.e., the first output end 163 of the comparison latch module 16, after buffering the fifth signal Q1.

The input 531 of the negative output buffer unit 53 is connected to the second output 514 of the comparing latch unit 51, and is configured to buffer the inverted signal Q2 of the fifth signal, and output a negative comparison result signal QBL from the output of the negative output buffer unit 53, i.e. the second output 164 of the comparing latch module 16.

The comparison latch unit 51 described above includes: a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a twelfth NMOS transistor N12, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, and a seventeenth NMOS transistor N17.

The gate of the fifteenth NMOS transistor N15 is connected to the first input terminal 511 of the comparison latch unit 51, and the gate of the seventeenth NMOS transistor N17 is connected to the second input terminal 512 of the comparison latch unit 51; the source of the fifteenth NMOS transistor N15 and the source of the seventeenth NMOS transistor N17 are connected to the drain of the twelfth NMOS transistor N12; the source of the twelfth NMOS transistor N12 is grounded GND.

The drain of the fifteenth NMOS transistor N15 is connected to the source of the fourteenth NMOS transistor N14, and the drain of the seventeenth NMOS transistor N17 is connected to the source of the sixteenth NMOS transistor N16; the gate of the fourteenth NMOS transistor N14, the gate of the third PMOS transistor P3, the drain of the fourth PMOS transistor P4, the drain of the fifth PMOS transistor P5, and the drain of the sixteenth NMOS transistor N16 are connected to the second output terminal 514 of the comparison latch unit 51; the gate of the sixteenth NMOS transistor N16, the gate of the fourth PMOS transistor P4, the drain of the third PMOS transistor P3, the drain of the second PMOS transistor P2, and the drain of the fourteenth NMOS transistor N14 are connected to the first output terminal 513 of the comparison latch unit 51.

The sources of the second PMOS transistor P2, the third PMOS transistor P3, the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are connected with the comparison latch voltage VDD 2; the gates of the second PMOS transistor P2, the fifth PMOS transistor P5, and the twelfth NMOS transistor N12 are connected to the output control signal SAEN.

The positive output buffer unit 52 described above includes: a first PMOS transistor P1 and a thirteenth NMOS transistor N13; the gates of the first PMOS transistor P1 and the thirteenth NMOS transistor N13 are connected to the input terminal 521 of the positive output buffer unit 52; the drains of the first PMOS transistor P1 and the thirteenth NMOS transistor N13 are connected to the output terminal of the positive output buffer unit 52, i.e., the first output terminal 163 of the comparison latch module 16; the source of the first PMOS transistor P1 is connected to the comparison latch voltage VDD2, and the source of the thirteenth NMOS transistor N13 is connected to GND.

The negative output buffer unit 53 described above includes: a sixth PMOS transistor P6 and an eighteenth NMOS transistor N18; the gates of the sixth PMOS transistor P6 and the eighteenth NMOS transistor N18 are connected to the input terminal 531 of the negative output buffer unit 53; the drains of the sixth PMOS transistor P6 and the eighteenth NMOS transistor N18 are connected to the output terminal of the negative output buffer unit 53, i.e., the second output terminal 164 of the comparison latch module 16; the source of the sixth PMOS transistor P6 is connected to the comparison latch voltage VDD2, and the source of the eighteenth NMOS transistor N18 is connected to the ground GND.

When the comparison latch module 16 is operated, the two output terminals of the coupling amplifier module 14 are connected to the comparison latch module 16, which includes a comparison latch unit 51 and positive and negative inverters serving as an output buffer unit. The main structure of the comparison latch unit 51 is a pair of pseudo differential transistors and a pair of complementarily connected inverters, and is controlled by an output control signal SAEN. When SAEN is high, the comparison latch unit 51 is turned on, performs comparison to obtain the fifth signal Q1 and the inverted signal Q2 thereof, and outputs final positive and negative comparison results (QB, QBL) through the left and right inverters.

Based on the MRAM memory cell reading circuit, the circuit can work in a discharging return-to-zero mode, a pre-charging mode, a coupling amplification mode and a comparison latch mode through circuit timing control, and the working modes are explained in detail below.

The main working process of the MRAM memory cell readout circuit provided by the embodiment of the present invention is as follows:

one, discharge return-to-zero mode

The charge zeroing signal DISCH is set to a high level, the precharge control signal PRE is set to a low level, the output control signal SAEN is set to a low level, the anodes and cathodes of the first bit line capacitor 11 and the second bit line capacitor are both grounded, and two output terminals (144 and 145) of the coupling amplifying circuit 14 are both grounded and are connected to the nodes of the left and right paths to ensure that the nodes are both at the same low level, so as to reduce the error between the left and right nodes as much as possible.

Second, precharge mode

The charge zeroing signal DISCH is set to a low level, the precharge control signal PRE is set to a high level, the output control signal SAEN is set to a low level, anodes of two bit line capacitors are connected to a bit line precharge voltage VBL _ RD, two output ends of the coupling amplification module 14 are connected to a coupling precharge voltage VDD1, and cathodes of the two bit line capacitors are not fixed to a voltage for storing threshold voltage mismatch of the left and right cross-coupled transistors (N4 and N5). Meanwhile, the left and right nodes are communicated, so that the error between the left and right nodes is reduced as much as possible.

Triple, coupled amplification mode

The charge zeroing signal DISCH is set to a low level, the precharge control signal PRE is set to a low level, and the output control signal SAEN is set to a low level, at this time, if the MRAM cell resistance of the cell bit line 132 to be read is smaller than the MRAM cell resistance of the reference cell bit line 134 to be read, the charge stored in the first bit line capacitor 11 is discharged faster, the voltage drop of the negative electrode of the first bit line capacitor 11 is faster, and the gate-source voltage difference of the seventh NMOS transistor N7 is larger, so that the seventh NMOS transistor N7 on the left side is turned on first, and the charge stored in the first output terminal 144 of the coupling amplification module 14 is discharged into the first bit line capacitor 11, thereby causing the voltage drop of the first output terminal 144, and finally obtaining a result that the voltage of the third signal INBL is smaller than the voltage of the fourth signal INB.

If the resistance of the MRAM cell connected to the bit line 132 to be read is greater than the resistance of the MRAM cell connected to the bit line 134, the charge stored in the second bit line capacitor 12 is discharged faster, the voltage of the negative electrode of the second bit line capacitor drops faster, and the voltage difference between the gate and the source of the eighth NMOS transistor N8 on the right side is greater, so that the eighth NMOS transistor N8 on the right side is turned on first, the charge stored in the second output terminal 145 of the coupling amplifier module 14 is discharged to the second bit line capacitor 12, which causes the voltage of the second output terminal 145 to drop, and finally, the result that the voltage of the fourth signal INB is less than the voltage of the third signal INBL is obtained.

Fourth, compare the latched mode

The charge zeroing signal DISCH is set to a low level, the precharge control signal PRE is set to a low level, the output control signal SAEN is set to a high level, the voltage information stored at the first output terminal 144 and the second output terminal 145 of the coupling amplifying module 14 is input to the comparing latch module 16 and the comparing latch unit 51 is turned on, and the comparison result is output through the inverter.

When the voltage of the third signal INBL is greater than the voltage of the fourth signal INB, the current on the left side of the pseudo differential pair of the comparison latch unit 51 is greater than the current on the right side, and the voltage drops more quickly, the output terminal of the left inverter for latching (i.e., the first output terminal 513 of the comparison latch unit 51) compares the latch result to a low level, and outputs a comparison result positive signal QB of a high level through the positive output buffer unit 52, where the comparison result negative signal QBL is a low level.

When the voltage of the third signal INBL is smaller than the voltage of the fourth signal INB, the current on the left side of the pseudo-differential pair of the comparison latch unit 51 is smaller than the current on the right side, the voltage drops more slowly, the output terminal of the left inverter for latching (i.e., the first output terminal 513 of the comparison latch unit 51) compares the latch result to the high level, and outputs the comparison result positive signal QB of the low level through the positive output buffer unit 52, where the comparison result negative signal QBL is the high level.

According to the above operation, the comparison result positive signal QB is high, which indicates that the resistance of the MRAM cell turned on by the left bit line 132 to be read is greater than the resistance of the MRAM cell turned on by the right bit line 134, and the comparison result positive signal QB is low, which indicates that the resistance of the MRAM cell turned on by the left bit line 132 to be read is less than the resistance of the MRAM cell turned on by the right bit line 134.

It should be noted that: the same voltage can be used for the coupling precharge voltage VDD1 and the comparison latch voltage VDD2 to reduce the circuit complexity and thus save the cost.

The control signal settings for each operation of the MRAM memory cell read circuit are shown in the following table.

Wherein, '0' indicates a low level and '1' indicates a high level.

The embodiment of the invention also provides an MRAM storage system, which comprises the MRAM storage unit reading circuit in the embodiment and an MRAM storage array consisting of a plurality of MRAM storage units. In the large-scale reading process of the MRAM memory array, the one sensing circuit can be connected to a plurality of MRAM memory cells for reading, namely, the sensing circuit of the plurality of memory cells can be refreshed at one time through the one sensing circuit. In the actual reading process, the refreshing charge can be eliminated every time of reading, so that the reading yield cannot be influenced even if the resistance value of the high-resistance state of the magnetic tunnel junction is greatly changed along with the temperature. The MRAM storage system in the embodiment of the invention can effectively eliminate the charge error between the left branch and the right branch caused by the voltage fluctuation and the device mismatch when the charge returns to zero and the voltage is precharged, thereby improving the yield of the read-out circuit and bearing the mismatch caused by the process angle change and the temperature fluctuation; the residual charges with different sizes in the node capacitance and the bit line capacitance of the circuit in the previous reading operation can be effectively eliminated, and the accuracy of continuous reading under various process angles and temperatures is further improved.

Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A charge cancellation circuit block for canceling a voltage difference between a first terminal and a second terminal of the circuit block, comprising: a charge-return-to-zero cell and a charge-averaging cell,

2. The circuit module of claim 1, wherein the three MOS transistors are all NMOS transistors, and gates of the three NMOS transistors are connected to a same discharge signal, wherein drains of two NMOS transistors are correspondingly connected to the first terminal and the second terminal, sources of the two NMOS transistors are grounded, and a source and a drain of the other NMOS transistor are correspondingly connected to the first terminal and the second terminal.

3. An MRAM memory cell readout circuit, comprising: the device comprises a first bit line capacitor, a second bit line capacitor, a bit line charge elimination module, a coupling amplification module, a coupling charge elimination module and a comparison latch module; the bit line charge cancellation module and the coupled charge cancellation module each comprise a charge cancellation circuit module as claimed in claim 1 or 2;

a first end of the bit line charge eliminating module is connected with a bit line of a unit to be read and the anode of the first bit line capacitor so as to acquire a bit line signal to be read from the bit line of the unit to be read, and a second end of the bit line charge eliminating module is connected with a bit line of a reference unit and the anode of the second bit line capacitor so as to acquire a reference bit line signal from the bit line of the reference unit; the bit line charge elimination module comprises a first charge return-to-zero unit and a first pre-charge averaging unit, wherein the first charge return-to-zero unit is used for discharging the positive pole of the first bit line capacitor and the positive pole of the second bit line capacitor to the same low level; the first pre-charge averaging unit is used for charging the positive pole of the first bit line capacitor and the positive pole of the second bit line capacitor to the same high level;

a first input end of the coupling amplification module is connected with a negative electrode of the first bit line capacitor, a second input end of the coupling amplification module is connected with a negative electrode of the second bit line capacitor, and the coupling amplification module is used for amplifying a difference value between a first signal of the bit line signal to be read after passing through the first bit line capacitor and a second signal of the reference bit line signal after passing through the second bit line capacitor so as to generate a third signal and a fourth signal;

the first end of the coupled charge eliminating module and the first input end of the comparison latch module are connected with the first output end of the coupled amplifying module, the second end of the coupled charge eliminating module and the second input end of the comparison latch module are connected with the second output end of the coupled amplifying module, the coupled charge eliminating module comprises a second charge return-to-zero unit and a second pre-charge averaging unit, and the second charge return-to-zero unit is used for discharging the first output end and the second output end of the coupled amplifying module to the same low level; the second pre-charge averaging unit is used for charging the first output end and the second output end of the coupling amplification module to the same high level;

the comparison latch module is configured to compare the third signal obtained from the first output terminal of the coupling amplifier module with the fourth signal obtained from the second output terminal of the coupling amplifier module, and then generate and latch a comparison result positive signal and a comparison result negative signal, where the first output terminal of the comparison latch module is configured to output the comparison result positive signal, and the second output terminal of the comparison latch module is configured to output the comparison result negative signal.

4. The MRAM memory cell readout circuit of claim 3, wherein the bit line charge cancellation module comprises: a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor constituting the first charge zeroing unit, and a first transmission gate, a second transmission gate, and a third transmission gate constituting the first pre-charge averaging unit;

the drain electrode of the first NMOS transistor, the output end of the second transmission gate, the drain electrode of the third NMOS transistor and the input end of the first transmission gate are connected with the first end of the bit line charge eliminating module; the output end of the first transmission gate, the output end of the third transmission gate, the source electrode of the third NMOS transistor and the drain electrode of the second NMOS transistor are connected with the second end of the bit line charge elimination module;

the source electrodes of the first NMOS transistor and the second NMOS transistor are grounded; the input ends of the second transmission gate and the third transmission gate are connected with a bit line precharge voltage;

positive control ends of the first transmission gate, the second transmission gate and the third transmission gate are connected with a pre-charging control signal, and negative control ends of the first transmission gate, the second transmission gate and the third transmission gate are connected with a reverse signal of the pre-charging control signal; and the grids of the first NMOS transistor, the second NMOS transistor and the third NMOS transistor are connected with a charge return-to-zero signal.

5. The MRAM memory cell readout circuit of claim 3 or 4, wherein the coupling amplification module comprises a coupling charge zeroing unit for discharging the negative pole of the first bit line capacitance and the negative pole of the second bit line capacitance to the same low level.

6. The MRAM memory cell readout circuit of claim 5, wherein the coupled charge return-to-zero cell comprises: a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; the drain electrode of the fourth NMOS transistor and the drain electrode of the sixth NMOS transistor are connected with the first input end of the coupling amplification module; the source electrode of the sixth NMOS transistor and the drain electrode of the fifth NMOS transistor are connected with the second input end of the coupling amplification module; the sources of the fourth NMOS transistor and the fifth NMOS transistor are grounded.

7. The MRAM memory cell readout circuit of claim 5, wherein the coupling amplification module further comprises a seventh NMOS transistor, an eighth NMOS transistor, a first node capacitance, and a second node capacitance;

the source electrode of the seventh NMOS transistor is connected with the first input end of the coupling amplification module, and the source electrode of the eighth NMOS transistor is connected with the second input end of the coupling amplification module; the grid electrode of the seventh NMOS transistor, the drain electrode of the eighth NMOS transistor, the positive electrode of the second node capacitor and the second output end of the coupling amplification module are connected; the grid electrode of the eighth NMOS transistor, the drain electrode of the seventh NMOS transistor, the positive electrode of the first node capacitor and the first output end of the coupling amplification module are connected;

the negative electrodes of the first node capacitor and the second node capacitor are grounded.

8. The MRAM memory cell readout circuit of claim 3, wherein the coupling charge cancellation module comprises: a ninth NMOS transistor, a tenth NMOS transistor, and an eleventh NMOS transistor constituting the second charge zeroing unit, and a fourth transfer gate, a fifth transfer gate, and a sixth transfer gate constituting the second pre-charge averaging unit;

the drain of the ninth NMOS transistor, the output end of the fifth transmission gate, the drain of the eleventh NMOS transistor and the input end of the fourth transmission gate are connected with the first end of the coupled charge elimination module; the output end of the fourth transmission gate, the output end of the sixth transmission gate, the source electrode of the eleventh NMOS transistor and the drain electrode of the tenth NMOS transistor are connected with the second end of the coupled charge eliminating module;

the sources of the ninth NMOS transistor and the tenth NMOS transistor are grounded; the input ends of the fifth transmission gate and the sixth transmission gate are coupled with a precharge voltage;

positive control ends of the fourth transmission gate, the fifth transmission gate and the sixth transmission gate are connected with a pre-charging control signal, and negative control ends of the fourth transmission gate, the fifth transmission gate and the sixth transmission gate are connected with a reverse signal of the pre-charging control signal; and the gates of the ninth NMOS transistor, the tenth NMOS transistor and the eleventh NMOS transistor are connected with a charge return-to-zero signal.

9. The MRAM memory cell readout circuit of claim 3, wherein the comparison latch module comprises:

the comparator comprises a comparison latch unit, a positive output buffer unit and a negative output buffer unit; the first input end of the comparison latch unit is connected with the first input end of the comparison latch module, the second input end of the comparison latch unit is connected with the second input end of the comparison latch module, and the comparison latch unit is used for comparing the third signal acquired from the first output end of the coupling amplification module with the fourth signal acquired from the second output end of the coupling amplification module to generate a fifth signal and an inverted signal of the fifth signal;

the input end of the positive output buffer unit is connected with the first output end of the comparison latch unit and is used for outputting a comparison result positive signal from the output end of the positive output buffer unit after the fifth signal is buffered;

the input end of the negative output buffer unit is connected with the second output end of the comparison latch unit and used for outputting a comparison result negative signal from the output end of the negative output buffer unit after the inverted signal of the fifth signal is buffered.

10. The MRAM memory cell readout circuit of claim 9, wherein the comparison latch unit comprises: a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a twelfth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, and a seventeenth NMOS transistor;

the gate of the fifteenth NMOS transistor is connected with the first input end of the comparison latch unit, and the gate of the seventeenth NMOS transistor is connected with the second input end of the comparison latch unit; the source electrode of the fifteenth NMOS transistor and the source electrode of the seventeenth NMOS transistor are connected with the drain electrode of the twelfth NMOS transistor; the source of the twelfth NMOS transistor is grounded;

the drain of the fifteenth NMOS transistor is connected with the source of the fourteenth NMOS transistor, and the drain of the seventeenth NMOS transistor is connected with the source of the sixteenth NMOS transistor; the gate of the fourteenth NMOS transistor, the gate of the third PMOS transistor, the drain of the fourth PMOS transistor, the drain of the fifth PMOS transistor and the drain of the sixteenth NMOS transistor are connected to the second output terminal of the comparison latch unit; the gate of the sixteenth NMOS transistor, the gate of the fourth PMOS transistor, the drain of the third PMOS transistor, the drain of the second PMOS transistor, and the drain of the fourteenth NMOS transistor are connected to the first output terminal of the comparison latch unit;

the sources of the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor and the fifth PMOS transistor are connected with a comparison latch voltage; and the gates of the second PMOS transistor, the fifth PMOS transistor and the twelfth NMOS transistor are connected with an output control signal.

11. The MRAM memory cell readout circuit of claim 9, wherein the positive output buffer cell comprises: a first PMOS transistor and a thirteenth NMOS transistor;

the grid electrodes of the first PMOS transistor and the thirteenth NMOS transistor are connected with the input end of the positive output buffer unit; the drains of the first PMOS transistor and the thirteenth NMOS transistor are connected with the output end of the positive output buffer unit; the source electrode of the first PMOS transistor is connected with the comparison latch voltage, and the source electrode of the thirteenth NMOS transistor is grounded.

12. The MRAM memory cell readout circuit of claim 9, wherein the negative output buffer cell comprises: a sixth PMOS transistor and an eighteenth NMOS transistor;

the grid electrodes of the sixth PMOS transistor and the eighteenth NMOS transistor are connected with the input end of the negative output buffer unit; the drains of the sixth PMOS transistor and the eighteenth NMOS transistor are connected with the output end of the negative output buffer unit; the source electrode of the sixth PMOS transistor is connected with the comparison latch voltage, and the source electrode of the eighteenth NMOS transistor is grounded.

13. An MRAM memory system comprising an MRAM memory cell read-out circuit according to any of claims 3 to 12 and an MRAM memory array comprising a plurality of MRAM memory cells.