CN114639331B - Driving circuit, driving method thereof and display device - Google Patents
Driving circuit, driving method thereof and display device Download PDFInfo
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- CN114639331B CN114639331B CN202210238087.0A CN202210238087A CN114639331B CN 114639331 B CN114639331 B CN 114639331B CN 202210238087 A CN202210238087 A CN 202210238087A CN 114639331 B CN114639331 B CN 114639331B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
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Abstract
The invention discloses a driving circuit, a driving method thereof and a display device, which relate to the technical field of display and comprise a plurality of switching transistors, wherein each switching transistor comprises an active layer, a source electrode and a drain electrode which are positioned on the same side of the active layer, and a first grid electrode and a second grid electrode which are respectively positioned on two sides of the active layer; in the same switching transistor, the active layer comprises a first channel region and a second channel region, wherein the first channel region is a region where the first grid electrode and the active layer overlap in the first direction, and the second channel region is a region where the second grid electrode and the active layer overlap in the first direction; the first direction is the lamination direction of the active layer, the first grid electrode and the second grid electrode, and the width-to-length ratio of the first channel region is larger than that of the second channel region; at a first driving frequency, the switching transistor is turned on in response to a signal of the first gate; at the second driving frequency, the switching transistor is turned on in response to the signal of the second gate, wherein the first driving frequency is greater than the second driving frequency. This is advantageous in reducing the overall power consumption of the display device.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a driving circuit, a driving method thereof, and a display device.
Background
From the CRT (Cathode Ray Tube) age to the Liquid Crystal Display (LCD) age, to the now coming OLED (Organic Light-Emitting Diode) age and the Light-Emitting Diode display age, the display industry has undergone decades of development to become more and more different. The display industry is closely related to our life, and the display technology is not separated from the traditional mobile phones, flat-panel televisions and PCs to the current intelligent wearable equipment, VR, vehicle-mounted display and other electronic equipment.
In the related art, more and more display devices have display characteristics of high-frequency refresh frequency and low-frequency refresh frequency, and power consumption is reduced by using low-frequency display so as to compensate for power consumption increase caused by high-frequency display, so that overall power consumption of the display device is reduced to a certain extent. However, in view of the structural characteristics of the components in the display device, how to further reduce the power consumption of the low-frequency display so as to further reduce the overall power consumption of the display device is one of the technical problems to be solved in the present stage.
Disclosure of Invention
In view of the above, the present invention provides a driving circuit, a driving method thereof, and a display device, which are aimed at further reducing the power consumption in the low-frequency display stage, so as to further reduce the overall power consumption.
In a first aspect, the present application provides a driving circuit, including a plurality of switching transistors, where the switching transistors include an active layer, a source electrode and a drain electrode located on the same side of the active layer, and a first gate electrode and a second gate electrode respectively located on two sides of the active layer;
In the same switching transistor, the active layer includes a first channel region and a second channel region, the first channel region is a region where the first gate and the active layer overlap in a first direction, and the second channel region is a region where the second gate and the active layer overlap in the first direction; wherein the first direction is a stacking direction of the active layer and the first and second gates, and the width-to-length ratio of the first channel region is greater than that of the second channel region;
At a first driving frequency, the switching transistor is turned on in response to a signal of the first gate; at a second driving frequency, the switching transistor is turned on in response to a signal of the second gate, wherein the first driving frequency is greater than the second driving frequency.
In a second aspect, the present application provides a driving method for a driving circuit, which is applied to the driving circuit provided by the present application, and the driving method includes:
providing a first on signal to the first gate of at least one of the switching transistors and providing an off signal to the second gate of each of the switching transistors at a first driving frequency, causing the switching transistor to turn on in response to the signal of the first gate, transmitting a first data signal through the turned-on switching transistor;
Providing a second on signal to the second gate of at least one of the switching transistors and providing an off signal to the first gate of each of the switching transistors at a second driving frequency, causing the switching transistor to turn on in response to the signal of the second gate, transmitting a second data signal through the turned-on switching transistor; wherein the first driving frequency is greater than the second driving frequency.
In a third aspect, the present application further provides a display device, including the driving circuit provided in the first aspect of the present application.
Compared with the prior art, the driving circuit, the driving method and the display device provided by the invention have the advantages that at least the following effects are realized:
The invention provides a driving circuit and a driving method thereof and a display device, wherein the driving circuit comprises a plurality of switching transistors, and the switching transistors are transistors with double-gate structures, namely, the switching transistors comprise a first grid electrode and a second grid electrode which are respectively positioned at two sides of an active layer, correspondingly, the switching transistors also comprise a first channel region corresponding to the first grid electrode and a second channel region corresponding to the second grid electrode, wherein the first channel region is a region where the first grid electrode and the active layer are overlapped along a first direction, and the second channel region is a region where the second grid electrode and the active layer are overlapped along the first direction; conversely, the smaller the width-to-length ratio of the channel region, the larger the on-resistance of the channel, and the smaller the magnitude of the current. Under the first driving frequency, namely in a higher-frequency driving mode, the switching transistor responds to the signal conduction of the first grid electrode, namely the first channel region with larger width-length ratio is controlled to be conducted, and when the width-length ratio is larger, the charging efficiency of the switching transistor can be effectively improved, so that the driving requirement of high frequency is met. Under the second driving frequency, namely in a lower frequency driving mode, the switching transistor is turned on in response to the signal of the second grid electrode, namely the second channel region with smaller width and length is controlled to be turned on, when the width and length are smaller, the current of the second channel region can be effectively reduced, and further the power consumption in a low frequency mode can be reduced, so that the power consumption in the low frequency mode is more saved, and the overall power consumption of the display device is further reduced.
Of course, it is not necessary for any one product embodying the invention to achieve all of the technical effects described above at the same time.
Other features of the present invention and its advantages will become apparent from the following detailed description of exemplary embodiments of the invention, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic diagram of a driving circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a film layer of a switching transistor in a driving circuit according to an embodiment of the invention;
Fig. 3 is a top view of a first channel region of a switching transistor;
fig. 4 is a top view of a second channel region of the switching transistor;
fig. 5 is another top view of a first channel region of a switching transistor;
fig. 6 is another top view of a second channel region of a switching transistor;
Fig. 7 is a schematic diagram of another film layer of a switching transistor in a driving circuit according to an embodiment of the invention;
fig. 8 is a top view of a first channel region of another switching transistor according to an embodiment of the present invention;
fig. 9 is a top view of a second channel region in the switching transistor corresponding to fig. 8;
Fig. 10 is a top view of a first channel region of a switching transistor according to another embodiment of the present invention;
fig. 11 is another top view of a second channel region corresponding to the switching transistor of fig. 10;
FIG. 12 is a schematic diagram showing another connection of the driving circuit according to the embodiment of the present invention;
FIG. 13 is a flowchart of a driving method of a driving circuit according to an embodiment of the present invention;
Fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present invention;
fig. 15 is a schematic diagram showing a connection between a driving circuit and a data line in a display device according to an embodiment of the invention.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.
The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of exemplary embodiments may have different values.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.
In the related art, in order to meet the requirement of the display device for high refresh frequency, the driving circuit including the switching transistor increases the current of the channel region by increasing the width-to-length ratio of the switching transistor, thereby meeting the charging requirement under the high refresh frequency. A problem that follows is that the power consumption of the display device increases substantially, so that a low frequency display mode is introduced in the high frequency display device to reduce the overall power consumption of the display device. However, in the low frequency display mode, the switch transistor still uses a higher width-to-length ratio structure, and the channel region is still high current although the charging time is short, so that the power saving effect is poor. Therefore, how to further reduce the power consumption of the low-frequency display to further reduce the overall power consumption of the display device is one of the technical problems to be solved in the present stage.
In view of this, the present invention provides a driving circuit, a driving method thereof, and a display device, which are aimed at further reducing the power consumption in the low-frequency display stage, so as to further reduce the overall power consumption.
Fig. 1 is a schematic diagram illustrating a connection of a driving circuit according to an embodiment of the present invention, fig. 2 is a schematic diagram illustrating a film layer of a switching transistor in the driving circuit according to the embodiment of the present invention, fig. 3 is a top view of a first channel region of the switching transistor, fig. 4 is a top view of a second channel region of the switching transistor, and referring to fig. 1 to 4, a driving circuit 100 according to an embodiment of the present invention includes a plurality of switching transistors T, the switching transistors T include an active layer P, a source S0 and a drain D0 located on the same side of the active layer P, and a first gate G1 and a second gate G2 located on two sides of the active layer P, respectively;
in the same switching transistor T, the active layer P includes a first channel region Q1 and a second channel region Q2, the first channel region Q1 is a region where the first gate electrode G1 overlaps the active layer P along the first direction D1, and the second channel region Q2 is a region where the second gate electrode G2 overlaps the active layer P along the first direction D1; the first direction D1 is a stacking direction of the active layer P and the first gate G1 and the second gate G2, and the width-to-length ratio of the first channel region Q1 is greater than that of the second channel region Q2;
At the first driving frequency, the switching transistor T is turned on in response to the signal of the first gate G1; at the second driving frequency, the switching transistor T is turned on in response to the signal of the second gate G2, wherein the first driving frequency is greater than the second driving frequency.
It should be noted that, fig. 1 only illustrates the connection relationship of the partial switching transistors T in the driving circuit 100, and does not limit the number of switching transistors T actually included in the driving circuit, and in some other embodiments of the present invention, the number of switching transistors T included in the driving circuit may be other, which is not particularly limited in the present invention. Fig. 2 illustrates only the film structure of the switching transistor T, and only the first gate electrode G1 is located on the side of the active layer P facing the source electrode S0 and the drain electrode D0, and the second gate electrode G2 is located on the side of the active layer P facing away from the source electrode S0 and the drain electrode D0, which is not limited to the actual number of films and the thickness of the films of the switching transistor T in fig. 2. Fig. 3 and 4 illustrate only one top view structure of the first channel region Q1 and the second channel region Q2, and the widths and lengths of the first channel region Q1 and the second channel region Q2 are also only illustrative, and do not represent the actual dimensions of the first channel region Q1 and the second channel region Q2.
Specifically, referring to fig. 1 to 4, the driving circuit provided by the present invention includes a plurality of switching transistors T, and the switching transistors T are transistors with a dual-gate structure, that is, the switching transistors T include a first gate G1 and a second gate G2 respectively located at two sides of the active layer P, and the switching transistors T further include a first channel region Q1 corresponding to the first gate G1 and a second channel region Q2 corresponding to the second gate G2, wherein the first channel region Q1 is a region where the first gate G1 overlaps the active layer P along the first direction D1, and the second channel region Q2 is a region where the second gate G2 overlaps the active layer P along the first direction D1.
The invention limits that the width-to-length ratio of the first channel region Q1 is larger than that of the second channel region Q2, and the larger the width-to-length ratio of the channel region is, the smaller the on-resistance of the channel is, and the larger the value of current is; conversely, the smaller the width-to-length ratio of the channel region, the larger the on-resistance of the channel, and the smaller the value of the current. Under the first driving frequency, namely in a higher-frequency driving mode, the switching transistor T is turned on in response to the signal of the first grid electrode G1, namely the first channel region Q1 with larger width-length ratio is controlled to be turned on, when the width-length ratio is larger, the charging current is larger, and the charging efficiency of the switching transistor T can be effectively improved, so that the driving requirement of high frequency is met. Under the second driving frequency, namely in a lower frequency driving mode, the switching transistor T is turned on in response to the signal of the second grid electrode G2, namely the second channel region Q2 with smaller width-length ratio is controlled to be turned on, when the width-length ratio is smaller, the current of the second channel region Q2 can be effectively reduced, and further the power consumption in the low frequency mode can be reduced, so that the power consumption in the low frequency mode is more saved, and the overall power consumption of the driving circuit is further reduced.
The embodiments shown in fig. 3 and fig. 4 illustrate a block structure in which the active layer P included in the same switching transistor T is an entire surface, and in other embodiments of the present invention, the active layer P in the same switching transistor T may be further configured to include at least two sub-active layers P0, that is, the same active layer P includes at least two sub-active layers P0 that are not connected to each other, for example, please refer to fig. 5 and fig. 6, fig. 5 illustrates another top view of the first channel region Q1 of the switching transistor T, fig. 6 illustrates another top view of the second channel region Q2 of the switching transistor T, and fig. 5 and fig. 6 correspond to the first channel region and the second channel region of the same switching transistor.
Referring to fig. 5 and 6, in an alternative embodiment of the present invention, at least part of the switching transistor T includes at least two sub-active layers P0 arranged at intervals along the second direction D2, and the source S0 and the drain D0 of the switching transistor T overlap each sub-active layer P0 along the first direction D1, and the second direction D2 is the width direction of the first channel region Q1 and the second channel region Q2.
Specifically, the embodiment shown in fig. 5 and 6 illustrates a scheme in which the same active layer P includes three sub-active layers P0 aligned along the second direction D2, and in some other embodiments of the present invention, the number of sub-active layers P0 included in the same active layer P may be two or more, which is not particularly limited in the present invention.
It can be understood that, when the same active layer P includes at least two sub-active layers P0, the first channel region Q1 includes a region where the first gate electrode G1 and each sub-active layer P0 actually overlap, and taking the embodiment shown in fig. 5 as an example, the first channel region Q1 includes sub-channel regions Q11, Q12 and Q13, and the aspect ratio of the first channel region Q1 refers to the aspect ratio of the region where the first gate electrode G1 and each sub-active layer P0 actually overlap; similarly, the second channel region Q2 includes a region where the second gate electrode G2 and each sub-active layer P0 actually overlap, and, taking the embodiment shown in fig. 6 as an example, the second channel region includes sub-channel regions Q21 and Q22, and the aspect ratio of the second channel region Q2 refers to the aspect ratio of the region where the second gate electrode G2 and each sub-active layer P0 actually overlap. When the active layer P includes at least two sub-active layers P0, the source S0 and the drain D0 of the switching transistor T each overlap with the respective sub-active layers P0.
When the active layer P in the same switching transistor T is set to include a plurality of sub-active layers P0 in the embodiment of the present invention, the influence of static electricity on the switching transistor T is reduced, so that performance reliability of the switching transistor T is improved.
In an alternative embodiment of the present invention, the number and size of the sub-active layers P0 included in the different switching transistors T are the same.
In the embodiment of the present invention, the same size of the sub-active layers P0 included in different switching transistors T in the same driving circuit means that the sub-active layers P0 in the same switching transistor T have the same length and the same width, and the sub-active layers P0 in different switching transistors T have the same length and the same width. When the number of the sub-active layers P0 included in the different switching transistors T in the same driving circuit is set to be the same and the sizes are also set to be the same, the active layers P corresponding to the different switching transistors T are manufactured by adopting the same specification parameters, so that the manufacturing complexity of the driving circuit is simplified, and the production efficiency of the driving circuit is improved.
When the number of the sub-active layers P0 included in the same switching transistor T is three or more, optionally, the widths of the intervals between any two adjacent sub-active layers P0 along the second direction D2 are the same, so as to further reduce the manufacturing complexity of the switching transistor T in the driving circuit. Alternatively, the widths of the above-mentioned intervals are the same in different switching transistors T.
In an alternative embodiment of the present invention, the width to length ratio of the first channel region Q1 of the different switching transistors T is the same, and the width to length ratio of the second channel region Q2 of the different switching transistors T is the same.
Taking the embodiment shown in fig. 3 and 4 as an example, the width-to-length ratio of the first channel region is W1/L1, and the width-to-length ratio of the second channel region is W2/L2. Taking the embodiment shown in fig. 5 and 6 as an example, the width-to-length ratio of the first channel region is (w11+w12+w13)/L1, and the width-to-length ratio of the second channel region is (w21+w22)/L2.
Specifically, in the same driving circuit, the width-to-length ratios of the first channel regions Q1 corresponding to the different switching transistors T are set to be the same, so that the first channel regions Q1 in the different switching transistors T can be manufactured by adopting the same width-to-length ratio specification, and different parameters of the first channel regions Q1 are not required to be set for the different switching transistors T, thereby being beneficial to simplifying the manufacturing difficulty of the different switching transistors T. Similarly, in the same driving circuit, the width-to-length ratios of the second channel regions Q2 corresponding to the different switching transistors T are set to be the same, so that the second channel regions Q2 in the different switching transistors T can be manufactured by adopting the same width-to-length ratio specification, different parameters of the second channel regions Q2 are not required to be set for the different switching transistors T, and the manufacturing difficulty of the different switching transistors T is also facilitated to be simplified. Meanwhile, the width-to-length ratios of the first channel regions Q1 of the different switching transistors T are set to be the same, and the width-to-length ratios of the second channel regions Q2 of the different switching transistors T are set to be the same, so that the manufacturing difficulty of the switching transistors T is simplified, and the production efficiency of a driving circuit is improved.
Referring to fig. 2 and fig. 7, fig. 7 is another schematic film diagram of a switching transistor T in a driving circuit according to an embodiment of the invention, and fig. 2 and fig. 7 respectively show two film structures of the switching transistor T, wherein the difference is that the relative positions of the first gate G1 and the second gate G2 are different.
In an alternative embodiment of the present invention, please refer to fig. 2, along the first direction D1, the first gate G1 is located on the same side of the active layer P as the source S0 and the drain D0; alternatively, referring to fig. 7, along the first direction D1, the second gate G2 is located on the same side of the active layer P as the source S0 and the drain D0.
Specifically, referring to fig. 2 to 7, in the switch transistor T provided by the embodiment of the invention, when the width-to-length ratios of the first channel region Q1 and the second channel region Q2 are set to be different, the first gate G1 corresponding to the first channel region Q1 with a larger width-to-length ratio may be located at a side of the active layer P facing the source S0 and the drain D0, and the second gate G2 corresponding to the second channel region Q2 with a smaller width-to-length ratio may be located at a side of the active layer P facing away from the source S0 and the drain D0, for example, refer to fig. 2; of course, the positions of the first gate electrode G1 and the second gate electrode G2 may also be interchanged, that is, the first gate electrode G1 corresponding to the first channel region Q1 with a larger width-to-length ratio may also be located on a side of the active layer P facing away from the source electrode S0 and the drain electrode D0, and the second gate electrode G2 corresponding to the second channel region Q2 with a smaller width-to-length ratio may also be located on a side of the active layer P facing toward the source electrode S0 and the drain electrode D0, for example, please refer to fig. 7. The relative positional relationship between the first gate G1 and the second gate G2 and the active layer P is not limited, and only by controlling different driving frequencies, a turn-on signal is provided to different gates, for example, a signal is provided to the first gate G1 at a higher driving frequency to turn on the first channel region Q1, so as to improve the charging current at a higher driving frequency, and effectively improve the charging efficiency of the switching transistor T. Providing a signal to the second gate G2 at a lower driving frequency turns on the second channel region Q2 to reduce the current of the second channel region Q2 in the low frequency mode, thereby further reducing the power consumption in the low frequency mode, and thus being beneficial to further reducing the overall power consumption of the driving circuit.
When the driving circuit of the invention is manufactured on the array substrate in the display device, optionally, the switching transistor T is positioned on one side of the substrate of the array substrate, and a shading layer is arranged between the active layer and the substrate on the array substrate, so that the influence of light on the active layer is avoided. When the switching transistor T is of a double-gate structure, the bottom gate and the shading layer can be arranged on the same layer, and the manufacture of the bottom gate in the switching transistor T can be completed in the process of manufacturing the shading layer, so that the complexity of a film layer on the array substrate is not increased, and the manufacturing process of the switching transistor of the double-gate structure is also facilitated to be simplified.
In an alternative embodiment of the present invention, please refer to fig. 3 to 6, in the first channel region Q1, the width of the first gate G1 along the second direction D2 is W1, and the length of the first gate G1 along the third direction D3 is L1; in the second channel region Q2, the width of the second gate G2 along the second direction D2 is W2, the length of the second gate G2 along the third direction D3 is L2, where the second direction D2 is the width direction of the first channel region Q1 and the second channel region Q2, and the third direction D3 is the length direction of the first channel region Q1 and the second channel region Q2;
in the same switching transistor T, l1=l2, and W1 > W2.
In the driving circuit provided by the embodiment of the invention, for the same switching transistor T, in order to realize the differential design of the width-to-length ratio of the first channel region Q1 and the second channel region Q2, the widths and/or lengths of the first channel region Q1 and the second channel region Q2 may be designed differently.
Taking the embodiment shown in fig. 3 and fig. 4 as an example, when the active layer P is a monolithic structure, the first channel region Q1 and the second channel region Q2 are respectively embodied as a monolithic rectangular structure, in the first channel region Q1, the width W1 of the first gate G1 along the second direction D2 represents the width of the first channel region Q1, and the length L1 of the first gate G1 along the third direction D3 represents the length of the first channel region Q1. In the second channel region Q2, the width W2 of the second gate G2 along the second direction D2 represents the width of the second channel region Q2, and the length L2 of the second gate G2 along the third direction D3 represents the length of the second channel region Q2. In this embodiment, the length L1 of the first gate G1 in the third direction D3 and the length L2 of the second gate G2 in the third direction D3 in the first channel region Q1 and the second channel region Q2 are set to be the same, and meanwhile, the width W1 of the first gate G1 in the second direction D2 in the first channel region Q1 is set to be greater than the width W2 of the second gate G2 in the second channel region Q2 in the second direction D2, so that the design that the width-to-length ratio W1/L1 of the first channel region Q1 is greater than the width-to-length ratio W2/L2 of the second channel region Q2 is realized. Meanwhile, as l1=l2, the first gate G1 and the second gate G2 are designed to be equal in length in the first channel region Q1 and the second channel region Q2, and only the widths of the first gate G1 and the second gate G2 in the channel region need to be designed differently, so that the manufacturing process can be simplified while the width-to-length ratio differential design of the first channel region Q1 and the second channel region Q2 is realized.
It can be understood that when the active layer P includes two or more sub-active layers P0, for example, referring to fig. 5 and 6, the width of the first channel region Q1 refers to the sum of the widths of the portions of the first gate electrode G1 overlapped with the respective sub-active layers P0 along the second direction D2, that is, w1=w11+w12+w13; the width of the second channel region Q2 refers to the sum of the widths of the portions of the second gate electrode G2 overlapping the respective sub-active layers P0 in the second direction D2, that is, w2=w21+w22.
The foregoing embodiments illustrate a scheme of implementing the differential design of the width-to-length ratio of the first and second channel regions Q1 and Q2 by differentially designing the widths of the first and second gate electrodes G1 and G2 while the lengths of the channel regions remain the same, and in some other embodiments of the present invention, the differential design of the width-to-length ratio may also be implemented by adjusting the lengths of the channel regions.
For example, please refer to fig. 8 and 9, wherein fig. 8 is a top view of a first channel region Q1 in another switching transistor T provided by the embodiment of the present invention, fig. 9 is a top view of a second channel region Q2 in a switching transistor T corresponding to fig. 8, in an alternative embodiment of the present invention, a width of a first gate G1 along a second direction D2 in the first channel region Q1 is W1, and a length of the first gate G1 along a third direction D3 is L1; in the second channel region Q2, the width of the second gate G2 along the second direction D2 is W2, the length of the second gate G2 along the third direction D3 is L2, where the second direction D2 is the width direction of the first channel region Q1 and the second channel region Q2, and the third direction D3 is the length direction of the first channel region Q1 and the second channel region Q2;
in the same switching transistor T, w1=w2, and L1 < L2.
The embodiment shown in fig. 8 and 9 is illustrated by taking the case where the active layer P in the switching transistor T includes three sub-active layers P0 as an example, and at this time, the width of the first channel region Q1 refers to the sum of the widths of the overlapping portions of the first gate electrode G1 and the respective sub-active layers P0 in the first channel region Q1 along the second direction D2, that is, w1=w11+w12+w13; the width of the second channel region Q2 refers to the sum of the widths of the portions of the second channel region Q2 where the second gate electrode G2 overlaps the respective sub-active layers P0 in the second direction D2, that is, w2=w21+w22+w23. In this embodiment, the first gate electrode G1 overlaps the three sub-active layers P0, the second gate electrode G2 overlaps the three sub-active layers P0, and w1=w2 is set. On the basis, the length L1 of the first grid electrode G1 in the first channel region Q1 along the third direction D3 is set to be smaller than the length L2 of the second grid electrode G2 in the second channel region Q2 along the third direction D3, so that the width-to-length ratio W1/L1 of the first channel region Q1 is smaller than the width-to-length ratio W2/L2 of the second channel region Q2. In this embodiment, the width-to-length ratio requirements of the first channel region Q1 and the second channel region Q2 can be achieved by only differentially designing the lengths of the first channel region Q1 and the second channel region Q2 without differentially designing the widths of the first channel region Q1 and the second channel region Q2, so that the manufacturing process of the switching transistor T is simplified, and further, the manufacturing process of the driving circuit is simplified, so that the production efficiency is improved.
The embodiments shown in fig. 8 and 9 illustrate a scheme in which the widths of the first channel region Q1 and the second channel region Q2 are set to be the same, and the lengths of the first channel region Q1 and the second channel region Q2 are differently designed to realize that the width-to-length ratio of the first channel region Q1 is greater than that of the second channel region Q2. In other embodiments of the present invention, to achieve that the width-to-length ratio of the first channel region Q1 is greater than the width-to-length ratio of the second channel region Q2, the lengths of the first channel region Q1 and the second channel region Q2 may also be differentially designed, and the widths of the first channel region Q1 and the second channel region Q2 may be simultaneously differentially designed.
For example, please refer to fig. 10 and 11, wherein fig. 10 is a top view of a first channel region Q1 of another switching transistor T according to an embodiment of the present invention, fig. 11 is another top view of a second channel region Q2 corresponding to the switching transistor T of fig. 10, in an alternative embodiment of the present invention, a width of the first gate G1 along the second direction D2 in the first channel region Q1 is W1 (specifically w11+w12+13), and a length of the first gate G1 along the third direction D3 is L1; in the second channel region Q2, the width of the second gate G2 along the second direction D2 is W2, the length of the second gate G2 along the third direction D3 is L2, where the second direction D2 is the width direction of the first channel region Q1 and the second channel region Q2, and the third direction D3 is the length direction of the first channel region Q1 and the second channel region Q2;
in the same switching transistor T, W1 > W2, and L1 < L2.
The embodiment shown in fig. 10 and 11 is illustrated by taking the case where the active layer P in the switching transistor T includes three sub-active layers P0 as an example, and at this time, the width of the first channel region Q1 refers to the sum of the widths of the portions of the first channel region Q1 overlapped by the respective sub-active layers P0 along the second direction D2, that is, w1=w11+w12+w13; the width of the second channel region Q2 refers to the sum of the widths of the second gate electrode G2 and the sub-active layer P0 overlapping portion of the second channel region Q2 in the second direction D2, that is, w2=w21. The length L1 of the first channel region Q1 refers to the length of the first gate G1 in the third direction D3 in the first channel region Q1, and the length L2 of the second channel region Q2 refers to the length of the second gate G2 in the third direction D3 in the second channel region Q2. The invention sets W1 to W2 and L1 to L2, thereby achieving the design requirement that the width-to-length ratio of the first channel region Q1 is larger than that of the second channel region Q2. The width difference of the first channel region Q1 and the second channel region Q2 is designed, and the length is also designed differently, so that the method is particularly suitable for the situation that the width-to-length ratio difference of the first channel region Q1 and the second channel region Q2 is large.
Referring to fig. 12, fig. 12 is a schematic diagram showing another connection of a driving circuit according to an embodiment of the invention, in an alternative embodiment of the invention, the driving circuit includes a plurality of switch units K0, and the switch units K0 include at least three switch transistors T; in the same switching unit K0, the first gate G1 and the second gate G2 of each switching transistor T are connected to different switching control signal lines L, the source S0 of each switching transistor T is connected to the same signal input line SR, and the drain D0 of each switching transistor T is connected to different data lines 10.
Specifically, the embodiment shown in fig. 12 is described by taking the driving circuit including two switch units K0 as an example, and in other embodiments of the present invention, the number of switch units K0 included in the driving circuit may be 3 or more, which is not particularly limited in the present invention. In addition, in the embodiment shown in fig. 12, only one switching unit K0 includes three switching transistors T as an example, and in some other embodiments of the present invention, the number of switching transistors T that may be included in one switching unit K0 may be other, for example, may be more than three.
In the same switching unit K0, the first gate G1 and the second gate G2 of each switching transistor T are respectively connected to different switching control signal lines L, and when the same switching unit K0 includes three switching transistors T, the number of corresponding switching control signal lines L is 6. The source S0 of each switching transistor T in the same switching unit K0 is connected to the same signal input line SR, the drain D0 is connected to different data lines 10, and if three data lines 10 are respectively the first data line 11, the second data line 12, and the third data line 13, when data transmission to the first data line 11 is required, the switching transistor T connected to the first data line 11 can be controlled to be turned on, and when the driving frequency is the high frequency driving frequency, an on signal can be provided to the first gate G1 of the corresponding switching transistor T, and an off signal can be provided to each gate of the second gate G2 and other transistors, and at this time, a data signal can be provided to the first data line 11 through the signal input line SR. Similarly, in the high frequency driving mode, when the data signal needs to be supplied to the second data line 12, the switching transistor T may be turned on by supplying the on signal to the first gate G1 of the switching transistor T connected to the second data line 12, so that the other switching transistors T in the switching unit K0 are turned off. In the low frequency driving mode, when the data signal is required to be supplied to the second data line 12, the switching transistor T may be turned on by supplying an on signal to the second gate G2 of the switching transistor T connected to the second data line 12, so that the other switching transistors T in the switching unit K0 are all turned off. The manner of providing the data to the third data signal line may refer to the manner of providing the data to the second data line 12, which is not described herein.
When the same switching unit K0 includes three switching transistors T, the same signal input line SR is used to provide data signals to three different data lines 10 in a time-sharing manner, so that the number of signal input lines SR in the driving circuit is greatly reduced, thereby being beneficial to simplifying the structure of the driving circuit. When the signal input line SR is electrically connected to the signal terminals on the driving chip to transmit signals from the driving chip, the design of the present invention is also advantageous for reducing the number of signal terminals included in the driving chip, so as to simplify the structural complexity of the driving chip.
Based on the same inventive concept, the present invention also provides a driving method of a driving circuit, which is applied to the driving circuit of any of the above embodiments of the present invention, and fig. 13 is a flowchart of the driving method of the driving circuit provided by the embodiment of the present invention, and please combine fig. 1 to fig. 4 and fig. 13, the driving method includes:
at a first driving frequency, providing a first on signal to a first gate G1 of at least one switching transistor T, and providing an off signal to a second gate G2 of each switching transistor T, so that the switching transistor T is turned on in response to the signal of the first gate G1, and transmitting a first data signal through the turned-on switching transistor T;
At a second driving frequency, providing a second on signal to a second gate G2 of at least one switching transistor T, and providing an off signal to a first gate G1 of each switching transistor T, so that the switching transistor T is turned on in response to the signal of the second gate G2, and transmitting a second data signal through the turned-on switching transistor T; wherein the first driving frequency is greater than the second driving frequency.
Specifically, in the embodiment of the invention, the switching transistor T in the driving circuit is configured to have a double-gate structure, and the width-to-length ratio of the first channel region Q1 corresponding to the first gate G1 is greater than the width-to-length ratio of the second channel region Q2 corresponding to the second gate G2, so that a larger charging current can be provided when the first channel region Q1 is turned on, and a smaller charging current can be provided when the second channel region Q2 is turned on. In the high-frequency driving mode, namely under the first driving frequency, the first grid electrode G1 is provided with the conducting signal to enable the first channel region Q1 to be conducted, and the charging efficiency of the switching transistor T can be effectively improved due to the fact that the width-to-length ratio of the first channel region Q1 is large and the charging current is large, so that the driving requirement of the high frequency is met. In the low-frequency driving mode, namely in the second driving frequency, the second gate G2 is provided with a conducting signal to conduct the second channel region Q2, and the width-to-length ratio of the second channel region Q2 is smaller, so that the charging current is smaller, the current of the second channel region Q2 in the low-frequency driving mode can be reduced, the power consumption in the low-frequency mode can be reduced, and the overall power consumption of the display device can be reduced further.
Referring to fig. 12, in an alternative embodiment of the present invention, the driving circuit includes a plurality of switch units K0, and the switch units K0 include at least three switch transistors T;
At a first driving frequency, providing a first on signal to a first gate G1 of a switching transistor T in the same switching unit K0 in a time-sharing manner;
At the second driving frequency, the second on signal is provided to the second gate G2 of the switching transistor T in the same switching unit K0 in a time-sharing manner.
Specifically, when the driving circuit provided in the embodiment of the present invention is configured as shown in the drawings, the same switching unit K0 includes three switching transistors T, and three first gates G1 and three second gates G2 corresponding to the three switching transistors T are respectively connected to different switching control signal lines L, and different channel regions of the switching transistors T can be selectively turned on under the control of the switching control signal lines L, for example, different switching transistors T can be controlled to be turned on in a time-sharing manner. For example, at the first driving frequency, the different switching transistors T can be turned on in a time-sharing manner by providing the on signals to the first gates G1 of the different switching transistors T in the same switching unit K0 in a time-sharing manner, and at this time, the corresponding first channel region Q1 has a larger width-to-length ratio, and the charging current is larger, so as to meet the high-frequency use requirement. At the second driving frequency, the different switching transistors T can be turned on in a time-sharing manner by providing the on signals to the second gates G2 of the different switching transistors T in the same switching unit K0 in a time-sharing manner, and at this time, the corresponding second channel region Q2 has a smaller width-to-length ratio, and the charging current is smaller, so that the power consumption in the low-frequency driving mode is greatly reduced, thereby being beneficial to reducing the overall power consumption of the driving circuit.
In addition, only one signal input line SR corresponds to the same switching unit K0, and the signal can be provided to the three data lines 10 in a time-sharing manner by one signal input, so that the number of signal input lines SR included in the whole driving circuit is greatly reduced, thereby being beneficial to reducing the number of signal terminals on the corresponding driving chip and simplifying the structure of the driving chip.
Based on the same inventive concept, the present invention also provides a display device, fig. 14 is a schematic structural diagram of a display device 200 according to an embodiment of the present invention, and fig. 15 is a schematic connecting diagram of a driving circuit 100 and a data line 10 in the display device 200 according to an embodiment of the present invention, where the display device includes the driving circuit according to any one of the above embodiments of the present invention.
When the display device includes the aforementioned driving circuit, referring to fig. 12, optionally, the driving circuit is located in a non-display area NA of the display device 200, and a plurality of data lines 10 are disposed in the display area AA of the display device for transmitting data signals to the sub-pixels in the display area AA. The drain D0 of the switching transistor T in the driving circuit is electrically connected to the data line 10, and a data signal can be transmitted to the data line 10 corresponding to the turned-on switching transistor T through the signal input line SR. Because the switching transistor T included in the driving circuit 100 has a dual-gate structure, channel regions corresponding to different gates can be selectively turned on in different driving frequency modes, for example, a first channel region with a larger width-to-length ratio in the switching transistor T is turned on in a high-frequency driving mode, so that charging current is increased, and high-frequency display requirements are met; the second channel region with smaller width and length in the switch transistor T is conducted in the low-frequency driving mode, so that charging current is reduced, power consumption in the low-frequency driving mode is further reduced, and overall power consumption of the display device is further reduced.
It should be noted that, the embodiment of the display device provided by the present invention may refer to the embodiment of the driving circuit, and will not be described herein. The display device provided by the embodiment of the invention can be embodied as any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
In summary, the driving circuit, the driving method thereof and the display device provided by the invention at least realize the following beneficial effects:
The invention provides a driving circuit and a driving method thereof and a display device, wherein the driving circuit comprises a plurality of switching transistors, and the switching transistors are transistors with double-gate structures, namely, the switching transistors comprise a first grid electrode and a second grid electrode which are respectively positioned at two sides of an active layer, correspondingly, the switching transistors also comprise a first channel region corresponding to the first grid electrode and a second channel region corresponding to the second grid electrode, wherein the first channel region is a region where the first grid electrode and the active layer are overlapped along a first direction, and the second channel region is a region where the second grid electrode and the active layer are overlapped along the first direction; conversely, the smaller the width-to-length ratio of the channel region, the larger the on-resistance of the channel, and the smaller the magnitude of the current. Under the first driving frequency, namely in a higher-frequency driving mode, the switching transistor responds to the signal conduction of the first grid electrode, namely the first channel region with larger width-length ratio is controlled to be conducted, and when the width-length ratio is larger, the charging efficiency of the switching transistor can be effectively improved, so that the driving requirement of high frequency is met. Under the second driving frequency, namely in a lower frequency driving mode, the switching transistor is turned on in response to the signal of the second grid electrode, namely the second channel region with smaller width and length is controlled to be turned on, when the width and length are smaller, the current of the second channel region can be effectively reduced, and further the power consumption in a low frequency mode can be reduced, so that the power consumption in the low frequency mode is more saved, and the overall power consumption of the display device is further reduced.
While certain specific embodiments of the invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (12)
1. The driving circuit is characterized by comprising a plurality of switching transistors, wherein each switching transistor comprises an active layer, a source electrode and a drain electrode which are positioned on the same side of the active layer, and a first grid electrode and a second grid electrode which are respectively positioned on two sides of the active layer;
In the same switching transistor, the active layer includes a first channel region and a second channel region, the first channel region is a region where the first gate and the active layer overlap in a first direction, and the second channel region is a region where the second gate and the active layer overlap in the first direction; wherein the first direction is a stacking direction of the active layer and the first and second gates, and the width-to-length ratio of the first channel region is greater than that of the second channel region;
At a first driving frequency, the switching transistor is turned on in response to a signal of the first gate; at a second driving frequency, the switching transistor is turned on in response to a signal of the second gate, wherein the first driving frequency is greater than the second driving frequency.
2. The driver circuit according to claim 1, wherein in at least part of the switching transistors, the active layer includes at least two sub-active layers arranged at intervals along a second direction, and in the first direction, a source electrode and a drain electrode of the switching transistor each overlap with each of the sub-active layers, and the second direction is a width direction of the first channel region and the second channel region.
3. The driver circuit of claim 2, wherein the number and size of the sub-active layers included in different switching transistors are the same.
4. The driver circuit of claim 1, wherein the aspect ratio of the first channel regions of different switching transistors is the same and the aspect ratio of the second channel regions of different switching transistors is the same.
5. The drive circuit according to claim 1, wherein the first gate electrode is located on the same side of the active layer as the source electrode and the drain electrode in the first direction; or along the first direction, the second gate electrode is positioned on the same side of the active layer as the source electrode and the drain electrode.
6. The driver circuit according to claim 1, wherein in the first channel region, a width of the first gate in the second direction is W1, and a length of the first gate in the third direction is L1; in the second channel region, the width of the second gate along the second direction is W2, the length of the second gate along the third direction is L2, wherein the second direction is the width direction of the first channel region and the second channel region, and the third direction is the length direction of the first channel region and the second channel region;
In the same switching transistor, l1=l2, and W1 > W2.
7. The driver circuit according to claim 1, wherein in the first channel region, a width of the first gate in the second direction is W1, and a length of the first gate in the third direction is L1; in the second channel region, the width of the second gate along the second direction is W2, the length of the second gate along the third direction is L2, wherein the second direction is the width direction of the first channel region and the second channel region, and the third direction is the length direction of the first channel region and the second channel region;
in the same switching transistor, w1=w2, and L1 < L2.
8. The driver circuit according to claim 1, wherein in the first channel region, a width of the first gate in the second direction is W1, and a length of the first gate in the third direction is L1; in the second channel region, the width of the second gate along the second direction is W2, the length of the second gate along the third direction is L2, wherein the second direction is the width direction of the first channel region and the second channel region, and the third direction is the length direction of the first channel region and the second channel region;
in the same switching transistor, W1 > W2, and L1 < L2.
9. The drive circuit according to claim 1, wherein the drive circuit includes a plurality of switching units including at least three of the switching transistors; in the same switching unit, the first gate and the second gate of each switching transistor are respectively connected with different switching control signal lines, the source of each switching transistor is connected with the same signal input line, and the drain of each switching transistor is respectively connected with different data lines.
10. A driving method of a driving circuit, applied to the driving circuit according to any one of claims 1 to 9, characterized by comprising:
providing a first on signal to the first gate of at least one of the switching transistors and providing an off signal to the second gate of each of the switching transistors at a first driving frequency, causing the switching transistor to turn on in response to the signal of the first gate, transmitting a first data signal through the turned-on switching transistor;
Providing a second on signal to the second gate of at least one of the switching transistors and providing an off signal to the first gate of each of the switching transistors at a second driving frequency, causing the switching transistor to turn on in response to the signal of the second gate, transmitting a second data signal through the turned-on switching transistor; wherein the first driving frequency is greater than the second driving frequency.
11. The driving method according to claim 10, wherein the driving circuit includes a plurality of switching units including at least three of the switching transistors;
Providing the first conduction signal to a first gate of the switching transistor in the same switching unit in a time-sharing manner at the first driving frequency;
and at the second driving frequency, providing the second conduction signal to a second gate of the switching transistor in the same switching unit in a time sharing mode.
12. A display device comprising the drive circuit according to any one of claims 1 to 9.
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| CN111725250A (en) * | 2020-06-29 | 2020-09-29 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display panel |
| CN112670305A (en) * | 2020-12-30 | 2021-04-16 | 厦门天马微电子有限公司 | Display panel and display device |
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| CN111402799B (en) * | 2020-04-09 | 2021-07-06 | 武汉天马微电子有限公司 | Light-emitting drive circuit and drive method, organic light-emitting display panel and device |
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| CN111725250A (en) * | 2020-06-29 | 2020-09-29 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display panel |
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