CN114638185A - Chip verification method and device and storage medium - Google Patents
Chip verification method and device and storage medium Download PDFInfo
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Abstract
A chip verification method, a device and a storage medium are provided, wherein the method comprises the following steps: obtaining verification excitation used for chip verification and an actual output result of the chip; inputting the verification excitation into a preset neural network model to obtain a prediction probability and a prediction result; the preset probability is the probability that the verification excitation input chip predicted by the neural network model has an output result, and the predicted result is the output result of the verification excitation input chip predicted by the neural network model; and screening verification stimuli according to a preset stimulus screening rule, the actual output result, the prediction probability and the prediction result of the chip, and sending the screened verification stimuli into the verification environment of the chip to verify the chip. According to the invention, through the addition of the neural network model, the input verification excitation is more biased to areas which are not easy to verify or are not verified in the verification chip, so that the chip verification efficiency can be improved, and the verification can be more comprehensively covered.
Description
Technical Field
The invention relates to the field of chip design, in particular to a chip verification method, a chip verification device and a storage medium.
Background
As the feature size of the chip is continuously reduced, the complexity of the chip itself is gradually increased, and the time and effort required to verify the complete function of the chip are greatly increased. Functional verification based on RTL (Register Transfer Level) simulation is a critical but very time-consuming step for design, and the verifier needs to exhaust all possible situations to generate excitation for the design and count the coverage rate under different excitation situations. Therefore, an important issue faced by current verification is how to generate appropriate stimuli quickly, which can shorten the simulation time while covering all possible scenarios as much as possible.
Disclosure of Invention
To solve the above technical problems or achieve the above object, in an aspect of the present invention, a chip verification method is provided, the method including: obtaining verification excitation used for chip verification and an actual output result of the chip; inputting the verification excitation into a preset neural network model to obtain a prediction probability and a prediction result; wherein the preset probability is the probability that the verification stimulus predicted by the neural network model is input into the chip and has an output result, and the predicted result is the output result of the verification stimulus predicted by the neural network model and input into the chip; and screening the verification stimulus according to a preset stimulus screening rule, the actual output result of the chip, the prediction probability and the prediction result, and sending the screened verification stimulus into a verification environment of the chip to verify the chip.
In one or more embodiments, the incentive screening rules include: and in response to the prediction probability being larger than a first preset value and the prediction result not being in the actual output result of the chip, sending the corresponding verification stimulus to the verification environment of the chip to perform chip verification.
In one or more embodiments, the incentive filtering rules further comprise: and in response to the prediction probability being larger than a first preset value and the prediction result being in the actual output result of the chip, filtering out the corresponding verification stimulus and acquiring the next verification stimulus.
In one or more embodiments, the verification incentives are centrally managed by a preset set of verification incentives, the method further comprising: deleting verification stimuli filtered out by the screening rule in the set of verification stimuli.
In one or more embodiments, the incentive filtering rules further comprise: in response to the prediction probability being smaller than a second preset value, filtering out the corresponding verification stimulus and acquiring the next verification stimulus; wherein the second preset value is smaller than the first preset value.
In one or more embodiments, the incentive filtering rules further comprise: responding to the prediction probability which is more than or equal to the second preset value and less than or equal to the first preset value, sending corresponding verification excitation to a verification environment of the chip, and obtaining an actual output result of the chip; saving the corresponding verification stimulus and the actual output result as a learning sample of the neural network model.
In one or more embodiments, the neural network model has a self-learning function, the method further comprising: feeding the learning samples into the neural network model such that the neural network model learns itself based on the learning samples.
In one or more embodiments, the chip verification method of the present invention further includes: acquiring a training sample, wherein the training sample comprises an excitation and an output result of a simulation chip preset by the excitation input; constructing a neural network model, and training the neural network model through the training sample; obtaining a verification sample, and verifying the prediction accuracy of the neural network model through the verification sample; responding to the prediction accuracy rate of the neural network model being more than or equal to a preset value, and outputting a corresponding neural network model; the preset simulation chip is designed for simulating a target chip.
In a second aspect of the present invention, an optimization apparatus for chip verification is provided, including: at least one processor; the environment module is used for providing a verification environment for the chip verification; and a memory, in which an executable computer program is preset, and when executed by the at least one processor, the computer program is configured to implement the steps of the chip verification method according to any one of the above embodiments, and the steps include: obtaining verification excitation for chip verification and an actual output result of the chip; inputting the verification excitation into a preset neural network model to obtain a prediction probability and a prediction result; wherein the preset probability is the probability that the verification stimulus predicted by the neural network model is input into the chip and has an output result, and the predicted result is the output result of the verification stimulus predicted by the neural network model and input into the chip; and screening the verification stimulus according to a preset stimulus screening rule, the actual output result of the chip, the prediction probability and the prediction result, and sending the screened verification stimulus into a verification environment of the chip to verify the chip.
In one or more embodiments, the incentive screening rules include: and sending corresponding verification stimulus to a verification environment of the chip to perform chip verification in response to the prediction probability being greater than a first preset value and the prediction result not being in an actual output result of the chip.
In one or more embodiments, the incentive filtering rules further comprise: and in response to the prediction probability being larger than a first preset value and the prediction result being in the actual output result of the chip, filtering out the corresponding verification stimulus and acquiring the next verification stimulus.
In one or more embodiments, the verification incentives are centrally managed by a preset set of verification incentives, the method further comprising: deleting verification stimuli filtered out by the screening rule in the set of verification stimuli.
In one or more embodiments, the incentive filtering rules further comprise: in response to the prediction probability being smaller than a second preset value, filtering out the corresponding verification stimulus and acquiring the next verification stimulus; wherein the second preset value is smaller than the first preset value.
In one or more embodiments, the incentive filtering rules further comprise: responding to the prediction probability which is more than or equal to the second preset value and less than or equal to the first preset value, sending corresponding verification excitation to a verification environment of the chip, and obtaining an actual output result of the chip; saving the corresponding verification stimulus and the actual output result as a learning sample of the neural network model.
In one or more embodiments, the neural network model has a self-learning function, the method further comprising: feeding the learning samples into the neural network model such that the neural network model learns itself based on the learning samples.
In one or more embodiments, the chip verification method of the present invention further includes: acquiring a training sample, wherein the training sample comprises an excitation and an output result of a simulation chip preset by the excitation input; constructing a neural network model, and training the neural network model through the training sample; obtaining a verification sample, and verifying the prediction accuracy of the neural network model through the verification sample; responding to the prediction accuracy rate of the neural network model being more than or equal to a preset value, and outputting a corresponding neural network model; the preset simulation chip is designed for simulating a target chip.
In a third aspect of the present invention, a readable storage medium is provided, where an executable computer program is preset in the readable storage medium, and when the computer program is executed, the computer program is configured to implement the steps of the chip verification method according to any one of the above embodiments, and the steps include: obtaining verification excitation used for chip verification and an actual output result of the chip; inputting the verification excitation into a preset neural network model to obtain a prediction probability and a prediction result; wherein the preset probability is the probability that the verification stimulus predicted by the neural network model is input into the chip and has an output result, and the predicted result is the output result of the verification stimulus predicted by the neural network model and input into the chip; and screening the verification stimulus according to a preset stimulus screening rule, the actual output result of the chip, the prediction probability and the prediction result, and sending the screened verification stimulus into a verification environment of the chip to verify the chip.
In one or more embodiments, the incentive screening rules include: and sending corresponding verification stimulus to a verification environment of the chip to perform chip verification in response to the prediction probability being greater than a first preset value and the prediction result not being in an actual output result of the chip.
In one or more embodiments, the incentive filtering rules further comprise: and in response to the prediction probability being larger than a first preset value and the prediction result being in the actual output result of the chip, filtering out the corresponding verification stimulus and acquiring the next verification stimulus.
In one or more embodiments, the verification incentives are centrally managed by a preset set of verification incentives, the method further comprising: deleting verification stimuli filtered out by the screening rule in the set of verification stimuli.
In one or more embodiments, the incentive filtering rules further comprise: in response to the prediction probability being smaller than a second preset value, filtering out the corresponding verification stimulus and acquiring the next verification stimulus; wherein the second preset value is smaller than the first preset value.
In one or more embodiments, the incentive filtering rules further comprise: responding to the prediction probability which is more than or equal to the second preset value and less than or equal to the first preset value, sending corresponding verification excitation to a verification environment of the chip, and obtaining an actual output result of the chip; saving the corresponding verification stimulus and the actual output result as a learning sample of the neural network model.
In one or more embodiments, the neural network model has a self-learning function, the method further comprising: feeding the learning samples into the neural network model such that the neural network model learns itself based on the learning samples.
In one or more embodiments, the chip verification method of the present invention further includes: acquiring a training sample, wherein the training sample comprises an excitation and an output result of a simulation chip preset by the excitation input; constructing a neural network model, and training the neural network model through the training sample; obtaining a verification sample, and verifying the prediction accuracy of the neural network model through the verification sample; responding to the prediction accuracy rate of the neural network model being more than or equal to a preset value, and outputting a corresponding neural network model; the preset simulation chip is designed for simulating a target chip.
The beneficial effects of the invention include: the invention filters the verification excitation of the verification environment of each chip to be input by training the neural network model in advance and identifying the output possibility and possible output result of each verification excitation input target chip by using the neural network model, thereby leading the input verification excitation to be more inclined to areas which are not easy to verify or not verified in the verification chip, improving the verification efficiency of the chip and realizing more comprehensive coverage verification of the chip.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a flowchart illustrating the operation of a chip verification method according to the present invention;
FIG. 2 is a schematic structural diagram of a chip verification optimization apparatus according to the present invention;
fig. 3 is a schematic structural diagram of a readable storage medium according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
The chip verification method provided by the invention introduces the machine learning model on the premise of not changing the original verification framework, realizes the screening of verification excitation by utilizing the machine learning model, and realizes self-learning in real time according to the actual output result of the chip, thereby realizing self-improvement. The method can effectively reduce the simulation condition of useless or repeated chip verification coverage, greatly save the simulation time and shorten the verification period. The steps of the present invention will be described in detail below with reference to the accompanying drawings.
FIG. 1 is a flowchart illustrating a chip verification method according to the present invention. As shown in fig. 1, the work flow of the chip verification method of the present invention includes: step S1, obtaining verification excitation for chip verification and actual output result of the chip; step S2, inputting the verification excitation into a preset neural network model to obtain a prediction probability and a prediction result; the preset probability is the probability that the verification excitation input chip predicted by the neural network model has an output result, and the predicted result is the output result of the verification excitation input chip predicted by the neural network model; and step S3, screening the verification stimulus according to a preset stimulus screening rule, the actual output result, the prediction probability and the prediction result of the chip, and sending the screened verification stimulus into the verification environment of the chip for chip verification.
Specifically, in a general embodiment, the verification stimulus is randomly generated by a stimulus generator, and then sent to the simulation design of the chip, and the coverage of the corresponding verification stimulus is determined according to whether the simulation design has an output result. It can be understood that when no result is output after the verification stimulus is sent to the simulation design of the chip, the corresponding verification stimulus is considered to be invalid without hitting; on the contrary, when the verification stimulus is sent to the chip after the simulation design and has an output result, the corresponding verification stimulus is considered to hit, and the verification stimulus is effective. A large amount of verification excitation is generated through the excitation generator and is input into the simulation design of the chip to obtain various output results of the simulation design, so that the aim of chip verification is fulfilled. The verification method is equivalent to detecting the target by using a large amount of random collisions, and due to the lack of effective constraint, the verification method is time-consuming, and the verification efficiency and comprehensiveness cannot be guaranteed.
Therefore, in the embodiment of the present invention, the neural network model is trained in advance, and the neural network model is used to identify the possibility and possible output result of each verification stimulus input target chip, so as to filter the verification stimulus of each verification environment to be input into the chip, so that the input verification stimulus is more biased to areas which are not easy to verify or not verified in the verification chip, thereby not only improving the verification efficiency of the chip, but also realizing more comprehensive coverage verification of the chip.
In the above, the constraint on the verification stimulus is realized by a preset screening rule.
In one embodiment, the incentive filter rule includes: and sending the corresponding verification excitation to the verification environment of the chip to perform chip verification in response to the prediction probability being greater than the first preset value and the prediction result not being in the actual output result of the chip.
Specifically, in the process of chip verification, the actual output result of the chip is stored, specifically, in a preset coverage database. The neural network model obtains randomly generated excitation from an excitation generator, predicts the excitation and obtains a prediction probability and a prediction result; the preset probability is the probability that the verification excitation input chip predicted by the neural network model has an output result, and the prediction result is the output result of the verification excitation input chip predicted by the neural network model; when the prediction probability is larger than a first preset value, the probability that the verification excitation has an output result is high, then the prediction results are subjected to traversal comparison in a coverage rate database, and when the prediction results are found not to be in the actual output results of the chip, the verification excitation is judged not to appear before, so that the verification excitation is allowed to be sent to the verification environment of the chip to verify the chip.
In another embodiment, the incentive filter rule further comprises: and in response to the prediction probability being larger than the first preset value and the prediction result being in the actual output result of the chip, filtering out the corresponding verification stimulus and acquiring the next verification stimulus. It can be understood that, when the predicted result is in the actual output result of the chip, i.e. in the coverage database, it is determined that the excitation or the corresponding region of the chip has been verified, and repeated verification is not required, so that the current verification excitation needs to be filtered, and the next verification excitation is obtained, so as to avoid repeated verification, thereby contributing to improving the verification efficiency of the chip.
In a further embodiment, the verification stimulus is centrally managed by a preset verification stimulus set, and correspondingly, the method of the present invention further comprises: the verification incentives filtered out by the screening rule are deleted in the set of verification incentives. It can be understood that the verification stimulus set is used for storing various non-repetitive historical data, which can be used for not only optimizing the neural network model, but also artificially generating stimuli uncovered by testing through the analysis of the verification stimuli, so as to more comprehensively realize the verification of the chip.
In one embodiment, the incentive filtering rules further comprise: in response to the prediction probability being smaller than a second preset value, filtering out the corresponding verification stimulus and acquiring the next verification stimulus; wherein the second preset value is smaller than the first preset value. It can be understood that when the predicted probability of the verification stimulus is smaller than the second preset value, the verification stimulus is considered to have a higher probability of being an invalid stimulus, and therefore the verification stimulus needs to be filtered.
In one embodiment, the incentive filtering rules further comprise: sending the corresponding verification excitation into the verification environment of the chip in response to the prediction probability being more than or equal to the second preset value and less than or equal to the first preset value, and obtaining the actual output result of the chip; and saving the corresponding verification excitation and the actual output result as a learning sample of the neural network model.
Specifically, because the training data of the neural network model is limited, when the neural network model is applied to the actual chip verification, the situation that the verification excitation cannot be accurately identified occurs; it will be appreciated that the prediction results predicted by the neural network model are also inaccurate in this case. Therefore, the verification stimulus with the prediction probability between the first preset value and the second preset value is regarded as a valid stimulus, and the prediction result of the verification stimulus is saved as a learning sample for the self-learning of the neural network model. In addition, the neural network model self-learning can also be understood as self-adjusting to constrain the verification stimuli, thereby making the input verification stimuli more biased toward areas in the verification chip that are not easily verified or not verified.
In a further embodiment, the neural network model has a self-learning function, and the chip verification method of the present invention further includes: the learning samples are fed into the neural network model such that the neural network model learns itself based on the learning samples.
In a further embodiment, the process of training the neural network model of the present invention comprises: acquiring a training sample, wherein the training sample comprises an excitation and an output result of the excitation input preset simulation chip; constructing a neural network model, and training the neural network model through a training sample; obtaining a verification sample, and verifying the prediction accuracy of the neural network model through the verification sample; responding to the prediction accuracy rate of the neural network model being more than or equal to a preset value, and outputting the corresponding neural network model; the preset simulation chip is designed for simulating the target chip.
In a specific embodiment, the neural network model calculates a probability value P of an output result based on a Logistic regression algorithm, and classifies according to two thresholds 0< beta < alpha <1, if P is more than or equal to alpha, a corresponding bin is classified as deccided-1, which means that the bin test is covered, namely, the corresponding verification excitation is effective excitation; if the decision is that P ≦ β, the corresponding bin is classified as Decoded-0, which means that the test fails to cover, i.e., the corresponding stimulus is a null stimulus and will be deleted. If β < p < α, the corresponding bin is classified as outstanding, indicating that the model is uncertain and the test can cover, the neural network model needs to be self-learned to be self-perfected.
In a second aspect of the present invention, an optimization apparatus for chip verification is provided. Fig. 2 is a schematic structural diagram of the chip verification optimization apparatus of the present invention. As shown in fig. 2, the chip verification optimizing apparatus of the present invention includes: at least one processor 100; an environment module 200 for providing a verification environment for chip verification; and a memory 300, wherein the memory 300 is pre-loaded with an executable computer program 301, and when the computer program 301 is executed by at least one processor 100, the method for implementing the chip verification method according to any of the above embodiments includes the steps of: obtaining verification excitation used for chip verification and an actual output result of the chip; inputting the verification excitation into a preset neural network model to obtain a prediction probability and a prediction result; the preset probability is the probability that a verification excitation input chip predicted by the neural network model has an output result, wherein the predicted result is the output result of the verification excitation input chip predicted by the neural network model; screening verification stimuli according to a preset stimulus screening rule, an actual output result, a prediction probability and a prediction result of the chip, and sending the screened verification stimuli into a verification environment of the chip to verify the chip. And the DUT is the chip to be verified.
Specifically, in a general embodiment, the verification stimulus is randomly generated by a stimulus generator, and then sent to the simulation design of the chip, and the coverage of the corresponding verification stimulus is determined according to whether the simulation design has an output result. It can be understood that when no result is output after the verification stimulus is sent to the simulation design of the chip, the corresponding verification stimulus is considered to be invalid without hit; on the contrary, when the verification stimulus is sent to the chip after the simulation design and has an output result, the corresponding verification stimulus is considered to hit, and the verification stimulus is effective. A large amount of verification excitation is generated through the excitation generator and is input into the simulation design of the chip to obtain various output results of the simulation design, so that the aim of chip verification is fulfilled. The verification method is equivalent to detecting the target by using a large number of random collisions, and due to the lack of effective constraint, the verification method is extremely time-consuming, and the verification efficiency and comprehensiveness cannot be guaranteed.
Therefore, in the embodiment of the present invention, the neural network model is trained in advance, and the neural network model is used to identify the possibility and possible output result of each verification stimulus input target chip, so as to filter the verification stimulus of each verification environment to be input into the chip, so that the input verification stimulus is more biased to areas which are not easy to verify or not verified in the verification chip, thereby not only improving the verification efficiency of the chip, but also realizing more comprehensive coverage verification of the chip.
In the above, the constraint on the verification stimulus is realized by a preset screening rule.
In one embodiment, the incentive filter rule includes: and sending the corresponding verification excitation to the verification environment of the chip to perform chip verification in response to the prediction probability being greater than the first preset value and the prediction result not being in the actual output result of the chip.
Specifically, in the process of chip verification, the actual output result of the chip is stored, specifically, in a preset coverage database. The neural network model obtains randomly generated excitation from an excitation generator, predicts the excitation and obtains a prediction probability and a prediction result; the preset probability is the probability that the verification excitation input chip predicted by the neural network model has an output result, and the prediction result is the output result of the verification excitation input chip predicted by the neural network model; when the prediction probability is larger than a first preset value, the probability that the verification excitation has an output result is high, then the prediction results are subjected to traversal comparison in a coverage rate database, and when the prediction results are found not to be in the actual output results of the chip, the verification excitation is judged not to appear before, so that the verification excitation is allowed to be sent to the verification environment of the chip to verify the chip.
In another embodiment, the incentive filter rule further comprises: and in response to the prediction probability being larger than the first preset value and the prediction result being in the actual output result of the chip, filtering out the corresponding verification stimulus and acquiring the next verification stimulus. It can be understood that, when the predicted result is in the actual output result of the chip, i.e. in the coverage database, it is determined that the excitation or the corresponding region of the chip has been verified, and repeated verification is not required, so that the current verification excitation needs to be filtered, and the next verification excitation is obtained, so as to avoid repeated verification, thereby contributing to improving the verification efficiency of the chip.
In a further embodiment, the verification stimulus is centrally managed by a preset verification stimulus set, and correspondingly, the method of the present invention further comprises: the verification incentives filtered out by the screening rule are deleted in the set of verification incentives. It can be understood that the verification stimulus set is used for storing various non-repetitive historical data, which can be used for not only optimizing the neural network model, but also artificially generating stimuli uncovered by testing through the analysis of the verification stimuli, so as to more comprehensively realize the verification of the chip.
In one embodiment, the incentive filtering rules further comprise: in response to the prediction probability being smaller than a second preset value, filtering out the corresponding verification stimulus and acquiring the next verification stimulus; and the second preset value is smaller than the first preset value. It can be understood that when the predicted probability of the verification stimulus is smaller than the second preset value, the verification stimulus is considered to have a higher probability of being an invalid stimulus, and therefore the verification stimulus needs to be filtered.
In one embodiment, the incentive filtering rules further comprise: sending the corresponding verification excitation into the verification environment of the chip in response to the prediction probability being more than or equal to the second preset value and less than or equal to the first preset value, and obtaining the actual output result of the chip; and storing the corresponding verification excitation and the actual output result as a learning sample of the neural network model.
Specifically, because the training data of the neural network model is limited, when the neural network model is applied to the actual chip verification, the situation that the verification excitation cannot be accurately identified occurs; it will be appreciated that the prediction results predicted by the neural network model are also inaccurate in this case. Therefore, the verification excitation with the prediction probability between the first preset value and the second preset value is regarded as the effective excitation, and the prediction result of the verification excitation is saved as a learning sample for the self-learning of the neural network model. In addition, the neural network model self-learning can also be understood as self-adjusting to constrain the verification stimuli, thereby making the input verification stimuli more biased toward areas in the verification chip that are not easily verified or not verified.
In a further embodiment, the neural network model has a self-learning function, and the chip verification method of the present invention further includes: the learning samples are fed into the neural network model such that the neural network model learns itself based on the learning samples.
In a further embodiment, the process of training the neural network model of the present invention comprises: acquiring a training sample, wherein the training sample comprises an excitation and an output result of the excitation input preset simulation chip; constructing a neural network model, and training the neural network model through a training sample; obtaining a verification sample, and verifying the prediction accuracy of the neural network model through the verification sample; responding to the prediction accuracy rate of the neural network model being more than or equal to a preset value, and outputting the corresponding neural network model; the preset simulation chip is designed for simulating the target chip.
In a third aspect of the invention, a readable storage medium is presented. Fig. 3 is a schematic structural diagram of a readable storage medium according to the present invention. The readable storage medium 400 of the present invention as shown in fig. 3 includes: an executable computer program 401, the computer program 401 being adapted to perform the steps of the chip verification method as in any of the above embodiments when executed.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method of chip verification, the method comprising:
obtaining verification excitation used for chip verification and an actual output result of the chip;
inputting the verification excitation into a preset neural network model to obtain a prediction probability and a prediction result; wherein the preset probability is the probability that the verification stimulus predicted by the neural network model is input into the chip and has an output result, and the predicted result is the output result of the verification stimulus predicted by the neural network model and input into the chip;
and screening the verification stimulus according to a preset stimulus screening rule, the actual output result of the chip, the prediction probability and the prediction result, and sending the screened verification stimulus into a verification environment of the chip to verify the chip.
2. The chip verification method according to claim 1, wherein the incentive screening rule comprises:
and sending corresponding verification stimulus to a verification environment of the chip to perform chip verification in response to the prediction probability being greater than a first preset value and the prediction result not being in an actual output result of the chip.
3. The chip verification method according to claim 2, wherein the incentive filtering rule further comprises:
and in response to the prediction probability being larger than a first preset value and the prediction result being in the actual output result of the chip, filtering out the corresponding verification stimulus and acquiring the next verification stimulus.
4. The chip verification method according to claim 3, wherein the verification stimuli are centrally managed by a preset verification stimuli set, the method further comprising:
deleting verification stimuli filtered out by the screening rule in the set of verification stimuli.
5. The chip verification method according to claim 3, wherein the incentive filter rule further comprises:
in response to the prediction probability being smaller than a second preset value, filtering out the corresponding verification stimulus and acquiring the next verification stimulus;
wherein the second preset value is smaller than the first preset value.
6. The chip verification method according to claim 5, wherein the incentive filtering rule further comprises:
responding to the prediction probability which is more than or equal to the second preset value and less than or equal to the first preset value, sending corresponding verification excitation to a verification environment of the chip, and obtaining an actual output result of the chip;
saving the corresponding verification stimulus and the actual output result as a learning sample of the neural network model.
7. The chip verification method according to claim 6, wherein the neural network model has a self-learning function, the method further comprising:
feeding the learning samples into the neural network model such that the neural network model learns itself based on the learning samples.
8. The chip verification method according to claim 1, further comprising:
acquiring a training sample, wherein the training sample comprises an excitation and an output result of a simulation chip preset by the excitation input;
constructing a neural network model, and training the neural network model through the training sample;
obtaining a verification sample, and verifying the prediction accuracy of the neural network model through the verification sample;
responding to the prediction accuracy rate of the neural network model being more than or equal to a preset value, and outputting a corresponding neural network model;
the preset simulation chip is designed for simulating a target chip.
9. An apparatus for optimizing chip verification, comprising:
at least one processor;
the environment module is used for providing a verification environment for the chip verification; and
a memory, in which an executable computer program is preinstalled, the computer program, when being executed by the at least one processor, being adapted to carry out the steps of the chip verification method according to any one of claims 1 to 8.
10. A readable storage medium, wherein the readable storage medium is pre-loaded with an executable computer program, and the computer program is used to implement the steps of the chip verification method according to any one of claims 1 to 8 when executed.
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| CN116431421A (en) * | 2023-06-13 | 2023-07-14 | 成都登临科技有限公司 | Neural network generation method and generator, verification method and system and storage medium |
| CN116431421B (en) * | 2023-06-13 | 2023-08-29 | 成都登临科技有限公司 | Neural network generation method and generator, verification method and system and storage medium |
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