CN114629356A

CN114629356A - Missile-borne secondary power supply multi-path output time sequence control method

Info

Publication number: CN114629356A
Application number: CN202210194761.XA
Authority: CN
Inventors: 胡庚; 韩明; 徐云华; 陈欢
Original assignee: Beijing Institute of Computer Technology and Applications
Current assignee: Beijing Institute of Computer Technology and Applications
Priority date: 2022-03-01
Filing date: 2022-03-01
Publication date: 2022-06-14
Anticipated expiration: 2042-03-01
Also published as: CN114629356B

Abstract

The invention relates to a missile-borne secondary power supply multi-path output time sequence control method, and belongs to the field of missile-borne computers. The output end of an input reverse connection protection and EMI filter circuit is connected with the input ends of a power-down maintaining and pre-voltage stabilizing circuit and a multi-path isolation output time sequence control circuit, the output end of the power-down maintaining and pre-voltage stabilizing circuit is connected with the input end of a DC push-pull isolation conversion rectifying circuit, the output end of the DC push-pull isolation conversion rectifying circuit is connected with the input ends of the multi-path isolation output time sequence control circuit and a secondary voltage stabilizing filter output circuit, the output end of the multi-path isolation output time sequence control circuit is connected with the input end of the secondary voltage stabilizing filter output circuit, and when a secondary power supply is electrified, an output Vout1 is electrified in advance to output a Vout2 and an output Vout 3; when the secondary power supply is powered down, the output Vout1 lags the output Vout2 and the output Vout 3. The invention has the advantages of small influence by load characteristics, high control precision and stability, flexible time sequence adjustment, controllable power-off time sequence and capability of realizing advanced power-on and delayed power-off of certain circuit output.

Description

Missile-borne secondary power supply multi-path output time sequence control method

Technical Field

The invention belongs to the field of missile-borne computers, and particularly relates to a missile-borne secondary power supply multi-path output time sequence control method.

Background

The power supply of the airborne computer equipment is generally supplied by a multi-path isolation secondary power output, such as a host Vout1, a bus Vout2, a switching value Vout3 and the like. In order to ensure the reliable operation of logic control and data communication in the power-on and power-off processes of computer equipment, the time sequence requirements of the output power supply of the multi-path isolation secondary power supply are as follows: when the power is on, the host machine Vout1 is electrified in advance of the bus Vout2 and the switching value Vout 3; when the power is off, the main unit Vout1 lags behind the bus Vout2 and the switching value Vout3, so it is important to design a multi-channel isolated output secondary power supply with controllable power-on and power-off timing.

The traditional method for controlling the output time sequence of the multi-path isolation secondary power supply generally adopts a mode of sequentially enabling output by cascading of each path of output, for example, enabling to control Vout2 output after Vout1 output is effective, and enabling to control Vout3 output after Vout2 output is effective, the power-on time sequence of the control mode is easily influenced by the characteristics of each path of load, the control precision and stability are poor, the time sequence adjustment is inflexible, and the power-off time sequence is uncontrollable or cannot realize the power-on and power-off delay functions of output of a certain path at the same time.

Disclosure of Invention

Technical problem to be solved

The invention provides a missile-borne secondary power supply multi-output time sequence control method, and aims to solve the problems that the traditional time sequence control method is large in load characteristic influence, poor in control precision and stability, inflexible in time sequence adjustment, uncontrollable in power-off time sequence or incapable of realizing advanced power-on and delayed power-off of a certain circuit output and the like.

(II) technical scheme

In order to solve the technical problem, the invention provides a missile-borne secondary power supply multi-output time sequence control method, wherein a time sequence control circuit comprises circuits of an input reverse connection protection and EMI filter circuit, a power-down holding and pre-voltage stabilizing circuit, a DC push-pull isolation conversion rectifying circuit, a multi-output isolation time sequence control circuit and a secondary voltage stabilizing filter output circuit; the secondary voltage-stabilizing filter output circuit comprises a secondary voltage-stabilizing filter output circuit a, a secondary voltage-stabilizing filter output circuit b and a secondary voltage-stabilizing filter output circuit c;

when a secondary power supply of the missile-borne computer is electrified, an input voltage Vin outputs a voltage Va after being input into a reverse connection protection and EMI filter circuit, the voltage Va inputs a power-down maintaining and pre-stabilizing circuit and a multi-path isolation output time sequence control circuit, when the voltage Va rises from zero voltage to a voltage set value which is greater than the voltage of the power-down maintaining and pre-stabilizing circuit, the output voltage Vb of the power-down maintaining and pre-stabilizing circuit is effective, the output voltage Vb enters a DC push-pull isolation conversion rectification circuit and is output into a secondary voltage Vc1, a secondary voltage Vc2 and a secondary voltage Vc3 after being subjected to push-pull isolation conversion rectification, the secondary voltage Vc1, the secondary voltage Vc2 and the secondary voltage Vc3 are respectively input into a secondary voltage stabilizing filter output circuit a, a secondary voltage stabilizing filter output circuit b and a secondary voltage stabilizing filter output circuit c, and the secondary voltage Vc2 and the secondary voltage Vc3 are input into the multi-path isolation output time sequence control circuit, the multi-path isolation output timing control circuit outputs Vd1 and Vd2 to a secondary voltage-stabilizing filter output circuit b and a secondary voltage-stabilizing filter output circuit c; the output voltage Vc1 is regulated by a secondary voltage-stabilizing filter output circuit a to output Vout1, and the output Vout1 is electrified; at the moment, an output Vd1 and an output Vd2 in the multi-path isolation output timing control circuit are low level, and the outputs of the secondary voltage stabilizing filter output circuit b and the secondary voltage stabilizing filter output circuit c are forbidden; along with the continuous rising of the input voltage Va, the output Vd1 of the multi-path isolation output timing control circuit is at a high level, the output Vout2 of the secondary voltage-stabilizing filter output circuit is effective, the output Vd2 of the multi-path isolation output timing control circuit is at a high level, the Vout3 of the secondary voltage-stabilizing filter output circuit is effective, at the moment, the power-on of the output Vout2 and the output Vout3 is completed, and the power-on functions of the output Vout1 leading the output Vout2 and the output Vout3 are realized;

when the secondary power supply of the missile-borne computer is powered off, the input voltage Va starts to drop from the rated voltage, the output Vd1 and the output Vd2 of the multi-path isolation output sequence control circuit are at low level, the output of the secondary voltage-stabilizing filter output circuit b and the output of the secondary voltage-stabilizing filter output circuit c are forbidden, the power-off of the output Vout2 and the output Vout3 is finished at the moment, the output Vc1 of the DC push-pull isolation conversion rectifying circuit is normal, and therefore the output Vout1 is still effective; when the voltages of the energy storage capacitor C6 and the energy storage capacitor C7 of the power-down maintaining and wide-range voltage pre-stabilizing circuit are discharged to be smaller than the set value of the under-voltage protection voltage of the power-down maintaining and wide-range voltage pre-stabilizing circuit, the output voltage Vb of the power-down maintaining and wide-range voltage pre-stabilizing circuit is forbidden, the output Vc1 of the DC push-pull isolation conversion rectifying circuit is forbidden, the output of the secondary voltage stabilizing filter output circuit a is forbidden, at the moment, the output Vout1 is powered off, and the power-down functions of the output Vout1, the output Vout2 and the output Vout3 are achieved.

(III) advantageous effects

The invention provides a missile-borne secondary power supply multi-path output time sequence control method, which adopts a multi-path isolation output time sequence control circuit and a secondary voltage stabilization filter output circuit to realize the power-on time sequence control function of multi-path isolation output of a missile-borne secondary power supply, and further realizes the power-off time sequence control function of multi-path isolation output through a power-down maintaining and pre-voltage stabilizing circuit. The missile-borne secondary power supply multi-path output time sequence control method solves the problems that a traditional multi-path isolation secondary power supply output time sequence control method is easily influenced by load characteristics of all paths, and is poor in control precision and stability, inflexible in time sequence adjustment, uncontrollable in power-off time sequence and the like, and has the characteristics of being little influenced by the load characteristics, high in control precision and stability, flexible in time sequence adjustment, controllable in power-off time sequence, capable of realizing advanced power-on and delayed power-off of output of a certain circuit and the like.

Drawings

FIG. 1 is a schematic block diagram of a method for controlling the multi-output timing of a missile-borne secondary power supply according to the present invention;

FIG. 2 is a circuit diagram of the input reverse connection protection and EMI filter circuit of the missile-borne secondary power supply multi-output timing control method according to the invention;

FIG. 3 is a diagram of a power-down maintaining and pre-voltage stabilizing circuit of the missile-borne secondary power supply multi-output sequential control method according to the invention;

FIG. 4 is a diagram of a DC push-pull isolation conversion rectification circuit of the missile-borne secondary power supply multi-output timing control method of the invention;

FIG. 5 is a diagram of a multiplexed isolated output timing control circuit of the method for controlling the multiplexed output timing of a missile-borne secondary power supply according to the present invention.

Fig. 6 is a circuit diagram of a secondary voltage stabilizing filter output circuit of the missile-borne secondary power supply multi-output timing control method of the present invention.

Detailed Description

In order to make the objects, contents and advantages of the present invention more apparent, the following detailed description of the present invention will be made in conjunction with the accompanying drawings and examples.

The invention discloses a missile-borne secondary power supply multi-path output time sequence control method, which comprises the following steps: the power failure protection and pre-stabilization circuit comprises an input reverse connection protection and EMI filter circuit (1), a power failure holding and pre-stabilization circuit (2), a DC push-pull isolation conversion rectifying circuit (3), a multi-path isolation output sequential control circuit (4) and a secondary voltage stabilization filter output circuit (5). The output end of the input reverse connection protection and EMI filter circuit (1) is connected with the input end of the power-down maintaining and pre-voltage stabilizing circuit (2) and the input end of the multi-path isolation output sequential control circuit (4), the output end of the power-down maintaining and pre-voltage stabilizing circuit (2) is connected with the input end of the DC push-pull isolation conversion rectifying circuit (3), the output end of the DC push-pull isolation conversion rectifying circuit (3) is connected with the input end of the multi-path isolation output sequential control circuit (4) and the input end of the secondary voltage stabilizing filter output circuit (5), and the output end of the multi-path isolation output sequential control circuit (4) is connected with the input end of the secondary voltage stabilizing filter output circuit (5).

The invention adopts a multi-path isolated output time sequence control circuit and a secondary voltage-stabilizing filter output circuit to realize the power-on time sequence control function of multi-path isolated output of the missile-borne secondary power supply, and further realizes the power-off time sequence control function of the multi-path isolated output through a power-off maintaining and voltage pre-stabilizing circuit. The missile-borne secondary power supply multi-path output time sequence control method solves the problems that a traditional multi-path isolation secondary power supply output time sequence control method is easily influenced by load characteristics of all paths, and is poor in control precision and stability, inflexible in time sequence adjustment, uncontrollable in power-off time sequence and the like, and has the characteristics of being little influenced by the load characteristics, high in control precision and stability, flexible in time sequence adjustment, controllable in power-off time sequence, capable of realizing advanced power-on and delayed power-off of output of a certain circuit and the like.

The invention aims to provide a missile-borne secondary power supply multi-path isolation output time sequence control method, which solves the problems of large load characteristic influence, poor control precision and stability, inflexible time sequence adjustment, uncontrollable power-off time sequence or incapability of realizing leading power-on and lagging power-off of certain output circuit and the like in the traditional time sequence control method.

A missile-borne secondary power supply multi-path output time sequence control method is applied to a circuit comprising an input reverse connection protection and EMI filter circuit, a power failure holding and pre-voltage stabilizing circuit, a DC push-pull isolation conversion rectifying circuit, a multi-path isolation output time sequence control circuit and a secondary voltage stabilizing filter output circuit, wherein the secondary voltage stabilizing filter output circuit comprises a secondary voltage stabilizing filter output circuit a, a secondary voltage stabilizing filter output circuit b and a secondary voltage stabilizing filter output circuit c.

Wherein, input protection and EMI filter circuit of joining conversely includes: the circuit comprises a transient voltage suppression diode D1, a transient voltage suppression diode D2, an ideal diode controller U1, a voltage stabilizing diode D3, an N-channel field effect transistor S1, a current limiting resistor R1, a filter capacitor C1, a common mode inductor L1, a differential mode capacitor C2, a differential mode capacitor C3, a differential mode inductor L2, a common mode capacitor C4 and a common mode capacitor C5. The power down holding and pre-voltage stabilizing circuit comprises: the current-limiting circuit comprises a current-limiting resistor R2, a current-limiting resistor R3, an energy-storing capacitor C6, an energy-storing capacitor C7, a rectifier diode D4, a synchronous switch buck-boost controller U2, an N-channel field effect transistor S2, an N-channel field effect transistor S3, an N-channel field effect transistor S4, an N-channel field effect transistor S5, an energy-storing inductor L2, a voltage-dividing resistor R4, a voltage-dividing resistor R5, a filter capacitor C8, a current sampling resistor R6, a voltage-dividing sampling resistor R7, a voltage-dividing sampling resistor R8 and a filter capacitor C9. DC push-pull isolation conversion rectifying circuit, including: the pulse width modulation push-pull controller comprises a pulse width modulation push-pull controller U3, an N-channel field effect transistor S6, an N-channel field effect transistor S7, a high-frequency switching transformer T1, a rectifier diode D5, a rectifier diode D6, a rectifier diode D7, a rectifier diode D8, a rectifier diode D9, a rectifier diode D10, a filter inductor L3, a filter inductor L4, a filter inductor L5, a filter capacitor C10, a filter capacitor C11 and a filter capacitor C12. The isolated output sequential control circuit of the multipath includes: the high-precision voltage reference source V1, a photoelectric coupler B1, a voltage division current-limiting resistor R9, a voltage division current-limiting resistor R10, a voltage division current-limiting resistor R11, an energy storage delay capacitor C13, an energy storage delay capacitor C14, a current-limiting resistor R12, a current-limiting resistor R13, a voltage stabilizing diode D11, a voltage division current-limiting resistor R14, a voltage division current-limiting resistor R15, a voltage division current-limiting resistor R16, a voltage division current-limiting resistor R17, a filter capacitor C15 and a filter capacitor C16. Two-stage voltage-stabilizing filter output circuit includes: the low dropout regulator U4, the low dropout regulator U5, the low dropout regulator U6, partial pressure sampling resistance R18, partial pressure sampling resistance R19, partial pressure sampling resistance R20, partial pressure sampling resistance R21, partial pressure sampling resistance R22, partial pressure sampling resistance R23, output filter capacitor C17, output filter capacitor C18, output filter capacitor C19, load resistance RL1 and load resistance RL 2.

The output end of the input reverse connection protection and EMI filter circuit is connected with the input end of the power-down maintaining and pre-voltage stabilizing circuit and the input end of the multi-path isolation output time sequence control circuit, the output end of the power-down maintaining and pre-voltage stabilizing circuit is connected with the input end of the DC push-pull isolation conversion rectifying circuit, the output end of the DC push-pull isolation conversion rectifying circuit is connected with the input end of the multi-path isolation output time sequence control circuit and the input ends of the secondary voltage stabilizing filter output circuit a, the secondary voltage stabilizing filter output circuit b and the secondary voltage stabilizing filter output circuit c, and the output end of the multi-path isolation output time sequence control circuit is connected with the input ends of the secondary voltage stabilizing filter output circuit b and the secondary voltage stabilizing filter output circuit c.

IN the input reverse connection protection and EMI filter circuit, the cathode of the transient voltage suppression diode D1 is connected with the input high-end Vin +, the IN end of the ideal diode controller U1 is connected with the input high-end Vin +, the SOURCE end of the ideal diode controller U1, the SOURCE of the N-channel FET S1 and the anode of the voltage-stabilizing diode D3, the grid of the N-channel FET S1 is connected with the cathode of the voltage-stabilizing diode D3 and the GATE end of the ideal diode controller U1, the drain of the N-channel FET S1 is connected with the OUT end of the ideal diode controller U1, one end of the filter capacitor C1, one end of the differential mode capacitor C2 and the input end of the common mode inductor L1, the anode of the transient voltage suppression diode D1 is connected with the anode of the transient voltage suppression diode D2, the cathode of the transient voltage suppression diode D2 is connected with the VSS end of the ideal diode controller U1 and one end of the current-limiting resistor R1, The other end of the filter capacitor C1 is connected, the input negative terminal of the common mode inductor L1 is respectively connected with the other end of the differential mode capacitor C2, the other end of the current-limiting resistor R1 and the input ground Vin-, the output positive terminal of the common mode inductor L1 is respectively connected with one end of the differential mode inductor L2 and one end of the differential mode capacitor C3, the other end of the differential mode inductor L2 is respectively connected with one end of the common mode capacitor C4 and the output high terminal Va, the other end of the common mode capacitor C4 is respectively connected with one end of the common mode capacitor C5 and the chassis ground, and the other end of the common mode capacitor C5 is respectively connected with the output negative terminal of the common mode inductor L1, the other end of the differential mode capacitor C3 and the signal ground.

In the power-down holding and pre-stabilizing circuit, an input high-end Va is respectively connected with one end of a current-limiting resistor R2, one end of a current-limiting resistor R3, a cathode of a rectifying diode D4, one end of a voltage-dividing resistor R4, one end of a filter capacitor C8 and a drain electrode of an N-channel field effect transistor S2, the other end of the current-limiting resistor R2 is respectively connected with the other end of a current-limiting resistor R3, an anode of a rectifying diode D4, a positive end of an energy-storage capacitor C6 and a positive end of an energy-storage capacitor C7, the other end of the voltage-dividing resistor R4 is respectively connected with an RUN end of a synchronous switch buck-boost controller U2 and one end of a voltage-dividing resistor R5, the other end of a voltage-dividing resistor R5 is respectively connected with a negative end of an energy-storage capacitor C6, a negative end of an energy-storage capacitor C7, the other end of a filter capacitor C8 and a signal ground, a source electrode of an N-channel field effect transistor S38 2 is respectively connected with one end of an energy-storage inductor L2 and a drain electrode of an N-channel field effect transistor S4, and the other end of an energy-storage inductor L2 is respectively connected with a source electrode S3, The drain of the N-channel field effect transistor S5 is connected, the source of the N-channel field effect transistor S4 is connected with the source of the N-channel field effect transistor S5, one end of the current sampling resistor R6 and the ISENSE + end of the synchronous switch buck-boost controller U2 respectively, the other end of the current sampling resistor R6 is connected with the ISENSE-end of the synchronous switch buck-boost controller U2, the GND end of the synchronous switch buck-boost controller U2 and signal ground respectively, the gate of the N-channel field effect transistor S2 is connected with the TG1 end of the synchronous switch buck-boost controller U2, the gate of the N-channel field effect transistor S4 is connected with the BG1 end of the synchronous switch buck-boost controller U2, the gate of the N-channel field effect transistor S3 is connected with the TG2 end of the synchronous switch buck-boost controller U2, the gate of the N-channel field effect transistor S5 is connected with the BG2 end of the synchronous switch buck-boost controller U2 respectively, and the drain of the N-channel field effect transistor S3 is connected with the BG 7 end of the sampling resistor R7 respectively, One end of the filter capacitor C9 is connected with the output high end Vb, the other end of the voltage division sampling resistor R7 is connected with the VSENSE end of the synchronous switch buck-boost controller U2 and one end of the voltage division sampling resistor R8, and the other end of the voltage division sampling resistor R8 is connected with the other end of the filter capacitor C9 and the signal ground.

In the DC push-pull isolation conversion rectifying circuit, an input high end Vb is respectively connected with a VCC end of a pulse width modulation push-pull controller U3 and a 2 end of a primary winding Np1 of a high-frequency switching transformer T1, a 1 end of a primary winding Np1 of the high-frequency switching transformer T1 is connected with a drain electrode of an N-channel field effect tube S6, a 3 end of a primary winding Np1 of the high-frequency switching transformer T1 is connected with a drain electrode of the N-channel field effect tube S7, and a source electrode of the N-channel field effect tube S6 is respectively connected with a source electrode of the N-channel field effect tube S7, a GND end of the pulse width modulation push-pull controller U3 and a signal ground. The grid of the N-channel field effect transistor S6 is connected with the PWM1 end of the pulse width modulation push-pull controller U3, the grid of the N-channel field effect transistor S7 is connected with the PWM2 end of the pulse width modulation push-pull controller U3, the 4 end of the secondary winding Ns1 of the high-frequency switching transformer T1 is connected with the anode of the rectifier diode D5, the cathode of the rectifier diode D5 is respectively connected with the cathode of the rectifier diode D6 and one end of the filter inductor L3, the anode of the rectifier diode D6 is connected with the 6 end of the secondary winding Ns1 of the high-frequency switching transformer T1, the other end of the filter inductor L3 is respectively connected with one end of the filter capacitor C10 and the output positive terminal Vc1+, the other end of the filter capacitor C10 is respectively connected with the 5 end of the secondary winding Ns 10 and the output negative terminal Vc 10-of the high-frequency switching transformer T10, the 7 end of the secondary winding 10 of the high-frequency switching transformer T10 is respectively connected with the anode of the rectifier diode D10, and the cathode of the rectifier diode D10, One end of a filter inductor L4 is connected, the anode of a rectifier diode D8 is connected with the 9 end of a secondary winding Ns2 of a high-frequency switch transformer T1, the other end of the filter inductor L4 is respectively connected with one end of a filter capacitor C11 and the output positive end Vc2+, the other end of a filter capacitor C11 is respectively connected with the 8 end and the output negative end Vc 2-of a secondary winding Ns2 of the high-frequency switch transformer T1, the 10 end of a secondary winding Ns3 of the high-frequency switch transformer T1 is connected with the anode of a rectifier diode D9, the cathode of a rectifier diode D9 is respectively connected with the cathode of the rectifier diode D10 and one end of a filter inductor L5, the anode of the rectifier diode D10 is connected with the 12 end of a secondary winding Ns3 of the high-frequency switch transformer T1, the other end of the filter inductor L5 is respectively connected with one end and the output positive end 3+ of a filter capacitor C12 and the other end of the filter capacitor C12 is respectively connected with the other end of a secondary winding Ns 3611 of a secondary winding transformer T3 of the high-frequency switch transformer T1, The output negative terminal Vc 3-is connected.

In the multi-path isolation output time sequence control circuit, an input high end Va is respectively connected with one end of a voltage division current-limiting resistor R9, one end of a current-limiting resistor R12 and one end of a current-limiting resistor R13, the other end of a voltage division current-limiting resistor R9 is connected with one end of a voltage division current-limiting resistor R10, the other end of a voltage division current-limiting resistor R10 is respectively connected with a Ref end of a high-precision voltage reference source V1, one end of a voltage division current-limiting resistor R11, one end of an energy storage delay capacitor C13 and one end of an energy storage delay capacitor C14, the other end of a voltage division current-limiting resistor R11 is respectively connected with the other end of an energy storage delay capacitor C13, the other end of an energy storage delay capacitor C14, the anode A end of a high-precision voltage reference source V1 and a signal ground, the other end of a current-limiting resistor R12 is respectively connected with the other end of a voltage-stabilizing diode R13, the cathode of a voltage stabilizing diode D11 and the cathode C end of a high-precision voltage reference source V1, and the anode of a voltage stabilizing diode D11 is respectively connected with an input end 1+ (1) of a photocoupler B8242, The input end 2+ of the photoelectric coupler B1 is connected, and the input end 1-of the photoelectric coupler B1 is respectively connected with the input end 2-of the photoelectric coupler B1 and the signal ground. An output end 1C of a photoelectric coupler B1 is connected with one end of a voltage-dividing current-limiting resistor R14, one end of a voltage-dividing current-limiting resistor R15, one end of a filter capacitor C15 and an output high-end Vd1 respectively, the other end of a voltage-dividing current-limiting resistor R14 is connected with an input positive end Vc2+, an output end 1E of a photoelectric coupler B1 is connected with the other end of a voltage-dividing current-limiting resistor R15, the other end of a filter capacitor C15 and an input negative end Vc2 respectively, an output end 2C of a photoelectric coupler B1 is connected with one end of a voltage-dividing current-limiting resistor R16, one end of a voltage-dividing current-limiting resistor R17, one end of a filter capacitor C16 and an output high-end Vd2 respectively, the other end of a voltage-dividing current-limiting resistor R16 is connected with an input positive end Vc3+, and an output end 2E of a photoelectric coupler B1 is connected with the other end of a current-dividing current-limiting resistor R17, the other end of a filter capacitor C16 and an input negative end Vc 3-respectively.

IN the two-stage voltage-stabilizing filtering output circuit, an input positive end Vc1+ is respectively connected with an IN end of a low-dropout regulator U4 and an EN end of a low-dropout regulator U4, an OUT end of the low-dropout regulator U4 is respectively connected with one end of a voltage-dividing sampling resistor R18, one end of an output filtering capacitor C17 and an output high end Vout1, the other end of the voltage-dividing sampling resistor R18 is respectively connected with an ADJ end of the low-dropout regulator U4 and one end of a voltage-dividing sampling resistor R19, a GND end of the low-dropout regulator U4 is respectively connected with an input negative end Vc1-, the other end of the voltage-dividing sampling resistor R19 and the other end of the output filtering capacitor C17, an input positive end Vc2+ is connected with the IN end of the low-dropout regulator U5, an input high end 1 is connected with the EN end of the low-dropout regulator U5, the OUT end of the low-dropout regulator U5 is respectively connected with one end of the sampling voltage-dividing sampling resistor R20, one end of the output filtering capacitor C18 and one end of a load resistor 1, The output high-end Vout2 is connected, the other end of the voltage dividing and sampling resistor R20 is respectively connected with the ADJ end of the low dropout regulator U5 and one end of the voltage dividing and sampling resistor R21, the GND end of the low dropout regulator U5 is respectively connected with the input negative end Vc2-, the other end of the voltage dividing and sampling resistor R21, the other end of the output filter capacitor C18 and the other end of the load resistor RL1, the input positive end Vc3+ is connected with the IN end of the low dropout regulator U6, the input high end 82Vd 56 is connected with the EN end of the low dropout regulator U6, the OUT end of the low dropout regulator U6 is respectively connected with one end of the voltage dividing and sampling resistor R22, one end of the output filter capacitor C19, one end of the load resistor RL 52 and the output high end Vout3, the other end of the voltage dividing and sampling resistor R22 is respectively connected with the ADJ end of the low dropout regulator U6 and one end of the voltage dividing and sampling resistor R23, the GND end of the low dropout regulator U6 is respectively connected with the input negative end 3-, the GND end of the voltage dividing and sampling resistor R9342-, the other end of the voltage divider, The other end of the output filter capacitor C19 is connected to the other end of the load resistor RL 2.

In a missile-borne secondary power supply multi-output time sequence control method, input Vin enters an input reverse connection protection and EMI filtering circuit to filter input common-mode signals and differential-mode signals while realizing a reverse connection protection function. The EMI filter circuit filters out external electromagnetic interference introduced on the incoming line on one hand, and inhibits the high-frequency signal circuit from emitting electromagnetic interference to the outside on the other hand, so that normal work of other electronic equipment under the same electromagnetic environment is not influenced. The input Vin firstly enters an input reverse connection protection and EMI filter circuit, the transient voltage suppression diode D1 and the transient voltage suppression diode D2 can suppress input transient interference voltage in the forward direction and the reverse direction, when the input Vin is reversely accessed, the transient voltage suppression diode D2 is reversely biased to be cut off, the N-channel field effect transistor S1 is cut off, and when the input Vin is forwardly accessed, the ideal diode controller U1 drives the N-channel field effect transistor S1 to be switched on, so that the input reverse connection protection function is realized. The input Vin enters an EMI filter circuit to carry out input common-mode signal and differential-mode signal filtering, wherein a common-mode inductor L1, a differential-mode capacitor C2 and a differential-mode capacitor C3 form a first-stage common-mode and differential-mode signal filter circuit, and a differential-mode inductor L2, a common-mode capacitor C4 and a common-mode capacitor C5 form a second-stage common-mode and differential-mode signal filter circuit. The EMI filter circuit filters out external electromagnetic interference introduced on the incoming line on one hand, and inhibits the high-frequency signal circuit from emitting electromagnetic interference to the outside on the other hand, so that normal work of other electronic equipment under the same electromagnetic environment is not influenced. The input Vin is output Va after passing through the input reverse connection protection and EMI filter circuit, and is respectively sent into the power-down maintaining and pre-voltage stabilizing circuit and the multi-path isolation output time sequence control circuit.

The input reverse connection protection and EMI filter circuit outputs Va to enter a power-down maintaining and pre-voltage stabilizing circuit, input voltage Va firstly charges an energy storage capacitor C6 and an energy storage capacitor C7 through a current limiting resistor R2 and a current limiting resistor R3 in the power-down maintaining circuit, and due to the effect of the front end reverse connection protection circuit, the energy storage capacitor C6 and the energy storage capacitor C7 can supply power to a rear end circuit through a rectifier diode D4 when input Va is in power-down to achieve the power-down maintaining function. The input voltage Va simultaneously enters the pre-voltage stabilizing circuit, and the synchronous switch buck-boost controller U2 realizes the wide-range input pre-voltage stabilizing function through controlling the conduction or the cut-off of the N-channel field effect transistor S2, the N-channel field effect transistor S3, the N-channel field effect transistor S4 and the N-channel field effect transistor S5. Synchronous switch buck-boost controller U2 realizes the undervoltage protection function through divider resistance R4 and divider resistance R5, realizes electric current and voltage closed loop feedback through current sampling resistance R6 and divider sampling resistance R7, divider sampling resistance R8, can accomplish switch steady voltage adjustment output Vb fast and accurately.

The output Vb of the power-down maintaining and pre-stabilizing circuit enters a DC push-pull isolation conversion rectifying circuit, a pulse width modulation push-pull controller U3 controls the alternating conduction or cut-off of an N-channel field effect tube S6 and an N-channel field effect tube S7 to perform isolation conversion on the input voltage Vb through a high-frequency switch transformer T1 and output multi-path isolation secondary voltage after rectification and filtering, wherein the output of a secondary winding Ns1 of the high-frequency switch transformer T1 is rectified by a rectifier diode D5 and a rectifier diode D6 and then is subjected to LC filtering by a filter inductor L3 and a filter capacitor C10 to output Vc1, the output of a secondary winding Ns2 of the high-frequency switch transformer T1 is rectified by a rectifier diode D7 and a rectifier diode D8 and then is subjected to LC filtering by a filter inductor L4 and a filter capacitor C11 to output Vc2, the output of a secondary winding Ns3 of the high-frequency switch transformer T1 is rectified by a rectifier diode D9 and a rectifier diode D10 and then is subjected to be rectified by a filter inductor L5 and filter capacitor C12 to output Vc3, the output secondary voltage Vc1, the output secondary voltage Vc2, and the output secondary voltage Vc3 are isolated from each other. The output voltage Vc1 is sent to the secondary stabilized filter output circuit, and the output voltage Vc2 and the output voltage Vc3 are respectively sent to the multi-path isolated output sequential control circuit and the secondary stabilized filter output circuit at the same time.

In the multi-path isolation output timing control circuit, a reference end Ref of a high-precision voltage reference source V1 samples an input voltage Va through a voltage dividing and current limiting resistor R9, a voltage dividing and current limiting resistor R10 and a voltage dividing and current limiting resistor R11, and is charged in a time-delay manner through an energy storage time-delay capacitor C13 and an energy storage time-delay capacitor C14, when the reference end Ref voltage of the high-precision voltage reference source V1 is less than a set value, an output cathode C end of the high-precision voltage reference source V1 is at a high level, an input end of a photoelectric coupler B1 is conducted, an output Vd1 and an output Vd2 are pulled to a low level through saturation conduction of an output end of the photoelectric coupler, when the reference end Ref voltage of the high-precision voltage reference source V1 reaches the set value, an output cathode C end of the high-precision voltage reference source V1 is at a low level, at the moment, an input end of a voltage stabilizing diode D11 and an input end of a photoelectric coupler B1 are cut off, an output end of the photoelectric coupler B1 is further cut off, and an output Vd1 is pulled up to a current limiting voltage Vc2 after passing through a voltage dividing and current limiting resistor R14 and a voltage dividing and a voltage limiting resistor R15, the output Vd2 is divided by the voltage dividing and current limiting resistor R16 and the voltage dividing and current limiting resistor R17 and then pulled up to the input voltage Vc 3.

In the two-stage voltage-stabilizing filtering output circuit, an input voltage Vc1 is subjected to voltage-stabilizing filtering by a low-dropout regulator U4 and then outputs Vout1, an input voltage Vc2 is subjected to voltage-stabilizing filtering by a low-dropout regulator U5 and then outputs Vout2, and an input voltage Vc3 is subjected to voltage-stabilizing filtering by a low-dropout regulator U6 and then outputs Vout 3. The EN terminal of the low dropout regulator U4 is directly pulled up to the IN off, when the input voltage Vc1 is active, the output Vout1 is active, the EN terminal of the low dropout regulator U5 is controlled by the input voltage Vd1, when and only when the input voltage Vc2 and the input voltage Vd1 are active simultaneously, the output Vout2 is active, and similarly, the EN terminal of the low dropout regulator U6 is controlled by the input voltage Vd2, when and only when the input voltage Vc3 and the input voltage Vd2 are active simultaneously, the output Vout3 is active.

When a secondary power supply of the missile-borne computer is powered on, an input voltage Vin outputs a voltage Va after being input into the reverse connection protection and EMI filter circuit, when the input voltage Va rises from zero voltage to a voltage set value which is larger than the under-voltage protection voltage of the power-down maintaining and voltage pre-stabilizing circuit, the output voltage Vb of the voltage pre-stabilizing circuit is effective, enters the DC push-pull isolation conversion rectifying circuit, is rectified by push-pull isolation conversion, and then outputs 3 paths of isolation secondary voltage Vc1, secondary voltage Vc2 and secondary voltage Vc 3. The output voltage Vc1 is regulated by a low dropout regulator U4 of a secondary voltage-stabilizing filtering output circuit and then outputs Vout1, the output Vout1 is electrified to be completed, at the moment, the Ref end voltage of a high-precision voltage reference source V1 in the multi-path isolation output sequential control circuit is smaller than a set value, the output cathode C end of the high-precision voltage reference source V1 is at a high level, the input end of a photoelectric coupler B1 is conducted, the output Vd1 and the output Vd2 are at a low level, and the output of the low dropout regulator U5 and the output of the low dropout regulator U6 in the secondary voltage-stabilizing filtering output circuit are forbidden; with the continuous rising of the input voltage Va, when the Ref terminal voltage of the high-precision voltage reference source V1 in the multi-path isolation output timing control circuit is charged to a set value through RC delay, the output cathode C of the high-precision voltage reference source V1 outputs a low level, the zener diode D11 is cut off, the input end of the photoelectric coupler B1 is cut off, the output Vd1 is a high level, the output Vout2 of the low dropout regulator U5 of the secondary voltage stabilizing and filtering output circuit is valid, similarly, the output Vd2 is a high level, the output Vout3 of the low dropout regulator U6 of the secondary voltage stabilizing and filtering output circuit is valid, at this time, the power-on of the output Vout2 and the output Vout3 is completed, and the power-on function of the output Vout1 leading output Vout2 and the output Vout3 is realized. As the input voltage Va continues to rise to the nominal voltage, the voltages on the energy storage capacitor C6 and the energy storage capacitor C7 also charge from Va to the nominal voltage through the current limiting resistor R2 and the current limiting resistor R3.

When the secondary power supply of the missile-borne computer is powered off, the input voltage Va begins to drop from the rated voltage, and due to the effect of the reverse connection protection circuit at the front end, the energy of the energy storage capacitor C6 and the energy storage capacitor C7 begins to discharge from the rated voltage to the rear end circuit through the branch of the rectifier diode D4, so that the rear end circuit is ensured to normally work within a certain time (dozens of mS). With the continuous drop of the input voltage Va, when the Ref terminal voltage of the high-precision voltage reference source V1 in the multi-path isolation output timing control circuit is smaller than the set value, the output cathode C of the high-precision voltage reference source V1 outputs high level, the input terminal of the photocoupler B1 is turned on, the output Vd1 and the output Vd2 are low level, the outputs of the low dropout regulator U5 and the low dropout regulator U6 of the two-stage voltage stabilizing and filtering output circuit are disabled, the power-down of the output Vout2 and the output Vout3 is completed, and when the loads of the output Vout2 and the output Vout3 are capacitive light loads, the power-down can be accelerated by adding the load resistor RL1 and the load resistor RL 2. At this time, because the output of the power-down maintaining and wide-range pre-voltage stabilizing circuit is normal, the output Vout1 is still valid, when the voltages of the energy storage capacitor C6 and the energy storage capacitor C7 are discharged to be less than the set value of the under-voltage protection voltage of the power-down maintaining and pre-voltage stabilizing circuit, the output voltage Vb of the pre-voltage stabilizing circuit is forbidden, further, the output Vc1 of the DC push-pull isolation conversion rectifying circuit is forbidden, the output of the low dropout regulator U4 in the secondary voltage stabilizing filter output circuit is forbidden, at this time, the power-down of the output Vout1 is completed, and thus the power-down function of the output Vout1 lagging the output Vout2 and the output Vout3 is realized.

The specific implementation mode is as follows:

a missile-borne secondary power supply multi-output time sequence control method is applied to a circuit comprising an input reverse connection protection and EMI filter circuit, a power failure holding and pre-voltage stabilizing circuit, a DC push-pull isolation conversion rectifying circuit, a multi-output isolation time sequence control circuit and a secondary voltage stabilizing filter output circuit. Wherein, input protection and EMI filter circuit of joining conversely includes: the circuit comprises a transient voltage suppression diode D1, a transient voltage suppression diode D2, an ideal diode controller U1, a voltage stabilizing diode D3, an N-channel field effect transistor S1, a current limiting resistor R1, a filter capacitor C1, a common mode inductor L1, a differential mode capacitor C2, a differential mode capacitor C3, a differential mode inductor L2, a common mode capacitor C4 and a common mode capacitor C5. The power down holding and pre-voltage stabilizing circuit comprises: the current-limiting resistor R2, the current-limiting resistor R3, an energy-storing capacitor C6, an energy-storing capacitor C7, a rectifier diode D4, a synchronous switch buck-boost controller U2, an N-channel field effect transistor S2, an N-channel field effect transistor S3, an N-channel field effect transistor S4, an N-channel field effect transistor S5, an energy-storing inductor L2, a voltage-dividing resistor R4, a voltage-dividing resistor R5, a filter capacitor C8, a current sampling resistor R6, a voltage-dividing sampling resistor R7, a voltage-dividing sampling resistor R8 and a filter capacitor C9. DC push-pull isolation conversion rectifying circuit, including: the pulse width modulation push-pull controller comprises a pulse width modulation push-pull controller U3, an N-channel field effect transistor S6, an N-channel field effect transistor S7, a high-frequency switching transformer T1, a rectifier diode D5, a rectifier diode D6, a rectifier diode D7, a rectifier diode D8, a rectifier diode D9, a rectifier diode D10, a filter inductor L3, a filter inductor L4, a filter inductor L5, a filter capacitor C10, a filter capacitor C11 and a filter capacitor C12. The isolated output sequential control circuit of the multipath includes: the high-precision voltage reference source V1, a photoelectric coupler B1, a voltage division current limiting resistor R9, a voltage division current limiting resistor R10, a voltage division current limiting resistor R11, an energy storage delay capacitor C13, an energy storage delay capacitor C14, a current limiting resistor R12, a current limiting resistor R13, a voltage stabilizing diode D11, a voltage division current limiting resistor R14, a voltage division current limiting resistor R15, a voltage division current limiting resistor R16, a voltage division current limiting resistor R17, a filter capacitor C15 and a filter capacitor C16. Two-stage voltage-stabilizing filter output circuit includes: the low dropout regulator U4, the low dropout regulator U5, the low dropout regulator U6, partial pressure sampling resistance R18, partial pressure sampling resistance R19, partial pressure sampling resistance R20, partial pressure sampling resistance R21, partial pressure sampling resistance R22, partial pressure sampling resistance R23, output filter capacitor C17, output filter capacitor C18, output filter capacitor C19, load resistance RL1, load resistance RL 2.

The output end of the input reverse connection protection and EMI filter circuit is connected with the input end of the power-down maintaining and pre-voltage stabilizing circuit and the input end of the multi-path isolation output time sequence control circuit, the output end of the power-down maintaining and pre-voltage stabilizing circuit is connected with the input end of the DC push-pull isolation conversion rectifying circuit, the output end of the DC push-pull isolation conversion rectifying circuit is connected with the input end of the multi-path isolation output time sequence control circuit and the input end of the secondary voltage stabilizing filter output circuit, and the output end of the multi-path isolation output time sequence control circuit is connected with the input end of the secondary voltage stabilizing filter output circuit.

In the power-down holding and pre-stabilizing circuit, an input high-end Va is respectively connected with one end of a current-limiting resistor R2, one end of a current-limiting resistor R3, a cathode of a rectifier diode D4, one end of a voltage-dividing resistor R4, one end of a filter capacitor C8 and a drain electrode of an N-channel field-effect tube S2, the other end of the current-limiting resistor R2 is respectively connected with the other end of the current-limiting resistor R3, an anode of the rectifier diode D4, a positive end of an energy-storing capacitor C6 and a positive end of an energy-storing capacitor C7, the other end of the voltage-dividing resistor R4 is respectively connected with an RUN end of a synchronous switch buck-boost controller U2 and one end of the voltage-dividing resistor R5, the other end of the voltage-dividing resistor R5 is respectively connected with a negative end of the energy-storing capacitor C6, a negative end of the energy-storing capacitor C7, the other end of the filter capacitor C8 and a signal ground, a source electrode of the N-channel field-effect tube S2 is respectively connected with one end of an energy-storing inductor L2 and a drain electrode of an N-channel field-effect tube S4, and the other end of an energy-storing inductor L2 is respectively connected with a source electrode S3, The drain electrode of an N-channel field effect tube S5 is connected, the source electrode of the N-channel field effect tube S4 is respectively connected with the source electrode of the N-channel field effect tube S5, one end of a current sampling resistor R6 and the ISENSE + end of a synchronous switch buck-boost controller U2, the other end of the current sampling resistor R6 is respectively connected with the ISENSE-end of the synchronous switch buck-boost controller U2, the GND end of the synchronous switch buck-boost controller U2 and the signal ground, the grid electrode of the N-channel field effect tube S2 is connected with the TG1 end of the synchronous switch buck-boost controller U2, the grid electrode of the N-channel field effect tube S4 is connected with the BG1 end of the synchronous switch buck-boost controller U2, the grid electrode 7 4 of the N-channel field effect tube S3 is connected with the TG2 end of the synchronous switch buck-boost controller U2, the grid electrode of the N-channel field effect tube S5 is connected with the BG2 end of the synchronous switch buck controller U2, the drain electrode of the N-channel field effect tube S3 is respectively connected with the BG 588 end of the sampling resistor R8, One end of the filter capacitor C9 is connected with the output high end Vb, the other end of the voltage division sampling resistor R7 is connected with the VSENSE end of the synchronous switch buck-boost controller U2 and one end of the voltage division sampling resistor R8, and the other end of the voltage division sampling resistor R8 is connected with the other end of the filter capacitor C9 and the signal ground.

In the DC push-pull isolation conversion rectifying circuit, an input high end Vb is respectively connected with a VCC end of a pulse width modulation push-pull controller U3 and a 2 end of a primary winding Np1 of a high-frequency switching transformer T1, a 1 end of the primary winding Np1 of the high-frequency switching transformer T1 is connected with a drain electrode of an N-channel field effect transistor S6, a 3 end of the primary winding Np1 of the high-frequency switching transformer T1 is connected with a drain electrode of the N-channel field effect transistor S7, and a source electrode of the N-channel field effect transistor S6 is respectively connected with a source electrode of the N-channel field effect transistor S7, a GND end of the pulse width modulation push-pull controller U3 and a signal ground. The grid of the N-channel field effect transistor S6 is connected with the PWM1 end of the pulse width modulation push-pull controller U3, the grid of the N-channel field effect transistor S7 is connected with the PWM2 end of the pulse width modulation push-pull controller U3, the 4 end of the secondary winding Ns1 of the high-frequency switching transformer T1 is connected with the anode of the rectifier diode D5, the cathode of the rectifier diode D5 is respectively connected with the cathode of the rectifier diode D6 and one end of the filter inductor L3, the anode of the rectifier diode D6 is connected with the 6 end of the secondary winding Ns1 of the high-frequency switching transformer T1, the other end of the filter inductor L3 is respectively connected with one end of the filter capacitor C10 and the output positive terminal Vc1+, the other end of the filter capacitor C10 is respectively connected with the 5 end of the secondary winding Ns 10 and the output negative terminal Vc 10-of the high-frequency switching transformer T10, the 7 end of the secondary winding 10 of the high-frequency switching transformer T10 is respectively connected with the anode of the rectifier diode D10, and the cathode of the rectifier diode D10, One end of a filter inductor L4 is connected, the anode of a rectifier diode D8 is connected with the 9 end of a secondary winding Ns2 of a high-frequency switch transformer T1, the other end of the filter inductor L4 is respectively connected with one end of a filter capacitor C11 and an output positive end Vc2+, the other end of a filter capacitor C11 is respectively connected with the 8 end and the output negative end Vc 2-of a secondary winding Ns2 of the high-frequency switch transformer T1, the 10 end of a secondary winding Ns3 of the high-frequency switch transformer T1 is connected with the anode of a rectifier diode D9, the cathode of a rectifier diode D9 is respectively connected with the cathode of a rectifier diode D10 and one end of a filter inductor L5, the anode of a rectifier diode D10 is connected with the 12 end of a secondary winding Ns3 of a high-frequency switch transformer T1, the other end of a filter inductor L5 is respectively connected with one end and the output positive end 3+ of a filter capacitor C12, and the other end of a Vc filter capacitor C12 is respectively connected with the secondary winding Ns 4611 end of a secondary winding T3 of the high-frequency switch transformer T1, The output negative terminal Vc 3-is connected.

In the method, an input Vin firstly enters an input reverse connection protection and EMI filter circuit, a transient voltage suppression diode D1 and a transient voltage suppression diode D2 can suppress forward and reverse input transient interference voltages, when the input Vin is reversely connected, a transient voltage suppression diode D2 is reversely biased to be cut off, an N-channel field effect transistor S1 is cut off, and when the input Vin is forwardly connected, an ideal diode controller U1 drives an N-channel field effect transistor S1 to be connected, so that the input reverse connection protection function is realized. The input Vin enters an EMI filter circuit to filter input common-mode signals and differential-mode signals, wherein a common-mode inductor L1, a differential-mode capacitor C2 and a differential-mode capacitor C3 form a first-stage common-mode and differential-mode signal filter circuit, and a differential-mode inductor L2, a common-mode capacitor C4 and a common-mode capacitor C5 form a second-stage common-mode and differential-mode signal filter circuit. The EMI filter circuit filters out external electromagnetic interference introduced on the incoming line on one hand, and inhibits the high-frequency signal circuit from emitting electromagnetic interference to the outside on the other hand, so that normal work of other electronic equipment under the same electromagnetic environment is not influenced. The input Vin is output Va after passing through the input reverse connection protection and EMI filter circuit, and is respectively sent into the power-down maintaining and pre-voltage stabilizing circuit and the multi-path isolation output time sequence control circuit.

In the power-down maintaining and pre-stabilizing circuit, an input voltage Va firstly charges an energy storage capacitor C6 and an energy storage capacitor C7 through a current-limiting resistor R2 and a current-limiting resistor R3 in a power-down maintaining circuit, and due to the effect of a front end reverse connection protection circuit, the energy storage capacitor C6 and the energy storage capacitor C7 can supply power to a rear end circuit through a rectifier diode D4 when the input Va is in power-down to realize the power-down maintaining function. The input voltage Va simultaneously enters the pre-voltage stabilizing circuit, and the synchronous switch buck-boost controller U2 realizes the wide-range input pre-voltage stabilizing function through controlling the conduction or the cut-off of the N-channel field effect transistor S2, the N-channel field effect transistor S3, the N-channel field effect transistor S4 and the N-channel field effect transistor S5. Synchronous switch buck-boost controller U2 realizes the undervoltage protection function through divider resistance R4 and divider resistance R5, realizes electric current and voltage closed loop feedback through current sampling resistance R6 and divider sampling resistance R7, divider sampling resistance R8, can accomplish switch steady voltage adjustment output Vb fast and accurately.

In the DC push-pull isolation conversion rectifying circuit, the PWM push-pull controller U3 controls the alternate on or off of the N-channel fet S6 and the N-channel fet S7 through the PWM1 signal and the PWM2 signal respectively, so that the input voltage Vb is isolated and converted by the high-frequency switching transformer T1, and then outputs a multi-path isolated secondary voltage after rectification and filtering, the winding of the high-frequency switching transformer T1 includes 1 primary winding Np1 and 3 secondary windings Ns1, Ns2 and Ns3, the 1 end of the primary winding Np1, the 2 end of the primary winding Np1, the 4 end of the secondary winding Ns1, the 5 end of the secondary winding Ns1, the 7 end of the secondary winding 2, the 8 end of the secondary winding Ns2, the 10 end of the secondary winding Ns3, and the 11 end of the secondary winding Ns3 are named ends. The output of the secondary winding Ns1 of the high-frequency switching transformer T1 is rectified by a rectifier diode D5 and a rectifier diode D6, and then LC filtering is completed by a filter inductor L3 and a filter capacitor C10, and then Vc1 is output, the output of the secondary winding Ns2 of the high-frequency switching transformer T1 is rectified by a rectifier diode D7 and a rectifier diode D8, and then LC filtering is completed by a filter inductor L4 and a filter capacitor C11, and then Vc2 is output, the output of the secondary winding Ns3 of the high-frequency switching transformer T1 is rectified by a rectifier diode D9 and a rectifier diode D10, and then LC filtering is completed by a filter inductor L5 and a filter capacitor C12, and then Vc3 is output, and the output of the secondary voltage Vc1, the output of the secondary voltage Vc2 and the output of the secondary voltage Vc3 are isolated from each other. The output voltage Vc1 is sent to the secondary stabilized filter output circuit, and the output voltage Vc2 and the output voltage Vc3 are respectively sent to the multi-path isolated output sequential control circuit and the secondary stabilized filter output circuit at the same time.

In the multi-path isolation output time sequence control circuit, a reference end Ref of a high-precision voltage reference source V1 samples an input voltage Va through a voltage division current-limiting resistor R9, a voltage division current-limiting resistor R10 and a voltage division current-limiting resistor R11, and is charged in a time-delay manner through an energy storage time-delay capacitor C13 and an energy storage time-delay capacitor C14, when the voltage of the reference terminal Ref of the high-precision voltage reference source V1 is less than a set value, the output cathode C end of the high-precision voltage reference source V1 is at a high level, the input end of a photoelectric coupler B1 is conducted at the moment, an output Vd1 and an output Vd2 are conducted to be pulled to a low level through the saturation of the output end of the photoelectric coupler, when the voltage of the reference end Ref of the high-precision voltage reference source V1 reaches a set value, the output cathode C of the high-precision voltage reference source V1 outputs a low level, the input end of the photoelectric coupler B1 is cut off, the output Vd1 is pulled up to a high level through the voltage-dividing current-limiting resistor R14 and the voltage-dividing current-limiting resistor R15, and the output Vd2 is pulled up to a high level through the voltage-dividing current-limiting resistor R16 and the voltage-dividing current-limiting resistor R17.

When a secondary power supply of the missile-borne computer is electrified, an input voltage Vin outputs a voltage Va after being input into the reverse connection protection and EMI filter circuit, when the input voltage Va rises from zero voltage to a voltage set value (for example, 12V) which is greater than the under-voltage protection voltage of the power-down maintaining and pre-stabilizing circuit, the output voltage Vb of the power-down maintaining and pre-stabilizing circuit is effective, and the output voltage Vb enters the DC push-pull isolation conversion rectifying circuit, is rectified by push-pull isolation conversion and outputs 3 paths of isolation secondary voltage Vc1, secondary voltage Vc2 and secondary voltage Vc 3. The output voltage Vc1 is regulated by a low dropout regulator U4 of a secondary voltage-stabilizing filtering output circuit and then outputs Vout1, the electrification of the output Vout1 is completed, at the moment, the Ref terminal voltage of a high-precision voltage reference source V1 in a multi-path isolation output timing sequence control circuit is smaller than a set value (for example, 2.5V), the output cathode C end of the high-precision voltage reference source V1 is at a high level, the input end of a photoelectric coupler B1 is conducted, the output Vd1 and the output Vd2 are at a low level, and the output of the low dropout regulator U5 and the output of the low dropout regulator U6 of the secondary voltage-stabilizing filtering output circuit are forbidden; with the continuous rising of the input voltage Va, when the Ref terminal voltage of the high-precision voltage reference source V1 in the multi-path isolation output timing control circuit is charged to a set value (e.g., 2.5V) through RC delay, the output cathode C of the high-precision voltage reference source V1 outputs a low level (less than 2V), the zener diode D11 (e.g., 3.5V) is turned off, the input terminal of the photocoupler B1 is turned off, the output Vd1 is a high level, the output Vout2 of the low dropout regulator U5 of the secondary regulator filter output circuit is valid, and similarly, the output Vd2 is a high level, the output Vout3 of the low dropout regulator U6 of the secondary regulator filter output circuit is valid, and at this time, the power-up of the output Vout2 and the output Vout3 is completed, so as to implement the power-up function of the output Vout1 leading the output Vout2 and the output Vout 3. As the input voltage Va continues to rise to the nominal voltage (e.g., 28V), the voltages on the storage capacitor C6 and the storage capacitor C7 also charge from Va to the nominal voltage via the current limiting resistor R2 and the current limiting resistor R3.

When the secondary power supply of the missile-borne computer is powered off, the input voltage Va starts to drop from the rated voltage (for example, 28V), and due to the action of a front-end reverse connection protection circuit, the energy of the energy storage capacitor C6 and the energy storage capacitor C7 starts to discharge from the rated voltage (28V) to the rear-end circuit through a branch circuit of the rectifier diode D4, so that the rear-end circuit is ensured to normally work within a certain time (dozens of mS). With the continuous drop of the input voltage Va, when the Ref terminal voltage of the high-precision voltage reference source V1 in the multi-path isolation output timing control circuit is smaller than the set value (e.g. 2.5V), the output cathode C of the high-precision voltage reference source V1 outputs high level, the input terminal of the photocoupler B1 is turned on, the output Vd1 and the output Vd2 are low level, the outputs of the low dropout regulator U5 and the low dropout regulator U6 of the two-stage voltage stabilizing and filtering output circuit are disabled, the power down of the output Vout2 and the output Vout3 is completed, and when the loads of the output Vout2 and the output Vout3 are capacitive light loads, the power down can be accelerated by increasing the load resistor RL1 and the load resistor RL 2. At this time, the output Vb of the power-down maintaining and wide-range pre-voltage stabilizing circuit is normal, so that the output Vc1 of the DC push-pull isolating converting rectifying circuit is also normal, and therefore the output Vout1 is still valid, when the voltages of the energy storage capacitor C6 and the energy storage capacitor C7 are discharged to a voltage set value (for example, 12V) smaller than the under-voltage protection voltage of the power-down maintaining and pre-voltage stabilizing circuit, the output voltage Vb of the power-down maintaining and wide-range pre-voltage stabilizing circuit is prohibited, further the output Vc1 of the DC push-pull isolating converting rectifying circuit is prohibited, the output of the low dropout regulator U4 in the secondary voltage stabilizing filter output circuit is prohibited, and at this time, the power-down of the output Vout1 is completed, so that the electric function of the output Vout1 lagging the output Vout2 and the output Vout3 is realized.

The invention adopts the multi-path isolation output time sequence control circuit and the secondary voltage stabilization filter output circuit to realize the power-on time sequence control function of multi-path isolation output of the missile-borne secondary power supply, further realizes the power-off time sequence control function of the multi-path isolation output through the power-down maintaining and voltage pre-stabilizing circuit, and has the characteristics of small load characteristic influence, high control precision and stability, flexible time sequence adjustment, controllable power-off time sequence, capability of realizing leading power-on and lagging power-off of certain output circuit and the like.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims

1. A missile-borne secondary power supply multi-path output time sequence control method is characterized in that a time sequence control circuit comprises an input reverse connection protection and EMI filter circuit, a power failure holding and pre-voltage stabilizing circuit, a DC push-pull isolation conversion rectifying circuit, a multi-path isolation output time sequence control circuit and a circuit of a secondary voltage stabilizing filter output circuit; the secondary voltage-stabilizing filter output circuit comprises a secondary voltage-stabilizing filter output circuit a, a secondary voltage-stabilizing filter output circuit b and a secondary voltage-stabilizing filter output circuit c;

when a secondary power supply of the missile-borne computer is electrified, an input voltage Vin outputs a voltage Va after being input into a reverse connection protection and EMI filter circuit, the voltage Va inputs a power-down maintaining and pre-stabilizing circuit and a multi-path isolation output time sequence control circuit, when the voltage Va rises from zero voltage to a value larger than the under-voltage protection voltage set value of the power-down maintaining and pre-stabilizing circuit, the output voltage Vb of the power-down maintaining and pre-stabilizing circuit is effective, the output voltage Vb enters a DC push-pull isolation conversion rectification circuit and is output into a secondary voltage Vc1, a secondary voltage Vc2 and a secondary voltage Vc3 after being subjected to push-pull isolation conversion rectification by a push-pull isolation conversion rectification circuit, the secondary voltage Vc1, the secondary voltage Vc2 and the secondary voltage Vc3 are respectively input into a secondary voltage stabilizing filter output circuit a, a secondary voltage stabilizing filter output circuit b and a secondary voltage stabilizing filter output circuit c, the secondary voltage Vc2 and the secondary voltage Vc3 are input into the multi-path isolation output time sequence control circuit, the multi-path isolation output timing control circuit outputs Vd1 and Vd2 to a secondary voltage-stabilizing filter output circuit b and a secondary voltage-stabilizing filter output circuit c; the output voltage Vc1 is regulated by a secondary voltage-stabilizing filter output circuit a to output Vout1, and the output Vout1 is electrified; at the moment, an output Vd1 and an output Vd2 in the multi-path isolation output timing control circuit are low level, and the outputs of the secondary voltage stabilizing filter output circuit b and the secondary voltage stabilizing filter output circuit c are forbidden; along with the continuous rising of the input voltage Va, the output Vd1 of the multi-path isolation output timing control circuit is at a high level, the output Vout2 of the secondary voltage-stabilizing filter output circuit is effective, the output Vd2 of the multi-path isolation output timing control circuit is at a high level, the Vout3 of the secondary voltage-stabilizing filter output circuit is effective, at the moment, the power-on of the output Vout2 and the output Vout3 is completed, and the power-on functions of the output Vout1 leading the output Vout2 and the output Vout3 are realized;

2. The method as claimed IN claim 1, wherein IN the input reverse connection protection and EMI filter circuit, the cathode of the transient voltage suppressor diode D1 is connected to the input high-side Vin +, the IN terminal of the ideal diode controller U1 is connected to the input high-side Vin +, the SOURCE terminal of the ideal diode controller U1, the SOURCE of the N-channel FET S1, and the anode of the zener diode D3, the GATE of the N-channel FET S1 is connected to the cathode of the zener diode D3 and the GATE terminal of the ideal diode controller U1, the drain of the N-channel FET S1 is connected to the OUT terminal of the ideal diode controller U1, the one terminal of the filter capacitor C1, the one terminal of the differential capacitor C2, and the input positive terminal of the common mode inductor L1, the anode of the transient voltage suppressor diode D1 is connected to the anode of the transient voltage suppressor diode D2, the cathode of the transient voltage suppression diode D2 is connected with the VSS end of an ideal diode controller U1, one end of a current-limiting resistor R1 and the other end of a filter capacitor C1 respectively, the input negative end of a common mode inductor L1 is connected with the other end of a differential mode capacitor C2, the other end of the current-limiting resistor R1 and the input ground Vin-, the output positive end of the common mode inductor L1 is connected with one end of a differential mode inductor L2 and one end of a differential mode capacitor C3 respectively, the other end of the differential mode inductor L2 is connected with one end of a common mode capacitor C4 and the output high end Va respectively, the other end of the common mode capacitor C4 is connected with one end of the common mode capacitor C5 and the chassis ground respectively, and the other end of the common mode capacitor C5 is connected with the output negative end of the common mode inductor L1, the other end of the differential mode capacitor C3 and the signal ground respectively;

the input Vin enters an input reverse connection protection and EMI filtering circuit to filter an input common-mode signal and a differential-mode signal while realizing a reverse connection protection function; the EMI filter circuit filters external electromagnetic interference introduced on the incoming line on one hand, and inhibits the high-frequency signal circuit from emitting electromagnetic interference to the outside on the other hand, so as to avoid influencing the normal work of other electronic equipment in the same electromagnetic environment; the input Vin firstly enters an input reverse connection protection and EMI filter circuit, a transient voltage suppression diode D1 and a transient voltage suppression diode D2 can suppress input transient interference voltage in the forward direction and the reverse direction, when the input Vin is reversely accessed, a transient voltage suppression diode D2 is reversely biased to be cut off, an N-channel field effect transistor S1 is cut off, and when the input Vin is forwardly accessed, an ideal diode controller U1 drives an N-channel field effect transistor S1 to be switched on, so that the input reverse connection protection function is realized; the input Vin enters an EMI filter circuit to carry out input common-mode signal and differential-mode signal filtering, wherein a common-mode inductor L1, a differential-mode capacitor C2 and a differential-mode capacitor C3 form a first-stage common-mode and differential-mode signal filter circuit, and a differential-mode inductor L2, a common-mode capacitor C4 and a common-mode capacitor C5 form a second-stage common-mode and differential-mode signal filter circuit.

3. The method as claimed in claim 2, wherein in the power-down maintaining and pre-stabilizing circuit, the input high end Va is connected to one end of a current-limiting resistor R2, one end of a current-limiting resistor R3, the cathode of a rectifying diode D4, one end of a voltage-dividing resistor R4, one end of a filter capacitor C8, and the drain of an N-channel fet S2, the other end of the current-limiting resistor R2 is connected to the other end of a current-limiting resistor R3, the anode of a rectifying diode D4, the positive end of an energy-storage capacitor C6, and the positive end of an energy-storage capacitor C7, the other end of the voltage-dividing resistor R4 is connected to the RUN end of a synchronous switch buck-boost controller U2 and one end of a voltage-dividing resistor R5, the other end of the voltage-dividing resistor R5 is connected to the negative end of an energy-storage capacitor C6, the energy-storage capacitor C7, the other end of the filter capacitor C8, and the signal ground, and the source of the N-channel fet S2 is connected to one end of an energy-storage inductor L2 The drain of an N-channel field effect tube S4 is connected, the other end of an energy storage inductor L2 is respectively connected with the source of an N-channel field effect tube S3 and the drain of an N-channel field effect tube S5, the source of the N-channel field effect tube S4 is respectively connected with the source of an N-channel field effect tube S5, one end of a current sampling resistor R6 and the ISENSE + end of a synchronous switch buck-boost controller U2, the other end of the current sampling resistor R6 is respectively connected with the ISENSE-end of a synchronous switch buck-boost controller U2, the GND end of a synchronous switch buck-boost controller U2 and signal ground, the gate of the N-channel field effect tube S2 is connected with the TG1 end of a synchronous switch buck-boost controller U2, the gate of the N-channel field effect tube S4 is connected with the BG1 end of a synchronous switch buck-boost controller U2, the gate of the N-channel field effect tube S3 is connected with the TG 52 end of a synchronous switch buck-boost controller U2, the BG 9358 is connected with the synchronous switch buck controller U2, the drain electrode of the N-channel field effect transistor S3 is respectively connected with one end of a voltage division sampling resistor R7, one end of a filter capacitor C9 and an output high end Vb, the other end of the voltage division sampling resistor R7 is respectively connected with a VSENSE end of a synchronous switch buck-boost controller U2 and one end of a voltage division sampling resistor R8, and the other end of the voltage division sampling resistor R8 is respectively connected with the other end of the filter capacitor C9 and a signal ground;

the input reverse connection protection and EMI filter circuit outputs Va to enter a power-down holding and pre-voltage stabilizing circuit, the input voltage Va firstly charges an energy storage capacitor C6 and an energy storage capacitor C7 through a current-limiting resistor R2 and a current-limiting resistor R3 in the power-down holding circuit, and due to the effect of the front end reverse connection protection circuit, the energy storage capacitor C6 and the energy storage capacitor C7 can supply power to a rear end circuit through a rectifier diode D4 when the input Va is in power-down to realize the power-down holding function; the input voltage Va simultaneously enters the pre-voltage stabilizing circuit, and the synchronous switch buck-boost controller U2 realizes the wide-range input pre-voltage stabilizing function by controlling the conduction or the cut-off of the N-channel field effect transistor S2, the N-channel field effect transistor S3, the N-channel field effect transistor S4 and the N-channel field effect transistor S5; the synchronous switch buck-boost controller U2 realizes the undervoltage protection function through divider resistance R4 and divider resistance R5, realizes the current and voltage closed loop feedback through current sampling resistance R6 and divider sampling resistance R7, divider sampling resistance R8, can accomplish the switching steady voltage adjustment output Vb fast accurately.

4. The method for controlling the multi-output timing of the missile-borne secondary power supply according to claim 3, wherein in the DC push-pull isolation conversion rectifying circuit, an input high end Vb is respectively connected with a VCC end of a pulse width modulation push-pull controller U3 and a 2 end of a primary winding Np1 of a high-frequency switching transformer T1, a 1 end of a primary winding Np1 of the high-frequency switching transformer T1 is connected with a drain electrode of an N-channel field effect transistor S6, a 3 end of a primary winding Np1 of the high-frequency switching transformer T1 is connected with a drain electrode of the N-channel field effect transistor S7, and a source electrode of the N-channel field effect transistor S6 is respectively connected with a source electrode of the N-channel field effect transistor S7, a GND end of the pulse width modulation push-pull controller U3 and a signal ground; the grid of the N-channel field effect transistor S6 is connected with the PWM1 end of the pulse width modulation push-pull controller U3, the grid of the N-channel field effect transistor S7 is connected with the PWM2 end of the pulse width modulation push-pull controller U3, the 4 end of the secondary winding Ns1 of the high-frequency switching transformer T1 is connected with the anode of the rectifier diode D5, the cathode of the rectifier diode D5 is respectively connected with the cathode of the rectifier diode D6 and one end of the filter inductor L3, the anode of the rectifier diode D6 is connected with the 6 end of the secondary winding Ns1 of the high-frequency switching transformer T1, the other end of the filter inductor L3 is respectively connected with one end of the filter capacitor C10 and the output positive terminal Vc1+, the other end of the filter capacitor C10 is respectively connected with the 5 end of the secondary winding Ns 10 and the output negative terminal Vc 10-of the high-frequency switching transformer T10, the 7 end of the secondary winding 10 of the high-frequency switching transformer T10 is respectively connected with the anode of the rectifier diode D10, and the cathode of the rectifier diode D10, One end of a filter inductor L4 is connected, the anode of a rectifier diode D8 is connected with the 9 end of a secondary winding Ns2 of a high-frequency switch transformer T1, the other end of the filter inductor L4 is respectively connected with one end of a filter capacitor C11 and the output positive end Vc2+, the other end of a filter capacitor C11 is respectively connected with the 8 end and the output negative end Vc 2-of a secondary winding Ns2 of the high-frequency switch transformer T1, the 10 end of a secondary winding Ns3 of the high-frequency switch transformer T1 is connected with the anode of a rectifier diode D9, the cathode of a rectifier diode D9 is respectively connected with the cathode of the rectifier diode D10 and one end of a filter inductor L5, the anode of the rectifier diode D10 is connected with the 12 end of a secondary winding Ns3 of the high-frequency switch transformer T1, the other end of the filter inductor L5 is respectively connected with one end and the output positive end 3+ of a filter capacitor C12 and the other end of the filter capacitor C12 is respectively connected with the other end of a secondary winding Ns 3611 of a secondary winding transformer T3 of the high-frequency switch transformer T1, Output negative terminal Vc 3-connection;

the output Vb of the power-down maintaining and pre-stabilizing circuit enters a DC push-pull isolation conversion rectifying circuit, a pulse width modulation push-pull controller U3 controls the alternating conduction or cut-off of an N-channel field effect tube S6 and an N-channel field effect tube S7 to perform isolation conversion on the input voltage Vb through a high-frequency switch transformer T1 and output multi-path isolation secondary voltage after rectification and filtering, wherein the output of a secondary winding Ns1 of the high-frequency switch transformer T1 is rectified by a rectifier diode D5 and a rectifier diode D6 and then is subjected to LC filtering by a filter inductor L3 and a filter capacitor C10 to output Vc1, the output of a secondary winding Ns2 of the high-frequency switch transformer T1 is rectified by a rectifier diode D7 and a rectifier diode D8 and then is subjected to LC filtering by a filter inductor L4 and a filter capacitor C11 to output Vc2, the output of a secondary winding Ns3 of the high-frequency switch transformer T1 is rectified by a rectifier diode D9 and a rectifier diode D10 and then is subjected to be rectified by a filter inductor L5 and filter capacitor C12 to output Vc3, the output secondary voltage Vc1, the output secondary voltage Vc2 and the output secondary voltage Vc3 are isolated from each other; the output voltage Vc1 is sent to the secondary stabilized filter output circuit, and the output voltage Vc2 and the output voltage Vc3 are respectively sent to the multi-channel isolation output time sequence control circuit and the secondary stabilized filter output circuit at the same time.

5. The method for controlling the multi-output timing of a missile-borne secondary power supply according to claim 4, wherein in the multi-isolated output timing control circuit, the input high end Va is respectively connected with one end of a voltage dividing current-limiting resistor R9, one end of a current-limiting resistor R12 and one end of a current-limiting resistor R13, the other end of the voltage dividing current-limiting resistor R9 is connected with one end of a voltage dividing current-limiting resistor R10, the other end of the voltage dividing current-limiting resistor R10 is respectively connected with the Ref end of a high-precision voltage reference source V1, one end of the voltage dividing current-limiting resistor R11, one end of an energy-storage delay capacitor C13 and one end of an energy-storage delay capacitor C14, the other end of the voltage dividing current-limiting resistor R11 is respectively connected with the other end of an energy-storage delay capacitor C13, the other end of an energy-storage delay capacitor C14, the anode A end of the high-precision voltage reference source V1 and signal ground, the other end of the current-limiting resistor R12 is respectively connected with the other end of a current-limiting resistor R13, the cathode of a voltage-stabilizing diode D11, The cathode C end of a high-precision voltage reference source V1 is connected, the anode of a voltage-stabilizing diode D11 is respectively connected with the input end 1+ of a photoelectric coupler B1 and the input end 2+ of a photoelectric coupler B1, and the input end 1-of a photoelectric coupler B1 is respectively connected with the input end 2-of a photoelectric coupler B1 in a signal ground manner; an output end 1C of a photoelectric coupler B1 is respectively connected with one end of a voltage-dividing current-limiting resistor R14, one end of a voltage-dividing current-limiting resistor R15, one end of a filter capacitor C15 and an output high-end Vd1, the other end of a voltage-dividing current-limiting resistor R14 is connected with an input positive end Vc2+, an output end 1E of a photoelectric coupler B1 is respectively connected with the other end of a voltage-dividing current-limiting resistor R15, the other end of a filter capacitor C15 and an input negative end Vc2-, an output end 2C of a photoelectric coupler B1 is respectively connected with one end of a voltage-dividing current-limiting resistor R16, one end of a voltage-dividing current-limiting resistor R17, one end of a filter capacitor C16 and an output high-end Vd2, the other end of a voltage-dividing current-limiting resistor R16 is connected with an input positive end Vc3+, and an output end 2E of a photoelectric coupler B1 is respectively connected with the other end of a current-dividing current-limiting resistor R17, the other end of a filter capacitor C16 and an input negative end Vc 3-;

6. The method as claimed IN claim 5, wherein IN the secondary voltage-stabilizing filter output circuit, the input positive terminal Vc1+ is connected to the IN terminal of the low dropout regulator U4 and the EN terminal of the low dropout regulator U4, the OUT terminal of the low dropout regulator U4 is connected to one terminal of the voltage-dividing sampling resistor R18, one terminal of the output filter capacitor C17 and the output high terminal Vout1, the other terminal of the voltage-dividing sampling resistor R18 is connected to the ADJ terminal of the low dropout regulator U4 and one terminal of the voltage-dividing sampling resistor R19, the GND terminal of the low dropout regulator U4 is connected to the input negative terminal Vc1-, the other terminal of the voltage-dividing sampling resistor R19 and the other terminal of the output filter capacitor C17, the input positive terminal Vc2+ is connected to the IN terminal of the low dropout regulator U5, the input high terminal Vd1 is connected to the EN terminal of the low dropout regulator U5, and the OUT terminal of the low dropout regulator U5 is connected to one terminal of the voltage-dividing sampling resistor R20, One end of an output filter capacitor C18, one end of a load resistor RL1 and an output high-end Vout2 are connected, the other end of a voltage division sampling resistor R20 is respectively connected with an ADJ end of a low dropout regulator U5 and one end of a voltage division sampling resistor R21, the GND end of the low dropout regulator U5 is respectively connected with an input negative end Vc2-, the other end of a voltage division sampling resistor R21, the other end of an output filter capacitor C18 and the other end of a load resistor RL1, an input positive end Vc3+ is connected with an IN end of the low dropout regulator U6, an input high-end Vd2 is connected with an EN end of the low dropout regulator U6, the OUT end of the low dropout regulator U6 is respectively connected with one end of a voltage division sampling resistor R22, one end of an output filter capacitor C19, one end of a load resistor RL2 and an output high-end Vout3, the other end of the sampling resistor R22 is respectively connected with an ADJ end of the low dropout regulator U6 and one end of the sampling resistor R23, and the Vc output high-end of the input voltage regulator Vc3, The other end of the voltage division sampling resistor R23, the other end of the output filter capacitor C19 and the other end of the load resistor RL2 are connected;

in the two-stage voltage-stabilizing filtering output circuit, an input voltage Vc1 is subjected to voltage-stabilizing filtering by a low-dropout regulator U4 and then outputs Vout1, an input voltage Vc2 is subjected to voltage-stabilizing filtering by a low-dropout regulator U5 and then outputs Vout2, and an input voltage Vc3 is subjected to voltage-stabilizing filtering by a low-dropout regulator U6 and then outputs Vout 3; the EN terminal of the low dropout regulator U4 is directly pulled up to the IN off, when the input voltage Vc1 is active, the output Vout1 is active, the EN terminal of the low dropout regulator U5 is controlled by the input voltage Vd1, when and only when the input voltage Vc2 and the input voltage Vd1 are active simultaneously, the output Vout2 is active, and similarly, the EN terminal of the low dropout regulator U6 is controlled by the input voltage Vd2, when and only when the input voltage Vc3 and the input voltage Vd2 are active simultaneously, the output Vout3 is active.

7. The method for controlling the multi-output timing sequence of the missile-borne secondary power supply according to claim 6, wherein when the missile-borne computer secondary power supply is powered on, the input voltage Vin outputs a voltage Va after passing through the input reverse connection protection and EMI filter circuit, when the input voltage Va rises from zero voltage to a value larger than the set value of the undervoltage protection voltage of the power-down maintaining and voltage pre-stabilizing circuit, the output voltage Vb of the voltage pre-stabilizing circuit is effective, and the output voltage Vb enters the DC push-pull isolation conversion rectifying circuit and is rectified by push-pull isolation conversion to output 3 paths of isolated secondary voltage Vc1, secondary voltage Vc2 and secondary voltage Vc 3; the output voltage Vc1 is regulated by a low dropout regulator U4 of a secondary voltage-stabilizing filtering output circuit and then outputs Vout1, the electrification of the output Vout1 is completed, at the moment, the Ref end voltage of a high-precision voltage reference source V1 in a multi-path isolation output sequential control circuit is smaller than a set value, the output cathode C end of the high-precision voltage reference source V1 is at a high level, the input end of a photoelectric coupler B1 is conducted, the output Vd1 and the output Vd2 are at a low level, and the output of the low dropout regulator U5 and the output of the low dropout regulator U6 in the secondary voltage-stabilizing filtering output circuit are forbidden; with the continuous rising of the input voltage Va, when the Ref terminal voltage of the high-precision voltage reference source V1 in the multi-path isolation output timing control circuit is charged to a set value through RC delay, the output cathode C of the high-precision voltage reference source V1 outputs a low level, the zener diode D11 is cut off, the input end of the photoelectric coupler B1 is cut off, the output Vd1 is a high level, the output Vout2 of the low dropout regulator U5 of the secondary voltage stabilizing and filtering output circuit is valid, similarly, the output Vd2 is a high level, the output Vout3 of the low dropout regulator U6 of the secondary voltage stabilizing and filtering output circuit is valid, at this time, the power-on of the output Vout2 and the output Vout3 is completed, and the power-on functions of the output Vout1 leading output Vout2 and the output Vout3 are realized; as the input voltage Va continues to rise to the nominal voltage, the voltages on the energy storage capacitor C6 and the energy storage capacitor C7 also charge from Va to the nominal voltage through the current limiting resistor R2 and the current limiting resistor R3.

8. The method for controlling the multi-output sequence of the missile-borne secondary power supply as claimed in claim 7, wherein when the missile-borne computer secondary power supply is powered off, the input voltage Va starts to drop from the rated voltage, and due to the action of the front-end reverse connection protection circuit, the energy of the energy storage capacitor C6 and the energy storage capacitor C7 starts to discharge from the rated voltage to the rear-end circuit through the branch of the rectifier diode D4 to ensure that the rear-end circuit works normally within a certain time (tens of mS); with the continuous decline of the input voltage Va, when the Ref terminal voltage of a high-precision voltage reference source V1 in the multi-path isolation output timing sequence control circuit is smaller than a set value, the output cathode C end of the high-precision voltage reference source V1 outputs high level, the input end of a photoelectric coupler B1 is conducted, an output Vd1 and an output Vd2 are low level, the outputs of a low-dropout regulator U5 and a low-dropout regulator U6 of the two-stage voltage-stabilizing filtering output circuit are forbidden, the power-down of the output Vout2 and the output Vout3 is completed at the moment, and when the loads of the output Vout2 and the output Vout3 are capacitive light loads, the power-down can be accelerated by increasing a load resistor RL1 and a load resistor RL 2; at this time, because the output of the power-down maintaining and wide-range pre-voltage stabilizing circuit is normal, the output Vout1 is still valid, when the voltages of the energy storage capacitor C6 and the energy storage capacitor C7 are discharged to be less than the set value of the under-voltage protection voltage of the power-down maintaining and pre-voltage stabilizing circuit, the output voltage Vb of the pre-voltage stabilizing circuit is forbidden, further, the output Vc1 of the DC push-pull isolation conversion rectifying circuit is forbidden, the output of the low dropout regulator U4 in the secondary voltage stabilizing filter output circuit is forbidden, at this time, the power-down of the output Vout1 is completed, and thus the power-down function of the output Vout1 lagging the output Vout2 and the output Vout3 is realized.

9. The method according to claim 8, wherein the undervoltage protection voltage setting of the power-down holding and pre-voltage stabilizing circuit is 12V.

10. The method for multiplexed output timing control of a missile-borne secondary power supply as claimed in claim 8 wherein the input voltage Va to the missile-borne computer is rated at 28V.