CN114629354A - Non-common-ground type three-level Bi Buck-Boost converter remaking device - Google Patents
Non-common-ground type three-level Bi Buck-Boost converter remaking device Download PDFInfo
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- CN114629354A CN114629354A CN202210533870.XA CN202210533870A CN114629354A CN 114629354 A CN114629354 A CN 114629354A CN 202210533870 A CN202210533870 A CN 202210533870A CN 114629354 A CN114629354 A CN 114629354A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1582—Buck-boost converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
- H02M1/34—Snubber circuits
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
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- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The invention discloses a non-common-ground type three-level Bi Buck-Boost converter reforming device which comprises a bus, a first bridge arm, a reforming buffer network, an output capacitor and a load battery BAT, wherein the bus, the first bridge arm, the reforming buffer network, the output capacitor and the load battery BAT are arranged in parallel. Compared with the prior art, all the heavy bridge arms are controlled by the same outer ring controller, and each heavy bridge arm is provided with a current inner ring controller, so that current equalization is realized; the phase difference between each two carriers is pi/n, the voltage harmonic is small, and the output capacitance can be reduced to a great extent; the reset buffer network effectively solves the problems that the capacitance on the bus or the capacitance on the bus is short-circuited after reset, and the IGBT is directly damaged. The invention enables the three-level Bi Buck-Boost converter to expand the capacity, improves the performance index of the system, reduces the cost and improves the stability.
Description
Technical Field
The invention relates to the technical field of power electronic converters, and particularly provides a method and a device for realizing the repetition of a non-common-ground type three-level Bi Buck-Boost converter.
Background
In the modern society, with the increase of new energy development, wind power generation, photovoltaic power generation, microgrid and energy storage technologies are continuously developed, and bidirectional direct current converters, particularly medium-high voltage bidirectional direct current converters are used more and more. The three-level direct current conversion technology can improve the voltage grade of a system under the condition that a switching device bears lower voltage, has small harmonic wave of output voltage and has obvious advantages in the field of high-power application. The method for expanding current and power of the three-level direct current converter mainly comprises three methods of selecting a larger-size switching device, connecting the switching devices in parallel and re-connecting the switching devices. The large-size switching device is selected, so that the control difficulty is not increased, and the cost is not superior to that of the parallel connection and the weight of the switching device; the parallel connection mode of the switching devices does not increase the control difficulty, but the risk of the system is increased due to excessive parallel connection; the duplication is a method which has proper cost and can avoid the risk of parallel connection of the switching devices, but the control difficulty is increased.
Patent No. CN201811330584.3 discloses a bidirectional dc converter power loop topology suitable for three-level double half-bridge. The power loop topology comprises a high-frequency transformer and a primary side circuit and a secondary side circuit which are connected to two sides of the high-frequency transformer; the primary side circuit includes: the high-frequency transformer comprises a primary side half-bridge circuit connected with the high-frequency transformer, a first clamping bridge arm and a high-voltage side power supply which are connected with the primary side half-bridge circuit, a first resistance circuit and a first capacitance circuit which are connected with the high-voltage side power supply, and a power inductor which is connected between the primary side half-bridge circuit and the primary side of the high-frequency transformer; the secondary side circuit includes: the high-frequency transformer comprises a secondary side half-bridge circuit connected with the high-frequency transformer, a second clamping bridge arm and a low-voltage side power supply which are connected with the secondary side half-bridge circuit, and a second resistor circuit and a second capacitor circuit which are connected with the low-voltage side power supply. The power loop topology is suitable for occasions with high voltage on one side and high current on the other side.
Disclosure of Invention
The non-common-ground three-level Bi Buck-Boost direct-current converter has the advantages that PWM driving control signals are excessive, more signals are generated after the PWM driving control signals are repeated, the control becomes more complex, the short circuit of an upper capacitor or a lower capacitor of a bus can be caused due to poor control, the direct connection of an IGBT is damaged, and the converter cannot work normally. The research and development of a simple and efficient reconstruction method has higher research and application values.
The technical task of the invention is to provide a non-common-ground three-level Bi Buck-Boost converter reconstruction method aiming at the problems.
In order to achieve the purpose, the invention provides the following technical scheme:
a non-common-ground three-level Bi Buck-Boost converter remaking device comprises a bus, a first bridge arm, a remaking buffer network, an output capacitor and a load battery BAT, wherein the bus, the first bridge arm, the remaking buffer network, the output capacitor and the load battery BAT are arranged in parallel, and the device comprises:
the bus bar structure comprises a bus bar upper capacitor Cp and a bus bar lower capacitor Cn,
the structure of the first bridge arm comprises a switching tube T1_1, a switching tube T2_1, a switching tube T3_1 and a switching tube T4_1,
the structure of the heavy bridge arm comprises a switching tube T1_ n, a switching tube T2_ n, a switching tube T3_ n and a switching tube T4_ n,
the output capacitor comprises a first output capacitor Cout _1 and a reset output capacitor Cout _ n;
the upper end of the bus upper capacitor Cp is connected with a bus positive voltage Udc +, the lower end of the bus upper capacitor Cp is connected with the upper end of a bus lower capacitor Cn, the lower end of the bus lower capacitor Cn is connected with a bus negative voltage Udc-, and the bus upper and lower capacitor connecting point is a bus midpoint: point 0.
The value range of n is 2-9, and 1-8 remaking bridge arms can be arranged according to different values of n.
The connection relation of the first bridge arm is as follows:
the upper end of the first switch tube T1_1 is connected with the bus positive voltage Udc +, the lower end is connected with the upper end of the second switch tube T2_1 at a point a1, a1 is connected with the end of the reforming buffer network a1,
the lower end of the second switching tube T2_1 is connected with the midpoint 0 point and the upper end of the third switching tube T3_1, the lower end of the third switching tube T3_1 and the upper end of the fourth switching tube T4_1 are connected at a point b1, a point b1 is connected with a reforming buffer network b1,
the lower end of the fourth switching tube T4_1 is connected with the negative bus voltage Udc-.
The connection relation of the nth remaking bridge arm is as follows:
the upper end of the first switch tube T1_ n is connected with the positive voltage Udc + of the bus, the lower end is connected with the upper end of the second switch tube T2_ n at an end, the end is connected with the end of the reforming buffer network an,
the lower end of the second switch tube T2_ n is connected with the midpoint 0 and the upper end of the third switch tube T3_ n,
the lower end of the third switch tube T3_ n is connected with the upper end of the fourth switch tube T4_ n at a point bn, the point bn is connected with the end bn of the reforming buffer network,
the lower end of the fourth switching tube T4_ n is connected with the negative bus voltage Udc-.
The device further comprises:
the bridge arm comprises an outer ring controller, a first bridge arm inner ring controller 1, a remaking bridge arm inner ring controller 2-n and a driving waveform generation module.
The output end Uo + _1 of the re-buffering network is connected with the upper end of the first output capacitor Cout _1 at the Uo + _1 point,
the output end Uo + _ n of the reset buffer network is connected with the upper end of a reset output capacitor Cout _ n at the point Uo + _ n,
and the Uo + _1 point and the Uo + _ n point are connected with the anode of a load battery BAT.
The output end Uo-1 of the re-buffering network is connected with the lower end of the first output capacitor Cout _1 at the point Uo-1,
the output end Uo-n of the re-quantization buffer network is connected with the lower end of the re-quantization output capacitor Cout _ n at the point Uo-n,
and the UO-1 point and the UO-n point are both connected with the negative electrode of the load battery BAT.
The said duplicate buffer network is n square 2 winding inductances with the same structure, the homonymous ends of the two windings are an and UO- _ n, the other ends of the two windings are bn and UO + _ n, among them:
an and UO _ n, bn and UO + _ n are ports of the rebuffering network;
port a1 is connected to first leg output point a1 and port an is connected to nth leg output point an;
the port b1 is connected with a first bridge arm output point b1, and the port bn is connected with an nth bridge arm output point bn;
the port Uo + _1 is connected with the upper end of the first output capacitor Cout _1 at Uo + _1,
the port Uo-1 is connected to the lower end of the first output capacitor Cout _1 at Uo-1,
the upper end of the port UO + _ n and the nth output capacitor Cout _ n are connected with UO + _ n,
the port UO-n is connected with the lower end of the nth output capacitor Cout _ n at UO-n.
The output voltage sampling end Uo _ back is connected with the inverting end of the outer loop controller,
the output voltage reference terminal Uo _ ref is connected to the positive phase terminal of the outer loop controller, and the output terminal of the outer loop controller is connected to the positive phase input terminals of the inner loop controllers 1 to n.
The output current i1 at the point a1 is connected with the inverting input terminal of the inner ring controller 1,
the an point output current in is connected with the inverting input end of the inner ring controller n;
the output end PI _1 of the inner ring controller 1 and the output end PI _ n of the inner ring controller n are both sent to a driving waveform generating module;
the driving waveform generation module outputs PWM driving signals T1_1, T2_1, T3_1, T4_1, T1_ n, T2_ n, T3_ n and T4_ n to drive the corresponding switching tubes to work.
The driving waveform generated by the driving waveform generating module comprises:
the driving signals T1_1, T2_1, T3_1, T4_ 1;
two paths of triangular waves Uc1 and Uc2,
drive signals T1_ n, T2_ n, T3_ n, T4_ n;
two paths of triangular waves Uc1_ n and Uc2_ n;
wherein the inner loop controller 1 output signal PI _1 is compared with Uc1 and Uc 2: PI _1> Uc1, T1_1=1, T2_1=0, PI _1> Uc2, T4_1=1, T3_1=0, T1_1 is complementary to T2_1, T3_1 is complementary to T4_ 1;
the inner loop controller n output signal PI _ n is compared with Uc1_ n and Uc2_ n: PI _ n > Uc1_ n, T1_ n =1, T2_ n =0, PI _ n > Uc2_ n, T4_ n =1, T3_ n =0, T1_ n is complementary to T2_ n, T3_ n is complementary to T4_ n;
the triangular waves Uc1_ n and Uc2_ n are 180 ° out of phase, and the triangular waves Uc1_1 and Uc1_ n are at an angle θ, where θ = π/n.
Compared with the prior art, the non-common-ground type three-level Bi Buck-Boost converter provided by the invention is used for realizing the digitization
The device has the following outstanding advantages:
compared with the prior art, all the heavy bridge arms are controlled by the same outer ring controller, and each heavy bridge arm is provided with a current inner ring controller, so that current equalization is realized; the phase difference between each two carriers is pi/n, the voltage harmonic is small, and the output capacitance can be reduced to a great extent; the reset buffer network effectively solves the problems that the capacitance on the bus or the capacitance on the bus is short-circuited after reset, and the IGBT is directly damaged. The invention enables the three-level Bi Buck-Boost converter to expand the capacity, simultaneously improves the performance index of the system, reduces the cost and improves the stability.
Drawings
FIG. 1 is a system block diagram of a redeployment device of the present invention;
fig. 2 is a system block diagram of a driving waveform generating section of the present invention;
FIG. 3 is a schematic diagram of a reorder buffer network;
FIG. 4 is a schematic diagram of the driving waveforms of the present invention;
description of reference numerals:
in fig. 2, 1, first subtractors (1) and (2), first PI controllers (2) and (3), second subtractors (3) and (4), second PI controllers (4) and (5), third subtractors (5) and (6), third PI controllers (6) and (7) and a driving waveform generation module.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
1. For example, with n = 3:
as shown in fig. 1, a non-common-ground three-level Bi Buck-Boost converter reconstruction device includes a bus, a first bridge arm, a reconstruction buffer network, an output capacitor, and a load battery BAT, where:
the bus bar structure comprises a bus bar upper capacitor Cp and a bus bar lower capacitor Cn,
the structure of the first bridge arm comprises a switching tube T1_1, a switching tube T2_1, a switching tube T3_1 and a switching tube T4_1,
the structure of the heavy bridge arm comprises a switching tube T1_2, a switching tube T2_2, a switching tube T3_2 and a switching tube T4_2,
the structure of the heavy bridge arm comprises a switching tube T1_3, a switching tube T2_3, a switching tube T3_3 and a switching tube T4_3,
the output capacitors comprise a first output capacitor Cout _1, a second output capacitor Cout _2 and a reset output capacitor Cout _ 3;
the upper end of the bus upper capacitor Cp is connected with a bus positive voltage Udc +, the lower end of the bus upper capacitor Cp is connected with the upper end of a bus lower capacitor Cn, the lower end of the bus lower capacitor Cn is connected with a bus negative voltage Udc-, and the bus upper and lower capacitor connecting point is a bus midpoint: point 0.
The connection relation of the first bridge arm is as follows:
the upper end of the first switch tube T1_1 is connected with the bus positive voltage Udc +, the lower end is connected with the upper end of the second switch tube T2_1 at a point a1, a1 point is connected with a re-transformation buffer network a1 end,
the lower end of the second switching tube T2_1 is connected with the midpoint 0 point and the upper end of the third switching tube T3_1, the lower end of the third switching tube T3_1 and the upper end of the fourth switching tube T4_1 are connected at a point b1, a point b1 is connected with a reforming buffer network b1,
the lower end of the fourth switching tube T4_1 is connected with the negative bus voltage Udc-.
The 2 nd reconstruction bridge arm connection relation is as follows:
the upper end of the first switch tube T1_2 is connected with the bus positive voltage Udc +, the lower end is connected with the upper end of the second switch tube T2_2 at a point a2, a2 is connected with the an end of the reforming buffer network,
the lower end of the second switch tube T2_2 is connected with the midpoint 0 and the upper end of the third switch tube T3_2,
the lower end of the third switch tube T3_2 and the upper end of the fourth switch tube T4_2 are connected at a point b2, a point b2 is connected with a reforming buffer network b2,
the lower end of the fourth switching tube T4_2 is connected with the negative bus voltage Udc-.
The 3 rd reconstruction bridge arm connection relation is as follows:
the upper end of the first switch tube T1_3 is connected with the bus positive voltage Udc +, the lower end is connected with the upper end of the second switch tube T2_3 at a point a3, a3 is connected with the an end of the reforming buffer network,
the lower end of the second switch tube T2_3 is connected with the midpoint 0 and the upper end of the third switch tube T3_3,
the lower end of the third switch tube T3_3 is connected with the upper end of the fourth switch tube T4_3 at a point b3, a point b3 is connected with a reforming buffer network b3,
the lower end of the fourth switching tube T4_3 is connected with the negative bus voltage Udc-.
As shown in fig. 2, the apparatus further comprises:
the system comprises an outer ring controller, a first bridge arm inner ring controller 1, a second bridge arm inner ring controller, a third bridge arm inner ring controller and a driving waveform generation module.
The output end Uo + _1 of the re-buffering network is connected with the upper end of the first output capacitor Cout _1 at the Uo + _1 point,
the output end Uo + _2 of the remaking buffer network is connected with the upper end of a remaking output capacitor Cout _2 at a Uo + _2 point,
the output end Uo + _3 of the reset buffer network is connected with the upper end of a reset output capacitor Cout _3 at a Uo + _3 point,
and the Uo + _1 point, the Uo + _2 point and the Uo + _3 point are connected with the anode of a load battery BAT.
The output end Uo- _1 of the rearrangement buffer network is connected with the lower end of the first output capacitor Cout _1 at the point Uo- _1,
the lower end of the output end UO-2 of the re-quantization buffer network is connected with the lower end of the re-quantization output capacitor Cout-2 at the UO-2 point,
the lower end of the output end UO- _3 of the re-quantization buffer network is connected with the lower end of a re-quantization output capacitor Cout _3 at a UO- _3 point,
and the UO- _1 point, the UO- _2 point and the UO- _3 point are connected with the negative electrode of the load battery BAT.
As shown in fig. 3, the said remaking buffer network is n square 2 winding inductors with the same structure, the ends with the same name of two windings are an (1-3) and Uo _n (1-3), and the other ends of two windings are bn (1-3) and Uo + _ n (1-3), where:
an (1-3) and UO-n (1-3), bn (1-3) and UO + _ n (1-3) are ports of the re-buffering network;
port a1 is connected to first leg output point a1, port a2 is connected to 2 nd leg output point a2, and port a3 is connected to 3 rd leg output point a 3;
port b1 is connected to the first leg output point b1, port b2 is connected to the 2 nd leg output point b2, and port b2 is connected to the 2 nd leg output point b 2;
the port Uo + _1 is connected with the upper end of the first output capacitor Cout _1 at Uo + _1,
the port Uo-1 is connected to the lower end of the first output capacitor Cout _1 at Uo-1,
the port Uo + _2 is connected with the upper end of the 2 nd output capacitor Cout _2 at Uo + _2,
the lower end of the port UO-2 and the lower end of the 2 nd output capacitor Cout-2 are connected with UO-2
The port Uo + _3 is connected with the upper end of the 3 rd output capacitor Cout _3 at Uo + _3,
the port UO-3 is connected to the lower end of the 3 rd output capacitor Cout _3 at UO-3.
The output voltage sampling end Uo _ back is connected with the inverting end of the outer loop controller,
the output voltage reference terminal Uo _ ref is connected to the positive phase terminal of the outer loop controller, and the output terminal of the outer loop controller is connected to the positive phase input terminals of the inner loop controllers 1 to n.
The output current i1 at the point a1 is connected with the inverting input terminal of the inner ring controller 1,
the an point output current in is connected with the inverting input end of the inner ring controller n;
an output end PI _1 of the inner ring controller 1, an output end PI _2 of the inner ring controller n and an output end PI _3 of the inner ring controller n are all sent to a driving waveform generating module;
the driving waveform generation module outputs PWM driving signals T1_1, T2_1, T3_1, T4_1, T1_2, T2_2, T3_2, T4_2, T1_3, T2_3, T3_3 and T4_3 to drive the corresponding switching tubes to work.
The driving waveform generated by the driving waveform generating module comprises:
the driving signals T1_1, T2_1, T3_1, T4_ 1;
two paths of triangular waves Uc1 and Uc2,
the driving signals T1_2, T2_2, T3_2, T4_ 2;
two paths of triangular waves Uc1_2 and Uc2_ 2;
the driving signals T1_3, T2_3, T3_3, T4_ 3;
two paths of triangular waves Uc1_3 and Uc2_ 3;
wherein the inner loop controller 1 outputs signals PI _1 which are compared with Uc1 and Uc 2: PI _1> Uc1, T1_1=1, T2_1=0, PI _1> Uc2, T4_1=1, T3_1=0; t1_1 is complementary to T2_1, and T3_1 is complementary to T4_ 1;
the inner loop controller 2 outputs signals PI _2 which are compared with Uc1_2 and Uc2_ 2: PI _2> Uc1_2, T1_2 =1, T2_2 =0, PI _2> Uc2_2, T4_2 =1, T3_2 =0, T1_2 is complementary to T2_2, T3_2 is complementary to T4_ 2;
the inner loop controller 3 outputs a signal PI _3 which is compared with Uc1_3 and Uc2_ 3: PI _3> Uc1_3, T1_3 =1, T2_3 =0, PI _3> Uc2_3, T4_3 =1, T3_3 =0, T1_3 is complementary to T2_3, T3_3 is complementary to T4_ 3;
the triangular waves Uc1_ n (1-3) and Uc2_ n (1-3) are 180 ° out of phase, and the triangular waves Uc1_1 and Uc1_ n (1-3) are out of phase by an angle θ, where θ = π/n.
2. As shown in fig. 2, the inner ring controller and the waveform generating module are implemented by a main control chip program, and are specifically implemented as follows:
the output voltage feedback value Uo _ back, the output voltage reference value Uo _ ref, the first subtracter (1) and the first PI controller (2) form an outer loop controller. The output voltage reference value Uo _ ref and the output voltage feedback value Uo _ back are connected with the input end of a first subtracter (1), input into a first PI controller (2) after the difference of the first subtracter, and output to the inner ring controllers 1 to n after the calculation of the first PI controller (2).
Output by the outer loop controller, a heavy inductor current i1,
the second subtracter (3) and the second PI controller (4) form the inner loop controller (1). The output of the outer loop controller and a heavy inductive current i1 are connected with the input end of a second subtracter (3), the difference is made by the second subtracter, then the difference is input into a second PI controller (4), and PI _1 is output after calculation by the second PI controller (4).
An inner loop controller n is formed by an outer loop controller output, n times of inductive current in, a third subtracter (5) and a third PI controller (6). The output of the outer loop controller and the n-fold inductive current in are connected with the input end of a third subtracter (5), the difference is made by the third subtracter, then the difference is input into a third PI controller (6), and PI _ n is output after calculation by the third PI controller (6).
As shown in fig. 4, PI _1 to PI _ n output by the inner ring controllers 1 to n are input to the driving waveform generation module (7), and compared with the carrier two-way triangular waves Uc1_ n and Uc2_ n, corresponding outputs T1_1, T2_1, T3_1, T4_1 to T1_ n, T2_ n, T3_ n, and T4_ n are output.
The above-described embodiments are merely preferred embodiments of the present invention, and those skilled in the art should be able to make various changes and substitutions within the scope of the present invention.
Claims (10)
1. The utility model provides a non-common ground formula three-level Bi Buck-Boost converter ization device which characterized in that, the device includes generating line, first bridge arm, the bridge arm of reforming, the buffer network of reforming, output capacitance and load battery BAT that sets up side by side, wherein:
the bus bar structure comprises a bus bar upper capacitor Cp and a bus bar lower capacitor Cn,
the structure of the first bridge arm comprises a switching tube T1_1, a switching tube T2_1, a switching tube T3_1 and a switching tube T4_1,
the structure of the heavy bridge arm comprises a switching tube T1_ n, a switching tube T2_ n, a switching tube T3_ n and a switching tube T4_ n,
the output capacitor comprises a first output capacitor Cout _1 and a reset output capacitor Cout _ n;
the upper end of the bus upper capacitor Cp is connected with a bus positive voltage Udc +, the lower end of the bus upper capacitor Cp is connected with the upper end of a bus lower capacitor Cn, the lower end of the bus lower capacitor Cn is connected with a bus negative voltage Udc-, and the bus upper and lower capacitor connecting point is a bus midpoint: point 0.
2. The non-common-ground three-level Bi Buck-Boost converter according to claim 1, wherein the first bridge arm connection relationship is:
the upper end of the first switch tube T1_1 is connected with the bus positive voltage Udc +, the lower end is connected with the upper end of the second switch tube T2_1 at a point a1, a1 is connected with the end of the reforming buffer network a1,
the lower end of the second switching tube T2_1 is connected with the midpoint 0 point and the upper end of the third switching tube T3_1, the lower end of the third switching tube T3_1 and the upper end of the fourth switching tube T4_1 are connected at a point b1, a point b1 is connected with a reforming buffer network b1,
the lower end of the fourth switching tube T4_1 is connected with the negative bus voltage Udc-.
3. The non-common-ground three-level Bi Buck-Boost converter according to claim 1, wherein the connection relationship of the reconstruction bridge arm is as follows:
the upper end of the first switch tube T1_ n is connected with the positive voltage Udc + of the bus, the lower end is connected with the upper end of the second switch tube T2_ n at an end, the end is connected with the end of the reforming buffer network an,
the lower end of the second switch tube T2_ n is connected with the midpoint 0 and the upper end of the third switch tube T3_ n,
the lower end of the third switch tube T3_ n is connected with the upper end of the fourth switch tube T4_ n at a point bn, the point bn is connected with the end bn of the reforming buffer network,
the lower end of the fourth switching tube T4_ n is connected with the negative bus voltage Udc-.
4. The non-common ground type three-level Bi Buck-Boost converter quantizing device according to claim 1, further comprising:
the bridge arm comprises an outer ring controller, a first bridge arm inner ring controller 1, a remaking bridge arm inner ring controller 2-n and a driving waveform generation module.
5. The non-common-ground three-level Bi Buck-Boost converter device of claim 1, wherein the output end Uo + _1 of said re-buffering network is connected to the upper end of the first output capacitor Cout _1 at Uo + _1 point,
the output end Uo + _ n of the reset buffer network is connected with the upper end of a reset output capacitor Cout _ n at the point Uo + _ n,
and the Uo + _1 point and the Uo + _ n point are connected with the anode of a load battery BAT.
6. The non-common ground type three-level Bi Buck-Boost converter reforming device according to claim 1, wherein the output end Uo _1 of the reforming buffer network is connected with the lower end of the first output capacitor Cout _1 at the point Uo _1,
the output end Uo-n of the re-quantization buffer network is connected with the lower end of the re-quantization output capacitor Cout _ n at the point Uo-n,
and the points UO- _1 and UO- _ n are connected with the negative electrode of the load battery BAT.
7. The non-common-ground three-level Bi Buck-Boost converter re-transformation device according to claim 5 or 6, wherein the re-transformation buffer network is n pieces of square 2-winding inductors with the same structure, the same-name ends of the two windings are an and Uo _ n, and the other ends of the two windings are bn and Uo + _ n, and wherein:
an and UO-n, bn and UO + _ n are ports of the rebuffering network;
port a1 is connected to first leg output point a1 and port an is connected to nth leg output point an;
the port b1 is connected with a first bridge arm output point b1, and the port bn is connected with an nth bridge arm output point bn;
the port Uo + _1 is connected with the upper end of the first output capacitor Cout _1 at Uo + _1,
the port UO-1 is connected with the lower end of the first output capacitor Cout _1 at UO-1,
the upper end of the port UO + _ n and the nth output capacitor Cout _ n are connected with UO + _ n,
the port UO-n is connected with the lower end of the nth output capacitor Cout _ n at UO-n.
8. The non-common ground type three-level Bi Buck-Boost converter according to claim 7, wherein said output voltage sampling terminal Uo _ back is connected to the inverting terminal of the outer loop controller,
the output voltage reference terminal Uo _ ref is connected to the positive phase terminal of the outer loop controller, and the output terminal of the outer loop controller is connected to the positive phase input terminals of the inner loop controllers 1 to n.
9. The non-common-ground three-level Bi Buck-Boost converter according to claim 8, wherein said a1 point output current i1 is connected to the inverting input terminal of the inner loop controller 1,
the an point output current in is connected with the inverting input end of the inner ring controller n;
the output end PI _1 of the inner ring controller 1 and the output end PI _ n of the inner ring controller n are all sent to a driving waveform generating module;
the driving waveform generation module outputs PWM driving signals T1_1, T2_1, T3_1, T4_1, T1_ n, T2_ n, T3_ n and T4_ n to drive the corresponding switching tubes to work.
10. The non-common-ground three-level Bi Buck-Boost converter according to claim 9, wherein the driving waveform generated by the driving waveform generating module comprises:
the driving signals T1_1, T2_1, T3_1, T4_ 1;
two paths of triangular waves Uc1 and Uc2,
driving signals T1_ n, T2_ n, T3_ n and T4_ n;
two paths of triangular waves Uc1_ n and Uc2_ n;
wherein the inner loop controller 1 outputs signals PI _1 which are compared with Uc1 and Uc 2: PI _1> Uc1, T1_1=1, T2_1=0, PI _1> Uc2, T4_1=1, T3_1=0, T1_1 is complementary to T2_1, T3_1 is complementary to T4_ 1;
the inner loop controller n output signal PI _ n is compared with Uc1_ n and Uc2_ n: PI _ n > Uc1_ n, T1_ n =1, T2_ n =0, PI _ n > Uc2_ n, T4_ n =1, T3_ n =0, T1_ n is complementary to T2_ n, T3_ n is complementary to T4_ n;
the triangular waves Uc1_ n and Uc2_ n are 180 ° out of phase, and the triangular waves Uc1_1 and Uc1_ n are at an angle θ, where θ = π/n.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101409517A (en) * | 2008-07-22 | 2009-04-15 | 南京航空航天大学 | Tri-level half-bridge single-stage inverter and control method |
| CN104113214A (en) * | 2013-04-18 | 2014-10-22 | 陕西省地方电力（集团）有限公司 | Triple-level DC-DC converter double-closed-loop control |
| CN104802646A (en) * | 2015-04-20 | 2015-07-29 | 株洲时代装备技术有限责任公司 | Method and system for recovering regenerative brake energy of energy storage type urban rail based on supercapacitor |
| CN105743344A (en) * | 2016-04-14 | 2016-07-06 | 西安许继电力电子技术有限公司 | Isolated three-level bidirectional DC-DC converter with coupling inductor |
| US20160329811A1 (en) * | 2014-01-15 | 2016-11-10 | Abb Inc. | Interleaved multi-channel, multi-level, multi-quadrant dc-dc converters |
| US20200099313A1 (en) * | 2017-06-02 | 2020-03-26 | Huawei Technologies Co., Ltd. | Multi-level circuit, three-phase multi-level circuit, and control method |
| CN110932256A (en) * | 2019-12-24 | 2020-03-27 | 新风光电子科技股份有限公司 | Three-level topology energy storage device for rail transit and control method thereof |
-
2022
- 2022-05-17 CN CN202210533870.XA patent/CN114629354A/en not_active Withdrawn
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101409517A (en) * | 2008-07-22 | 2009-04-15 | 南京航空航天大学 | Tri-level half-bridge single-stage inverter and control method |
| CN104113214A (en) * | 2013-04-18 | 2014-10-22 | 陕西省地方电力（集团）有限公司 | Triple-level DC-DC converter double-closed-loop control |
| US20160329811A1 (en) * | 2014-01-15 | 2016-11-10 | Abb Inc. | Interleaved multi-channel, multi-level, multi-quadrant dc-dc converters |
| CN104802646A (en) * | 2015-04-20 | 2015-07-29 | 株洲时代装备技术有限责任公司 | Method and system for recovering regenerative brake energy of energy storage type urban rail based on supercapacitor |
| CN105743344A (en) * | 2016-04-14 | 2016-07-06 | 西安许继电力电子技术有限公司 | Isolated three-level bidirectional DC-DC converter with coupling inductor |
| US20200099313A1 (en) * | 2017-06-02 | 2020-03-26 | Huawei Technologies Co., Ltd. | Multi-level circuit, three-phase multi-level circuit, and control method |
| CN110932256A (en) * | 2019-12-24 | 2020-03-27 | 新风光电子科技股份有限公司 | Three-level topology energy storage device for rail transit and control method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 张喜茂，孙丛君: ""三电平地铁再生制动能量储能变流器研究"", 《电气化铁道》 * |
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