CN114628374A

CN114628374A - Chip packaging structure and manufacturing method thereof

Info

Publication number: CN114628374A
Application number: CN202011458844.2A
Authority: CN
Inventors: 王梓瑄; 刘承衔
Original assignee: Unimicron Technology Corp
Current assignee: Unimicron Technology Corp
Priority date: 2020-12-11
Filing date: 2020-12-11
Publication date: 2022-06-14

Abstract

The invention discloses a chip packaging structure and a manufacturing method thereof. The chip packaging structure comprises a circuit board, a first chip, a second chip, a heat conduction material, a mold sealing material and a heat dissipation part. The circuit board comprises a plurality of circuit connecting pads. The first chip is arranged on the circuit board and is electrically connected with at least one of the circuit pads. The first chip is positioned between the second chip and the circuit board. The heat conduction material is positioned on the circuit board and penetrates through the second chip and the first chip to extend to the circuit board. The molding material is disposed on the circuit board, and the heat dissipation part is disposed on the molding material and thermally coupled to the heat conductive material. The heat conducting materials penetrating through the first chip and the second chip can conduct heat energy to the heat dissipation part so as to help the chips dissipate heat. In addition, a method for manufacturing the chip package structure is also provided.

Description

Chip packaging structure and manufacturing method thereof

Technical Field

The present invention relates to a chip package structure and a method for manufacturing the same, and more particularly, to a stacked chip package structure (stacked package structure) and a method for manufacturing the same.

Background

The existing semiconductor packaging technology has developed a stacked chip package structure, which includes a plurality of chips stacked on each other and a molding compound covering the chips, wherein the chips are usually sealed by the molding compound. However, the thermal conductivity of the molding material is low, so that the heat generated by the chips stacked on top of each other is not easily dissipated from the molding material, and the heat is easily accumulated on the chips, thereby reducing the performance of the chips.

Disclosure of Invention

At least one embodiment of the present invention provides a chip package structure, which includes a thermal conductive material capable of dissipating heat of at least two chips.

Another embodiment of the present invention provides a method for manufacturing a chip package structure, so as to manufacture the chip package structure.

The chip packaging structure provided by at least one embodiment of the invention comprises a circuit board, a first chip, a second chip, a heat conduction material, a mold sealing material and a heat dissipation part. The circuit board comprises a main body part and a plurality of circuit connecting pads, wherein the main body part is provided with an installation surface, and the circuit connecting pads are positioned on the installation surface. The first chip is arranged on the mounting surface and is electrically connected with at least one of the circuit pads. The second chip is stacked on the first chip, wherein the first chip is positioned between the second chip and the circuit board. The second chip is provided with a first surface and a second surface opposite to the first surface. The heat conduction material is located on the circuit board and penetrates through the second chip and the first chip, wherein the heat conduction material sequentially penetrates through the second chip and the first chip from the second surface of the second chip and extends to the circuit board. The molding material is disposed on the mounting surface and covers the first chip and the mounting surface, wherein the molding material surrounds the second chip. The heat dissipation part is arranged on the molding material and is thermally coupled with the heat conduction material, wherein the molding material is positioned between the heat dissipation part and the circuit board.

In at least one embodiment of the present invention, the heat dissipation portion directly contacts the heat conductive material and the second surface of the second chip.

In at least one embodiment of the present invention, the first chip has at least one first through hole, and the second chip has at least one second through hole. The heat conducting material is an electric insulator and fills the first through hole, the second through hole, the first gap and the second gap, wherein the first gap is located between the first chip and the circuit board, and the second gap is located between the first chip and the second chip.

In at least one embodiment of the present invention, the first chip has at least one first through hole, and the second chip has at least one second through hole. The heat conduction material comprises at least one metal column, the metal column penetrates through the first chip and the second chip from the first through hole and the second through hole, and the first chip, the second chip and the circuit pads are electrically insulated from the heat conduction material.

In at least one embodiment of the present invention, the chip package structure further includes at least one conductive pillar. The conductive column penetrates through the first chip and is positioned between the second chip and the circuit board, wherein the conductive column is electrically connected with at least one of the circuit pads and the second chip, and the heat conduction material is electrically insulated from the conductive column.

In at least one embodiment of the present invention, the size of the first chip is larger than the size of the second chip.

In at least one embodiment of the present invention, the heat conductive material has a top surface, and the molding material has an upper surface. The top surface, the second surface and the upper surface are aligned with each other.

The method for manufacturing a chip package structure provided in at least one embodiment of the present invention includes mounting a first chip and a second chip on a circuit board, wherein the first chip is located between the second chip and the circuit board. The first chip has at least one first through hole, and the second chip has at least one second through hole. Filling the first through hole and the second through hole with a heat conductive material. And forming a molding material on the circuit board, wherein the molding material covers the first chip and the circuit board and surrounds the second chip. A heat sink portion is formed over the molding material, wherein the heat sink portion is thermally coupled to the thermally conductive material.

In at least one embodiment of the present invention, the thermal conductive material is filled in the first through hole and the second through hole before the molding material is formed.

In at least one embodiment of the invention, before the thermal conductive material is filled in the first through hole and the second through hole, a jig is disposed on the circuit board, wherein the jig covers and fixes the first chip and the second chip, and has an opening exposing the second through hole, and the thermal conductive material is filled in the first through hole and the second through hole from the opening. After the heat conductive material is filled in the first through hole and the second through hole and before the molding material is formed, the jig is removed.

In at least one embodiment of the present invention, forming the molding material on the circuit board includes the following steps. And forming an initial molding material on the circuit board, wherein the initial molding material covers the first chip, the second chip, the circuit board and the heat conduction material. A portion of the initial encapsulation material over the second chip is removed to expose the thermally conductive material.

In at least one embodiment of the present invention, the method of removing a portion of the initial encapsulation material over the second chip includes grinding the initial encapsulation material to expose the thermally conductive material and the second chip.

In at least one embodiment of the present invention, the thermal conductive material is filled in the first through hole and the second through hole after the molding material is formed.

In at least one embodiment of the invention, before the thermal conductive material is filled in the first through hole and the second through hole, a covering layer is disposed on the second chip, wherein the covering layer completely covers the second through hole. And forming an initial molding material on the circuit board, wherein the initial molding material covers the first chip, the second chip, the circuit board and the cover layer. Removing a portion of the initial molding material over the second chip to expose the cap layer. After removing a portion of the initial molding material located above the second chip, the cover layer is removed to expose the second through hole.

In at least one embodiment of the present invention, the method of removing the portion of the initial molding material over the second chip includes photolithography or laser drilling.

In at least one embodiment of the present invention, the heat conductive material is filled in the first through hole and the second through hole before the first chip and the second chip are mounted on the circuit board.

In at least one embodiment of the present invention, the method for filling the first through hole and the second through hole with the thermal conductive material includes performing through hole electroplating on the first through hole and the second through hole to form a first sub-metal pillar in the first through hole and a second sub-metal pillar in the second through hole.

In at least one embodiment of the present invention, in the process of mounting the first chip and the second chip on the circuit board, the second sub-metal pillar is aligned with the first sub-metal pillar, and the second sub-metal pillar is connected to the first sub-metal pillar.

In at least one embodiment of the present invention, before the first chip and the second chip are mounted on the circuit board, at least one conductive pillar penetrating through the first chip is formed.

Based on the above, since the heat conductive material can penetrate through the plurality of chips (e.g., the second chip and the first chip), the heat conductive material can conduct the heat energy of the chips to the heat dissipation portion, so that the heat energy of the chips can be conducted to the heat dissipation portion rapidly, thereby helping the chips dissipate heat.

Drawings

Fig. 1A to fig. 1J are schematic cross-sectional views illustrating a method for manufacturing a chip package structure according to at least one embodiment of the invention.

Fig. 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing a chip package structure according to another embodiment of the invention.

Fig. 3A to 3C are schematic cross-sectional views illustrating a method for manufacturing a chip package structure according to another embodiment of the invention.

[ description of main element symbols ]

10: jig 11, 252: opening of the container

17: an upper cover 18: first wall body

19: second wall 20: covering layer

34:

metal posts

100, 200, 300: chip packaging structure

110. 110 i:

first chips

111, 111i, 121 i: chip body

112. 113, 122, 132a, 132 b: line pad 114: conductive pole

119 a: through hole 119 b: the first through hole

119s, 129 s:

side walls

120, 120 i: second chip

129 b: second through hole 130: circuit board

131: main body portion 131 a: mounting surface

131 b: back surfaces 133a, 133 b: insulating protective layer

134: metal layers 136, 137: conductive connecting piece

138: insulating layer 139: line layer

140. 240, 340: heat conductive materials 141, 241: the top surface

150. 250: molding material 151, 251: upper surface of

160: heat dissipation portion 341: first sub-metal column

342: second sub-metal posts B1, B2: solder ball

G1: first gap G2: second gap

P10, P11, P20, P21: non-functional regions P12, P22: functional area

S21: first surface S22: second surface

Detailed Description

In the following description, the dimensions (e.g., length, width, thickness, and depth) of elements (e.g., layers, films, substrates, regions, etc.) in the figures are exaggerated in various proportions for the sake of clarity. Accordingly, the following description and illustrations of the embodiments are not limited to the sizes and shapes of elements shown in the drawings, but are intended to cover deviations in sizes, shapes and both that result from actual manufacturing processes and/or tolerances. For example, the planar surfaces shown in the figures may have rough and/or non-linear features, while the acute angles shown in the figures may be rounded. Therefore, the elements shown in the drawings are for illustrative purposes only, and are not intended to accurately depict the actual shapes of the elements or to limit the scope of the claims.

Furthermore, the terms "about", "approximately" or "substantially" as used herein encompass not only the explicitly recited values and ranges of values, but also the allowable range of deviation as understood by those of ordinary skill in the art, wherein the range of deviation can be determined by the error in measurement, for example, due to limitations of both the measurement system and the process conditions. Furthermore, "about" can mean within one or more standard deviations of the above-described values, e.g., within ± 30%, 20%, 10%, or 5%. The terms "about", "approximately" or "substantially" as used herein may be selected with an acceptable range of deviation or standard deviation based on the optical, etching, mechanical or other properties, and not all of the optical, etching, mechanical and other properties may be used with one standard deviation alone.

Fig. 1A to 1J are schematic cross-sectional views illustrating a method for manufacturing a chip package structure according to at least one embodiment of the invention, wherein fig. 1J illustrates a substantially completed chip package structure 100. Referring to fig. 1A, in the method for manufacturing a chip package structure of the present embodiment, first, a first chip 110i is provided, wherein the first chip 110i includes a chip main body 111i and a plurality of circuit pads 112, and the circuit pads 112 are located on one surface of the chip main body 111 i. Taking fig. 1A as an example, the circuit pads 112 are all located on the lower surface of the chip main body 111 i.

In the present embodiment, the first chip 110i may be a die (die), which is an unpackaged chip. Accordingly, the main material of the chip body 111i may be a semiconductor material, such as silicon or gallium arsenide. However, in other embodiments, the first chip 110i may be a packaged chip, so the first chip 110i is not limited to an unpackaged die. The chip body 111i has a non-functional region P10 and a functional region P12, in which the functional region P12 adjoins the non-functional region P10. The functional region P12 stores circuitry (circuitry) of the first chip 110i, but the non-functional region P10 may not store any circuitry.

Referring to fig. 1B, at least one conductive pillar 114 is formed. In the embodiment shown in fig. 1B, a plurality of conductive posts 114 may be formed, but in other embodiments, only one conductive post 114 may be formed. Therefore, fig. 1B is for illustration only, and does not limit the number of conductive pillars 114. Referring to fig. 1A and fig. 1B, in the present embodiment, a method for forming the conductive pillars 114 may include the following steps.

First, a drilling process is performed on the non-functional region P10 of the first chip 110i to form the first chip 110 having at least one via 119a, wherein fig. 1B illustrates the formation of a plurality of vias 119 a. Since only one conductive pillar 114 may be formed, in other embodiments, the first chip 110 may have only one through hole 119 a. The first chip 110 also includes a chip body 111, and the chip body 111 has a functional region P12 and a non-functional region P11, wherein the difference between the non-functional regions P11 and P10 is only in the presence or absence of the through hole 119a, and no circuitry exists in the non-functional region P11.

The drilling process may be a Through Silicon Via (TSV) process. For example, the via hole 119a may be formed by laser drilling or etching. Next, an electroplating process is performed on the first chip 110 to form the conductive pillars 114 in the through holes 119a, wherein the conductive pillars 114 penetrate through the first chip 110. In addition, the electroplating process can be used to form not only the conductive pillars 114, but also at least one circuit pad 113 (fig. 1B shows a plurality of circuit pads 113), wherein the

circuit pads

113 and 112 are both located on the same surface of the chip body 111, and the circuit pad 113 is connected to the conductive pillars 114.

It should be noted that the drilling process not only forms the through hole 119a, but also forms at least one first through hole 119b in the non-functional region P11. Therefore, first chip 110 not only has via 119a, but also has first via 119b, wherein the first via 119b and via 119a may have the same orientation. In addition, the embodiment shown in fig. 1B is illustrated with a plurality of first through holes 119B, but in other embodiments, the first chip 110 may have a single first through hole 119B. Therefore, fig. 1B does not limit the number of the first through holes 119B included in the first chip 110.

Since no circuit system exists in the non-functional region P11, the first through holes 119b and the through holes 119a do not affect the overall circuit function of the circuit pad 112, and the conductive posts 114 and the circuit pad 113 in the non-functional region P11 may not be directly electrically connected to the circuit pad 112. In other words, when the first chip 110 is not mounted on the circuit board 130, both the conductive pillars 114 and the circuit pads 113 may be electrically insulated from the circuit pads 112.

Referring to fig. 1C, a second chip 120i is provided. The second chip 120i includes a chip body 121i and a plurality of circuit pads 122. The circuit pads 122 are disposed on one surface of the chip body 121 i. Taking fig. 1C as an example, the circuit pads 122 are all located on the lower surface of the chip body 121 i. The chip body 121i also has a non-functional region P20 and a functional region P22, wherein the functional region P22 adjoins the non-functional region P20. The functional region P22 stores the circuitry of the second chip 120i, but the non-functional region P20 stores no circuitry.

The second chip 120i may also be a die, i.e., an unpackaged chip. Accordingly, the main material of the chip body 121i may also be a semiconductor material, such as silicon or gallium arsenide. However, in other embodiments, the second chip 120i may be a packaged chip, so the second chip 120i is not limited to being an unpackaged die. In addition, as can be seen from comparing fig. 1A and fig. 1C, the size of the first chip 110i is significantly larger than that of the second chip 120 i.

Referring to fig. 1D, a drilling process is then performed on the non-functional region P20 of the second chip 120i to form the second chip 120 having at least one second via 129 b. Specifically, the second chip 120 further has a first surface S21 and a second surface S22 opposite to the first surface S21, wherein the second through hole 129b extends from the second surface S22 to the first surface S21. Therefore, the two end holes of the second through hole 129b are exposed to the first surface S21 and the second surface S22, respectively. In addition, since the size of the first chip 110i is larger than that of the second chip 120i, the size of the first chip 110 is also larger than that of the second chip 120.

Fig. 1D illustrates forming a plurality of second vias 129b, but fig. 1D does not limit the number of second vias 129 b. The second via 129b may be formed in the same manner as the first via 119b, so the drilling process performed on the non-functional region P20 may be a Through Silicon Via (TSV) process. In addition, the second chip 120 also includes a chip body 121, and the chip body 121 has a functional region P22 and a non-functional region P21. The difference between the non-functional areas P21 and P20 is only the presence or absence of the second via 129b, wherein the second via 129b is located in the non-functional area P21, and no circuitry is located in the non-functional area P21.

Referring to fig. 1E and fig. 1F, next, the first chip 110 and the second chip 120 are mounted on the circuit board 130. The circuit board 130 includes a main body 131 and a plurality of circuit pads 132a, wherein the main body 131 has a mounting surface 131a and a back surface 131b opposite to the mounting surface 131a, and the circuit pads 132a are located on the mounting surface 131 a. The first chip 110 and the second chip 120 are both mounted on the mounting surface 131a, and the first chip 110 is electrically connected to at least one of the circuit pads 132 a.

In the embodiment shown in fig. 1E and 1F, after the first chip 110 is mounted on the circuit board 130, the second chip 120 is mounted on the first chip 110, so that the second chip 120 is stacked on the first chip 110, wherein both the first chip 110 and the second chip 120 can be mounted on the circuit board 130 by using a flip chip method. Specifically, the first chip 110 may be mounted on the mounting surface 131a of the circuit board 130 by using a plurality of solder balls B1, wherein the

circuit pads

112 and 113 of the first chip 110 are electrically connected to the circuit pads 132a through the solder balls B1, respectively, so that the first chip 110 can be electrically connected to at least one of the circuit pads 132 a.

Referring to fig. 1F, the second chip 120 may be mounted on the first chip 110. For example, the second chip 120 may be mounted on the first chip 110 by using a plurality of solder balls B2, wherein the circuit pads 122 of the second chip 120 are electrically connected to the conductive pillars 114 through the solder balls B2, respectively. Since the conductive pillars 114 are respectively connected to the circuit pads 113, and the circuit pads 113 are respectively electrically connected to the circuit pads 132a through the solder balls B1, the conductive pillars 114 can respectively electrically connect the circuit pads 132a and the second chip 120. Thus, the circuit pads 122 of the second chip 120 can be electrically connected to the circuit pads 132a through the solder balls B1, B2, the conductive posts 114 and the circuit pads 113, so that the second chip 120 is electrically connected to the circuit board 130, as shown in fig. 1F.

Since the conductive pillars 114 and the circuit pads 113 are located in the non-functional region P11 (see fig. 1B) of the first chip 110, the second chip 120 is not electrically connected to the first chip 110 only through the solder balls B1, B2, the conductive pillars 114 and the circuit pads 113. That is, the electrical signal generated by the second chip 120 cannot be directly transmitted to the first chip 110 through the conductive pillar 114, and must be transmitted to the first chip 110 through the circuit board 130.

After the first chip 110 and the second chip 120 are both mounted on the circuit board 130, the first chip 110 is located between the second chip 120 and the circuit board 130, and the first surface S21 is located between the second surface S22 and the first chip 110, wherein the conductive pillar 114 is located between the second chip 120 and the circuit board 130. Gaps are formed between adjacent two of the first chip 110, the second chip 120 and the circuit board 130. Taking fig. 1F as an example, a first gap G1 may be formed between the first chip 110 and the circuit board 130, and a second gap G2 may be formed between the first chip 110 and the second chip 120. In addition, since the size of the first chip 110 is larger than that of the second chip 120, the first chip 110 may protrude from the sidewall 129s of the second chip 120.

The circuit board 130 may be a printed circuit board or a package carrier (package carrier), and the main body portion 131 is a component of the circuit board 130 except for the circuit pads 132 a. In the present embodiment, the main body 131 may include a plurality of circuit pads 132b, a plurality of insulating layers 138, a plurality of circuit layers 139, and a plurality of

conductive connectors

136 and 137. The circuit pads 132b are opposite to the circuit pads 132a, and the circuit pads 132b are located on the back surface 131 b. The insulating layers 138 and the circuit layers 139 are stacked alternately, wherein each circuit layer 139 may be sandwiched between two adjacent insulating layers 138.

The

conductive connectors

136 and 137 are disposed in the insulating layers 138 and electrically connect the circuit layers 139 and the

circuit pads

132a and 132b, so that electrical signals transmitted in the circuit layers 139 can be transmitted between the circuit layers 139 and the

circuit pads

132a and 132b through the

conductive connectors

136 and 137. In addition, in the present embodiment, the conductive connecting element 136 may be a conductive blind via structure, and the conductive connecting element 137 may be a conductive buried via structure, as shown in fig. 1E and 1F.

In the embodiment, the circuit board 130 is a multilayer circuit board and has four circuit layers, i.e., two circuit layers 139 and

circuit pads

132a and 132b respectively located at two opposite sides of the circuit board 130. However, in other embodiments, the circuit board 130 may be a single-layer circuit board or a double-sided circuit board. Alternatively, the circuit layer of the circuit board 130 may have more than four layers, and therefore, the number of the circuit layers of the circuit board 130 is not limited by fig. 1E and F.

It should be noted that, in the embodiment shown in fig. 1E and fig. 1F, the first chip 110 and the second chip 120 are mounted on the circuit board 130 in a flip-chip manner. However, in other embodiments, the first chip 110 and the second chip 120 may be mounted on the circuit board 130 by other methods besides flip-chip, such as wire bonding (wire bonding). Second, the second chip 120 can also be electrically connected to the circuit board 130 directly by wire bonding without electrically connecting the circuit board 130 through the conductive posts 114. In other words, when the second chip 120 is electrically connected to the circuit board 130 by wire bonding, the conductive pillars 114 shown in fig. 1F can be omitted. Therefore, the way of mounting the first chip 110 and the second chip 120 on the circuit board 130 shown in fig. 1F is for illustration only, and is not limited to mounting only in a flip-chip manner.

Particularly, in the present embodiment, the circuit board 130 may further include two insulating

protection layers

133a and 133b, wherein the insulating protection layer 133a may cover the mounting surface 131a and expose the circuit pads 132 a. The insulating passivation layer 133b is disposed on the main body portion 131 and opposite to the insulating passivation layer 133a, wherein the main body portion 131 is disposed between the insulating

passivation layers

133a and 133b, and the insulating passivation layer 133b is disposed on the back surface 131b and exposes the circuit pads 132 b. In addition, the insulating

passivation layers

133a and 133b may be solder masks.

Particularly, the circuit board 130 may further include a metal layer 134, wherein the metal layer 134 is disposed on the mounting surface 131a and exposed by the insulating protection layer 133 a. The metal layer 134 is not electrically connected to the

circuit pads

132a, 132b, i.e., the metal layer 134 can be electrically insulated from the

circuit pads

132a, 132b, wherein the metal layer 134 can be used as a grounding pad of the circuit board 130. In addition, the metal layer 134 and the circuit pads 132a may be formed by photolithography (including etching) using the same metal layer.

Referring to fig. 1G, a thermal conductive material 140 is filled in the first through hole 119b and the second through hole 129 b. After the thermal conductive material 140 is filled in the first through hole 119b and the second through hole 129b, the thermal conductive material 140 is located on the circuit board 130 and penetrates through the second chip 120 and the first chip 110, wherein the thermal conductive material 140 sequentially penetrates through the second chip 120 and the first chip 110 from the second surface S22 of the second chip 120 and extends to the circuit board 130.

The thermally conductive material 140 may be an electrical insulator, and the material of the thermally conductive material 140 may include a material with high thermal conductivity, such as graphene (graphene) or other polymer material with high thermal conductivity, so that the thermally conductive material 140 is electrically insulated from the conductive pillar 114. That is, even though the thermal conductive material 140 directly contacts the solder balls B1 and B2 and the circuit pad 113, the thermal conductive material 140 is not electrically connected to the conductive pillars 114, so as to prevent the conductive pillars 114 from being short-circuited.

Before the thermal conductive material 140 is filled in the first through holes 119b and the second through holes 129b, the jig 10 may be disposed on the circuit board 130. The fixture 10 can cover and fix the first chip 110 and the second chip 120 to prevent the first chip 110 and the second chip 120 from moving relatively. Thus, in the subsequent process, the jig 10 can help the thermal conductive material 140 to smoothly fill the first through holes 119b and the second through holes 129 b.

The fixture 10 has a top cover 17, a first wall 18, a second wall 19 and an opening 11, wherein the first wall 18 and the second wall 19 are both annular in shape. The upper cover 17 is connected to the second wall 19 and located on the second wall 19 and the first wall 18. Opening 11 is formed in cover 17 and second wall 19 is located on first wall 18. After the jig 10 covers and fixes the first chip 110 and the second chip 120, the cover 17 covers the second chip 120, and the first wall 18 and the second wall 19 respectively surround the first chip 110 and the second chip 120, wherein the opening 11 exposes the second through hole 129 b. Therefore, the heat conductive material 140 can be filled into the first through holes 119b and the second through holes 129b from the opening 11.

When the heat conductive material 140 fills the first through holes 119b and the second through holes 129b from the opening 11, the heat conductive material 140 has fluidity, so that the heat conductive material 140 can sequentially flow into the second gap G2, the first through hole 119b and the first gap G1 from the second through holes 129b, so that the heat conductive material 140 can fill the first through hole 119b, the second through hole 129b, the first gap G1 and the second gap G2.

Since the thermally conductive material 140 can fill the first gap G1, the thermally conductive material 140 can directly contact the metal layer 134. In addition, in the embodiment shown in fig. 1G, first wall 18 may contact sidewall 119s of first chip 110, and second wall 19 may not contact sidewall 129s of second chip 120, so that flowing heat conduction material 140 can contact sidewall 129s and fill the gap between sidewall 129s and second wall 19. After the thermal conductive material 140 is filled in the first through holes 119b and the second through holes 129b, the jig 10 is removed. The thermally conductive material 140 may be cured by heating before removing the jig 10.

Referring to fig. 1H and fig. 1I, after the thermal conductive material 140 is filled in the first through hole 119b and the second through hole 129b, a molding material 150 (as shown in fig. 1I) is formed on the circuit board 130. In this embodiment, forming the molding material 150 may include the following steps.

Referring to fig. 1H, an initial molding material 150i is formed on the circuit board 130, wherein the initial molding material 150i covers the first chip 110, the second chip 120, the circuit board 130 and the thermal conductive material 140, and covers the first chip 110, the second chip 120 and the thermal conductive material 140. In addition, in the embodiment shown in fig. 1H, the initial molding material 150i completely covers the second surface S22 of the second chip 120 and the second through holes 129b, so that the first chip 110, the second chip 120 and the thermal conductive material 140 are completely sealed in the initial molding material 150 i.

Referring to fig. 1H and fig. 1I, next, a portion of the initial molding material 150I above the second chip 120 is removed to expose the thermal conductive material 140 and form a molding material 150, wherein the molding material 150 disposed on the mounting surface 131a covers the first chip 110 and the circuit board 130 and surrounds the second chip 120. In addition, in the present embodiment, the molding material 150 does not contact the sidewall 129s of the second chip 120, and a portion of the thermal conductive material 140 may fill the gap between the sidewall 129s and the molding material 150, as shown in fig. 1I.

In this embodiment, the method of removing a portion of the initial molding material 150i may be grinding the initial molding material 150 i. Thus, a portion of the initial molding material 150i above the second chip 120 may be removed, so that the thermal conductive material 140 and the second chip 120 are exposed. After grinding the initial molding material 150i, the thermally conductive material 140 may have a top surface 141, and the molding material 150 may have an upper surface 151, wherein the top surface 141, the second surface S22, and the upper surface 151 may be aligned with each other.

Referring to fig. 1J, a heat dissipation portion 160 is formed on the upper surface 151 of the molding material 150, wherein the molding material 150 is located between the heat dissipation portion 160 and the circuit board 130, and the heat dissipation portion 160 may be a heat dissipation adhesive, a heat dissipation pad, or a heat dissipation fin. The heat sink 160 thermally couples to the thermally conductive material 140. Specifically, the heat dissipation portion 160 disposed on the molding material 150 may directly contact the heat conductive material 140 and the second surface S22 of the second chip 120. Alternatively, a heat conductive material (not shown) having a high thermal conductivity, such as a heat paste or a heat dissipation adhesive, may be disposed between the heat dissipation portion 160 and the heat conductive material 140. After the heat sink member 160 is formed, a chip package structure 100 including the wiring board 130, the first chip 110, the second chip 120, the thermal conductive material 140, the molding material 150, and the heat sink member 160 is substantially completed.

Based on the above, the thermal energy of the second chip 120 is conducted to the heat dissipation part 160, and the thermal energy of the first chip 110 is conducted from the heat conductive material 140 to the heat dissipation part 160. Thus, the heat generated by the first chip 110 and the second chip 120 can be rapidly transferred to the heat dissipation portion 160, so that the heat can be dissipated from the heat dissipation portion 160, and the performance degradation of the first chip 110 and the second chip 120 due to the heat accumulation can be avoided. In addition, since the heat conductive material 140 can directly contact the metal layer 134, the heat energy of both the first chip 110 and the second chip 120 can also be conducted to the metal layer 134 to help reduce the heat energy accumulation.

Fig. 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing a chip package structure according to another embodiment of the invention. Referring to fig. 2A, the manufacturing method of the chip package structure of the present embodiment is similar to that of the previous embodiment. Therefore, the differences between the methods for manufacturing the chip package structures of the present embodiment and the foregoing embodiments are mainly described below. The features of the present embodiment that are the same as those of the previous embodiments are not described and illustrated in the drawings.

The main differences between this embodiment and the previous embodiments are: in the above embodiments (see fig. 1A to 1J), the thermal conductive material 140 is filled in the first through hole 119b and the second through hole 129b before the molding material 150 is formed, but in the present embodiment, the thermal conductive material 240 is filled in the first through hole 119b and the second through hole 129b after the molding material 250 is formed. In addition, the heat conductive material 240 of the present embodiment has the same composition as the heat conductive material 140 of the previous embodiment.

Referring to fig. 2A, after the first chip 110 and the second chip 120 are mounted on the circuit board 130, the cover layer 20 is disposed on the second chip 120, wherein the cover layer 20 completely covers all of the second through holes 129b of the second chip 120. The cover layer 20 may be a tape or a patch (st icker), and can be adhered to the second chip 120 to block the subsequent initial molding material 150i from entering the second through holes 129 b.

Next, an initial molding compound 150i is formed on the circuit board 130, wherein the initial molding compound 150i covers the first chip 110, the second chip 120, the circuit board 130 and the cover layer 20. Since the cover layer 20 completely covers all of the second through holes 129b, the initial molding material 150i does not substantially penetrate into the second through holes 129b and the first through holes 119 b.

Referring to fig. 2A and 2B, next, a portion of the initial molding compound 150i located above the second chip 120 is removed to expose the cover layer 20, and a molding compound 250 having an opening 252 is formed, wherein the opening 252 exposes the cover layer 20. The method of removing portions of the initial encapsulation material 150i may be photolithography or laser drilling. When a portion of the initial molding material 150i is removed by photolithography or laser drilling to form the molding material 250, the upper surface 251 of the molding material 250 is not aligned with the second surface S22 of the second chip 120, wherein the height of the upper surface 251 relative to the circuit board 130 may be higher than the height of the second surface S22 relative to the circuit board 130, as shown in fig. 2B. In addition, in the present embodiment, the initial molding material 150i may cover and directly contact the sidewall 129s of the second chip 120 to cover the second chip 120.

Referring to fig. 2B and fig. 2C, after removing a portion of the initial molding material 150i located above the second chip 120, the cover layer 20 is removed to expose the second through hole 129B. Since the cover layer 20 may be an adhesive tape or a patch, the cover layer 20 may be removed by tearing. Referring to fig. 2C, after removing the cover layer 20, the first through hole 119b and the second through hole 129b are filled with a thermal conductive material 240, so that the thermal conductive material 240 on the circuit board 130 penetrates through the second chip 120 and the first chip 110. In addition, since the composition of the thermal conductive material 240 may be the same as that of the thermal conductive material 140, the thermal conductive material 240 in the first through hole 119b and the second through hole 129b may be cured, wherein the method of curing the thermal conductive material 240 may be heating.

Then, a heat dissipation part 160 is formed on the upper surface 251 of the molding material 250, wherein the molding material 250 is located between the heat dissipation part 160 and the circuit board 130, and the heat dissipation part 160 is thermally coupled to the heat conductive material 240. To this end, a chip package structure 200 is substantially completed. Since the upper surface 251 of the molding material 250 is not aligned with the second surface S22 of the second chip 120, the top surface 241 of the thermal conductive material 240 may be aligned with the upper surface 251 but not aligned with the second surface S22, as shown in fig. 2C.

Fig. 3A to 3C are schematic cross-sectional views illustrating a method for manufacturing a chip package structure according to another embodiment of the invention. The manufacturing method of the chip package structure of the present embodiment is similar to that of the chip package structure of the previous embodiment, and the main difference between the two methods is as follows: the heat conductive material 340 (see fig. 3B) of the present embodiment is filled in the first through hole 119B and the second through hole 129B before the first chip 110 and the second chip 120 are mounted on the circuit board 130.

Referring to FIG. 3A, first, a first chip 110 having at least one first via 119b and at least one via 119a is provided. Then, the first through hole 119b and the through hole 119a are subjected to via electroplating to form a first sub-metal pillar 341 in the first through hole 119b and a conductive pillar 114 in the through hole 119 a. Then, the first chip 110 is mounted on the mounting surface 131a of the circuit board 130.

After the first chip 110 is mounted on the circuit board 130, the first sub-metal posts 341 can be thermally coupled to the metal layer 134 of the circuit board 130. For example, the first sub-metal pillars 341 directly contact the metal layer 134. Alternatively, a heat conductive material (not shown) with high thermal conductivity, such as a thermal paste, or a solder, may be disposed between the first sub-metal pillar 341 and the metal layer 134.

Referring to FIG. 3B, a second chip 120 having at least one second via 129B is provided. Then, the second via hole 129b is subjected to via electroplating to form a second sub-metal pillar 342 in the second via hole 129 b. Then, the second chip 120 is mounted on the first chip 110, wherein the second sub-metal posts 342 are aligned with the first sub-metal posts 341, and the second chip 120 may be mounted on the first chip 110 by ultrasonic bonding (ultrasonic bonding) so that the second sub-metal posts 342 are connected to the first sub-metal posts 341, respectively. In addition, in the process of mounting the second chip 120 on the first chip 110, the circuit pads 122 of the second chip 120 can be electrically connected to the conductive pillars 114 by ultrasonic bonding, so that the second chip 120 can be electrically connected to the circuit board 130 through the conductive pillars 114.

Particularly, in the present embodiment, the second chip 120 is mounted on the first chip 110 by ultrasonic bonding. However, in other embodiments, the second chip 120 may also be mounted on the first chip 110 by using a plurality of solder balls B2 (see fig. 1F), wherein the solder balls B2 may connect the circuit pad 122, the conductive pillar 114, the first sub-metal pillar 341 and the second sub-metal pillar 342, so that the circuit pad 122 is electrically connected to the conductive pillar 114, and the first sub-metal pillar 341 is connected to the second sub-metal pillar 342.

After the first chip 110 and the second chip 120 are mounted on the circuit board 130, the first sub-metal pillar 341 and the second sub-metal pillar 342 connected to each other form a metal pillar 34, and the heat conductive material 340 includes at least one metal pillar 34. In addition, the embodiment is exemplified by the heat conductive material 340 including a plurality of metal columns 34, but in other embodiments, the heat conductive material 340 may include only one metal column 34. Therefore, fig. 3B does not limit the number of metal pillars 34 included in the thermally conductive material 340.

The metal pillars 34 penetrate the first chip 110 and the second chip 120 from the first via 119b and the second via 129 b. Since the first through holes 119b are located in the non-functional region P11 and the second through holes 129b are located in the non-functional region P21, the circuit pads 132a of the first chip 110, the second chip 120 and the circuit board 130 are electrically insulated from the thermal conductive material 340. In addition, since the first sub-metal pillar 341 is thermally coupled to the metal layer 134 of the circuit board 130, the metal pillar 34 can also be thermally coupled to the metal layer 134 of the circuit board 130.

Referring to fig. 3C, an encapsulant 350 and a heat sink 160 are sequentially formed, wherein the encapsulant 350 fills a first gap G1 between the first chip 110 and the circuit board 130 and a second gap G2 between the first chip 110 and the second chip 120. To this end, a chip package structure 300 including a molding material 350 and a thermally conductive material 340 is substantially completed. In addition, the molding material 350 may be formed by the same method and material as the molding material 150 shown in fig. 1H and 1I, and thus, will not be described herein.

It should be noted that the above embodiments are illustrated by two chips, i.e., the first chip 110 and the second chip 120. However, in other embodiments, the chip package structure may include three or more chips, so the number of chips included in the chip package structure disclosed in the above embodiments is not limited to two chips.

In summary, since the heat conductive material can penetrate through the plurality of chips (such as the second chip and the first chip), the heat conductive material can conduct the heat energy of the chips to the heat dissipation portion, so that the heat energy of the chips can be conducted to the heat dissipation portion rapidly to help the chips dissipate heat, thereby facilitating the improvement of the performance of the chips.

Although the invention has been described with reference to specific embodiments, it will be apparent to one of ordinary skill in the art that changes and modifications may be made without departing from the spirit and scope of the invention.

Claims

1. A chip package structure, comprising:

the circuit board comprises a main body part and a plurality of circuit connecting pads, wherein the main body part is provided with an installation surface, and the circuit connecting pads are positioned on the installation surface;

the first chip is arranged on the mounting surface and is electrically connected with at least one of the circuit pads;

the second chip is stacked on the first chip, wherein the first chip is positioned between the second chip and the circuit board, and the second chip is provided with a first surface and a second surface opposite to the first surface;

the heat conduction material is positioned on the circuit board and penetrates through the second chip and the first chip, wherein the heat conduction material sequentially penetrates through the second chip and the first chip from the second surface of the second chip and extends to the circuit board;

a molding material disposed on the mounting surface and covering the first chip and the mounting surface, wherein the molding material surrounds the second chip; and

a heat dissipation part disposed on the molding material and thermally coupled to the heat conductive material, wherein the molding material is disposed between the heat dissipation part and the circuit board.

2. The chip package structure of claim 1, wherein the heat spreader directly contacts the thermally conductive material and the second surface of the second chip.

3. The chip package structure according to claim 1, wherein the first chip has at least one first via and the second chip has at least one second via, the thermally conductive material is an electrical insulator and fills the at least one first via, the at least one second via, a first gap and a second gap, wherein the first gap is located between the first chip and the circuit board, and the second gap is located between the first chip and the second chip.

4. The chip package structure according to claim 1, wherein the first chip has at least one first through hole, the second chip has at least one second through hole, the thermally conductive material comprises at least one metal pillar, and the at least one metal pillar penetrates the first chip and the second chip from the at least one first through hole and the at least one second through hole, wherein the first chip, the second chip and the circuit pad are electrically insulated from the thermally conductive material.

5. The chip package structure according to claim 1, further comprising:

at least one conductive column penetrates through the first chip and is positioned between the second chip and the circuit board, wherein the at least one conductive column is electrically connected with at least one of the circuit pads and the second chip, and the heat conduction material is electrically insulated from the at least one conductive column.

6. The chip package structure according to claim 1, wherein the size of the first chip is larger than the size of the second chip.

7. The chip package structure of claim 1, wherein the thermally conductive material has a top surface, and the molding material has an upper surface, and the top surface, the second surface and the upper surface are aligned with each other.

8. A method for manufacturing a chip package structure includes:

installing a first chip and a second chip on a circuit board, wherein the first chip is positioned between the second chip and the circuit board, the first chip is provided with at least one first through hole, and the second chip is provided with at least one second through hole;

filling a heat conduction material into the at least one first through hole and the at least one second through hole;

forming a molding material on the circuit board, wherein the molding material covers the first chip and the circuit board and surrounds the second chip; and

a heat sink portion is formed over the molding material, wherein the heat sink portion is thermally coupled to the thermally conductive material.

9. The method as claimed in claim 8, wherein the thermally conductive material is filled in the at least one first via and the at least one second via before the molding material is formed.

10. The method of manufacturing a chip package structure according to claim 9, further comprising:

before the heat conduction material is filled into the at least one first through hole and the at least one second through hole, a jig is configured on the circuit board, wherein the jig covers and fixes the first chip and the second chip and is provided with an opening for exposing the at least one second through hole, and the heat conduction material is filled into the at least one first through hole and the at least one second through hole from the opening; and

after the thermal conductive material is filled in the at least one first through hole and the at least one second through hole and before the molding material is formed, the jig is removed.

11. The method of claim 9, wherein the step of forming the molding material on the circuit board comprises:

forming an initial molding material on the circuit board, wherein the initial molding material covers the first chip, the second chip, the circuit board and the heat conductive material; and

removing a portion of the initial molding material over the second chip to expose the thermally conductive material.

12. The method of claim 11, wherein the step of removing the portion of the initial molding material over the second chip comprises:

grinding the initial molding material to expose the heat conductive material and the second chip.

13. The method as claimed in claim 8, wherein the thermally conductive material is filled in the at least one first through hole and the at least one second through hole after the molding material is formed.

14. The method of manufacturing a chip package structure according to claim 13, further comprising:

before the heat conducting material is filled into the at least one first through hole and the at least one second through hole, a covering layer is arranged on the second chip, wherein the covering layer completely covers the at least one second through hole;

forming an initial molding material on the circuit board, wherein the initial molding material covers the first chip, the second chip, the circuit board and the cover layer;

removing a portion of the initial molding material over the second chip to expose the cap layer; and

after removing a portion of the initial molding material located above the second chip, the cover layer is removed to expose the at least one second through hole.

15. The method of claim 14, wherein the step of removing the portion of the initial molding material over the second chip comprises photolithography or laser drilling.

16. The method of claim 8, wherein the thermal conductive material is filled in the at least one first through hole and the at least one second through hole before the first chip and the second chip are mounted on the circuit board.

17. The method of claim 16, wherein the filling of the at least one first via and the at least one second via with the thermally conductive material comprises electroplating the at least one first via and the at least one second via to form a first sub-metal pillar in the at least one first via and a second sub-metal pillar in the at least one second via.

18. The method of claim 17, wherein the second sub-metal pillar is aligned with the first sub-metal pillar and the second sub-metal pillar is connected to the first sub-metal pillar during the process of mounting the first chip and the second chip on the circuit board.

19. The method of manufacturing a chip package structure according to claim 8, further comprising:

before the first chip and the second chip are arranged on the circuit board, at least one conductive column penetrating through the first chip is formed.