CN114627072A - Wafer defect extraction method based on neural network - Google Patents
Wafer defect extraction method based on neural network Download PDFInfo
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Abstract
The invention relates to a defect extraction method, in particular to a wafer defect extraction method based on a neural network. The method comprises the steps of mining defect data generated in the historical wafer manufacturing process, extracting the defect data to form a data set, scanning a wafer on a wafer manufacturing production line in real time, generating a series of wafer image data according to a time sequence, inputting the generated series of wafer image data into the data set, outputting the wafer defect condition by adopting a neural network defect detection algorithm, indicating that the wafer image data is matched with elements in the data set, outputting a machine operation stopping signal, and keying out the defect data in the data set. The invention can stop the machine when the defect occurs, thereby avoiding the machine from manufacturing unqualified wafers with larger defects, and can quickly determine the name and the generation reason of the defect of the current wafer, thereby facilitating the subsequent improvement of the machine according to the generation reason.
Description
Technical Field
The invention relates to a defect extraction method, in particular to a wafer defect extraction method based on a neural network.
Background
In the wafer manufacturing process, due to the increased complexity of the manufacturing process, a fusion of a plurality of defective features on the wafer map occurs, defects may be generated in each step of the wafer manufacturing line, and at present, the defects of the wafer are often identified and extracted after the wafer is produced to determine whether the wafer is qualified or not, however, if defects occur in the first steps of the wafer production line, the machine still operates normally, and the defects cannot be found until the wafer is manufactured, so that the produced unqualified wafers cannot be found in time, the waste of resources is easily caused, and the time for extracting the wafer defects is extremely important, in addition, at present, when a wafer defect is extracted, the generation reason of the defect cannot be determined, so that a machine cannot be maintained according to the defect condition, and the wafer manufacturing progress is influenced.
Disclosure of Invention
The present invention is directed to a method for extracting wafer defects based on a neural network, so as to solve the problems mentioned in the background art.
In order to achieve the above object, the present invention provides a method for extracting wafer defects based on a neural network, comprising the following steps:
s1, mining defect data generated in the historical wafer manufacturing process, and extracting the defect data to form a data set;
s2, scanning the wafer in real time on the wafer manufacturing production line, and generating a series of wafer image data according to the time sequence;
s3, inputting the generated series of wafer image data into a data set, and outputting wafer defect conditions by adopting a neural network defect detection algorithm, wherein the wafer defect conditions comprise the following postures:
the first posture indicates that the wafer image data are matched with elements in the data set when the wafer defect is unqualified, a machine operation stop signal is output, and defect data in the data set are keyed out;
and secondly, the wafer defect is qualified, the wafer image data is not matched with elements in the data set, and a normal operation signal of the machine is output.
As a further improvement of the present technical solution, the extracting of the defect data in S1 includes the following steps:
detecting the electrical property of each crystal grain on the historical wafer, and marking out the invalid and normal crystal grains by using an orthogonal seat system to obtain wafer defect data, wherein the expression is as follows:
wherein, XijIs the die located in row i and column j, 0 indicates no die at this location coordinate, 1 indicates a normal die that passed the electrical test, and 2 indicates a failed die that failed the electrical test, through which defect data was identified.
As a further improvement of the technical solution, the expression of the data set is as follows:
I＝(a，b，c)
wherein, I is an element of the data set, a is a defect name, b is a defect feature, and c is a generation reason.
As a further improvement of the present technical solution, the scanning of the wafer in S2 employs an optical microscope.
As a further improvement of the present technical solution, the neural network defect detecting algorithm in S3 includes the following steps:
setting a defect threshold;
selecting a data set as an input sample and a corresponding expectation;
extracting the characteristics of the wafer image data, determining the defect range ratio, sending out a qualified signal if the defect range ratio is smaller than a defect threshold value, sending out an unqualified signal if the defect range ratio is larger than the defect threshold value, cutting off a machine equipment power supply, matching the image data with the expectation of the data set, and outputting elements corresponding to the current wafer defects through a neural network algorithm.
As a further improvement of the technical solution, the neural network defect detection algorithm further includes a defect coordinate positioning algorithm, and the defect coordinate positioning algorithm includes the following steps:
the method comprises the steps of establishing a coordinate axis by taking the center of a wafer image as a circular point, identifying the position of a failure crystal grain on the coordinate axis, dividing the coordinate axis into four quadrant areas, reading the number of the failure crystal grains in each quadrant, wherein the quadrants with a large number represent that the precision of a wafer is lower, and the quadrants with the lower precision of the wafer represent that the defects of the quadrants are more.
As a further improvement of the technical solution, the neural network defect detection algorithm further includes a threshold setting module, and the threshold setting module is used for self-defining a defect threshold.
As a further improvement of the technical solution, the neural network defect detection algorithm further comprises an accuracy identification algorithm, and the accuracy identification algorithm comprises the following steps:
establishing a precision grade range according to the defect proportion;
and receiving a wafer qualified signal, and determining the precision grade of the wafer according to the current defect proportion of the wafer and the grade range.
Compared with the prior art, the invention has the beneficial effects that:
according to the method for extracting the wafer defects based on the neural network, a neural network defect detection algorithm is adopted to output the wafer defect condition, when the wafer defects are unqualified, the matching of wafer image data and elements in a data set is represented, a machine operation stopping signal is output, and defect data in the data set is keyed out.
Drawings
FIG. 1 is a flow chart of the overall structure of embodiment 1 of the present invention;
FIG. 2 is a flowchart of a neural network defect detection algorithm in embodiment 1 of the present invention;
fig. 3 is a schematic view of wafer image segmentation in embodiment 2 of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example 1
Referring to fig. 1-2, the present embodiment provides a method for extracting a wafer defect based on a neural network, including the following steps:
s1, mining defect data generated in the historical wafer manufacturing process, extracting the defect data to form a data set, conveniently and quickly determining the name, defect characteristics and generation reasons of the current defect by referring to the content in the data set when the defect occurs, and saving the judgment time;
further, the extracting of the defect data in S1 includes the following steps:
detecting the electrical property of each crystal grain on the historical wafer, and marking out the invalid and normal crystal grains by using an orthogonal seat system to obtain wafer defect data, wherein the expression is as follows:
wherein, XijIs the die located in row i and column j, 0 indicates no die at this location coordinate, 1 indicates a normal die that passed the electrical test, and 2 indicates a failed die that failed the electrical test, through which defect data was identified.
Specifically, the expression of the data set is as follows:
I＝(a，b，c)
wherein I is an element of the data set, a is a defect name, b is a defect feature, and c is a generation reason;
assume that there are two elements in the dataset, element one: a1, a local system defect, b1, a local area of a failed crystal grain presents a fixed pattern rule, such as dots, rings, scratches, edge rings and the like, and c1, a process influence in the manufacturing process, including gas pollution in the manufacturing process and process abnormality caused by equipment failure; element two: a2 is random defect, b2 is failure crystal grain which is randomly distributed on the whole, c2 is production environment influence in the manufacturing process, including caused by suspended particles and gas pollution in the manufacturing environment, therefore, the defect generation reason of the wafer can be judged according to the distribution state of the failure crystal grain, thereby facilitating subsequent improvement.
S2, scanning a wafer in real time on a wafer manufacturing production line, generating a series of wafer image data according to a time sequence, and conveniently and more intuitively seeing the change of the wafer in the manufacturing process through the wafer image data so as to conveniently see the manufacturing condition;
in S2, the optical microscope is used to scan the wafer, and its working principle is known to those skilled in the art, and the optical microscope uses the optical principle to magnify and image the tiny objects that cannot be distinguished by human eyes, so that people can extract the optical instrument of the fine structure information, and can obtain the image data of the wafer in the manufacturing process, and the wafer image data structure is more accurate.
S3, inputting the generated series of wafer image data into a data set, and outputting wafer defect conditions by adopting a neural network defect detection algorithm, wherein the wafer defect conditions comprise the following postures:
the method has the advantages that the first posture indicates that the wafer is unqualified, the image data of the wafer is matched with elements in the data set, the operation stop signal of the machine is output, and the defect data in the data set is keyed out, so that the machine can be stopped from operating when the defect occurs, the situation that the machine produces unqualified wafers with large defects is avoided, the used resources of the machine are saved, the name and the generation reason of the current wafer defect can be rapidly determined, the machine is conveniently improved according to the generation reason in the follow-up process, and the quality of the follow-up wafer production is improved;
and secondly, the wafer defect is qualified, the wafer image data is not matched with elements in the data set, and a normal operation signal of the machine is output.
Specifically, the neural network defect detection algorithm in S3 includes the following steps:
setting a defect threshold, wherein the defect threshold is a defect range which can be accepted by the wafer, for example, the defect threshold is 5%, the defect ratio in the wafer is not up to the standard if the defect ratio in the wafer exceeds 5%, otherwise, the defect ratio in the wafer is lower than 5%, the use range is met, and the defects of the wafer do not influence the normal use;
selecting a data set as an input sample and a corresponding expectation;
extracting the characteristics of wafer image data, determining the defect range ratio, sending a qualified signal if the defect range ratio is smaller than a defect threshold value, sending an unqualified signal if the defect range ratio is larger than the defect threshold value, cutting a machine equipment power supply, simultaneously matching the image data with the expectation of a data set, outputting an element corresponding to the current wafer defect through a neural network algorithm, ensuring that the cutting machine equipment power supply is stopped in time when the wafer defect occurs, avoiding the waste of machine resources and the continuous processing of subsequent wafers, obtaining the generation reason of the wafer defect through the output element, facilitating the subsequent maintenance and improvement, and improving the wafer manufacturing quality;
the neural network algorithm is an unsupervised learning algorithm, a learning sample (data set) is input, a back propagation algorithm is used for repeatedly adjusting and training the weight and the deviation of the network, the output vector is enabled to be as close as possible to an expected vector, namely, a wafer defect image is as close as possible to the defect characteristics in the data set, and the method specifically comprises the following steps:
(1) initialization, each connection weight and threshold value are randomly given, namely, the wafer defect characteristics in any element in the data set are randomly given.
(2) Calculating the output of each unit of the hidden layer and the output layer by a given input-output mode pair, and outputting the result of the given wafer defect characteristic to the current wafer image characteristic;
(3) calculating new connection weight and threshold value, and calculating the matching degree of the defect characteristics of the output wafer and the image characteristics of the current wafer;
(4) and selecting the next input mode pair, returning to the step 2 for repeated training until the network output error meets the requirement, finishing the training, namely, the wafer defect characteristics accord with the matching of the current wafer image characteristics, the wafer defect characteristics express that the current wafer image characteristics accord with the current elements, and outputting the element contents corresponding to the wafer defects.
When the method is used, image data obtained by scanning a wafer on a wafer manufacturing production line in real time is input into the data set, a neural network defect detection algorithm is adopted to output the wafer defect condition, if the wafer defect is unqualified, the matching of the wafer image data and elements in the data set is indicated, a machine operation stopping signal is output, and defect data in the data set is keyed out.
Example 2
In view of the fact that after the fail signal is outputted, the position of the wafer defect cannot be accurately determined, which results in the range where the machine has problems being unable to be determined, and which results in the disadvantage of subsequent maintenance, the present embodiment is different from embodiment 1 in that, referring to fig. 3, in order to facilitate the determination of the wafer defect distribution, wherein:
the neural network defect detection algorithm further comprises a defect coordinate positioning algorithm, and the defect coordinate positioning algorithm comprises the following steps:
the method comprises the steps of establishing a coordinate axis by taking the center of a wafer image as a circular point, identifying the position of a failure crystal grain on the coordinate axis, dividing the coordinate axis into four quadrant areas, reading the number of the failure crystal grains in each quadrant, wherein the quadrants with a large number represent that the precision of a wafer is lower, and the quadrants with the lower precision of the wafer represent that the defects of the quadrants are more, so that the defect distribution condition can be judged, the key inspection on the relative position of a manufacturing machine is facilitated, and the problem of machine equipment is conveniently and quickly inspected;
specifically, as shown in fig. 3, the wafer image is divided into four quadrants, namely quadrant one (+, +), quadrant two (-, +), quadrant three (-, -) and quadrant four (+, -), by the coordinate axis, and the coordinates of the failed die are identified, for example, the coordinate of the failed die 1 is (-4,6), which indicates that the failed die 1 is in quadrant two, the number of the failed die in each quadrant can be read, and the distribution of the failed die in the four quadrants is determined according to the number.
Example 3
Considering that the acceptable defect ratios of wafers are different when the wafers are used in different applications, the present embodiment is different from embodiment 1 in order to customize the defect threshold, wherein:
the neural network defect detection algorithm further comprises a threshold setting module, wherein the threshold setting module is used for self-defining a defect threshold;
the defect threshold value can be set by a user according to the use of the wafer after manufacturing, the defect range ratio is convenient to determine, and the dynamic range is convenient to compare with the defect threshold value, so that some usable wafers are prevented from being abandoned, and the resource utilization rate is improved.
Example 2
Considering that the generated wafers cannot be classified according to their accuracy and cannot be subjected to grade determination at the time of shipment, this embodiment is different from embodiment 1 in that:
the neural network defect detection algorithm further comprises a precision identification algorithm, and the precision identification algorithm comprises the following steps:
establishing a precision grade range according to the defect proportion;
receiving a wafer qualified signal, and determining the precision grade of the wafer according to the current defect proportion of the wafer and substituting the defect proportion into the grade range;
for example, the accuracy class range is: grade one: 0 to 2 percent; grade two: 2 to 3 percent; grade three: 3-5%, the current wafer defect ratio can be determined to be 2.5%, the precision grade is substituted, the current wafer can be output to be grade two, the wafers can be conveniently screened according to different grades, different purposes can be conveniently distributed, and the practicability is improved.
The foregoing shows and describes the general principles, principal features, and advantages of the invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only preferred examples of the present invention and are not intended to limit the present invention, and that various changes and modifications may be made without departing from the spirit and scope of the present invention, which fall within the scope of the claimed invention. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (8)
1. A wafer defect extraction method based on a neural network is characterized by comprising the following steps:
s1, mining defect data generated in the historical wafer manufacturing process, and extracting the defect data to form a data set;
s2, scanning the wafer in real time on the wafer manufacturing production line, and generating a series of wafer image data according to the time sequence;
s3, inputting the generated series of wafer image data into a data set, and outputting the wafer defect condition by adopting a neural network defect detection algorithm, wherein the wafer defect condition comprises the following postures:
the first posture indicates that the wafer image data are matched with elements in the data set when the wafer defect is unqualified, a machine operation stop signal is output, and defect data in the data set are keyed out;
and secondly, the wafer defect is qualified, the wafer image data is not matched with elements in the data set, and a normal operation signal of the machine is output.
2. The wafer defect extraction method based on the neural network as claimed in claim 1, wherein: the extracting of the defect data in S1 includes the steps of:
detecting the electrical property of each crystal grain on the historical wafer, and marking out the invalid and normal crystal grains by using an orthogonal seat system to obtain wafer defect data, wherein the expression is as follows:
wherein, XijIs the die in row i and column j, with 0 indicating no die at this location coordinate, 1 indicating a normal die that passed the electrical test, and 2 indicating a failed die that failed the electrical test.
3. The wafer defect extraction method based on the neural network as claimed in claim 2, wherein: the data set expression is as follows:
I＝(a，b，c)
wherein, I is an element of the data set, a is a defect name, b is a defect feature, and c is a generation reason.
4. The wafer defect extraction method based on the neural network as claimed in claim 1, wherein: the wafer scanned in S2 is subjected to an optical microscope.
5. The wafer defect extraction method based on the neural network as claimed in claim 1, wherein: the neural network defect detection algorithm in the step S3 includes the following steps:
setting a defect threshold value;
selecting a data set as an input sample and a corresponding expectation;
extracting the characteristics of the wafer image data, determining the defect range ratio, sending out a qualified signal if the defect range ratio is smaller than a defect threshold value, sending out an unqualified signal if the defect range ratio is larger than the defect threshold value, cutting off a machine equipment power supply, matching the image data with the expectation of the data set, and outputting elements corresponding to the current wafer defects through a neural network algorithm.
6. The wafer defect extraction method based on the neural network as claimed in claim 1, wherein: the neural network defect detection algorithm further comprises a defect coordinate positioning algorithm, and the defect coordinate positioning algorithm comprises the following steps:
the center of the wafer image is used as a circular point, a coordinate axis is established, the position of the failed crystal grain on the coordinate axis is identified, the coordinate axis is divided into four quadrant areas, the number of the failed crystal grains in each quadrant is read, the quadrants with larger number indicate that the precision of the wafer is lower, and the quadrants with lower precision of the wafer indicate that the defects of the quadrants are more.
7. The wafer defect extraction method based on the neural network as claimed in claim 1, wherein: the neural network defect detection algorithm further comprises a threshold setting module, and the threshold setting module is used for self-defining the defect threshold.
8. The wafer defect extraction method based on the neural network as claimed in claim 1, wherein: the neural network defect detection algorithm further comprises a precision identification algorithm, and the precision identification algorithm comprises the following steps:
establishing a precision grade range according to the defect proportion;
and receiving a wafer qualified signal, and determining the wafer precision level according to the current wafer defect ratio and substituting the current wafer defect ratio into the level range.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115239719A (en) * | 2022-09-22 | 2022-10-25 | 南昌昂坤半导体设备有限公司 | Defect detection method, system, electronic device and storage medium |
| CN115588626A (en) * | 2022-12-12 | 2023-01-10 | 北京象帝先计算技术有限公司 | Defect mode identification method and device for wafer and storage medium |
| CN116612113A (en) * | 2023-07-17 | 2023-08-18 | 征图新视(江苏)科技股份有限公司 | Multi-image stitching detection method based on wafer |
| CN117523343A (en) * | 2024-01-08 | 2024-02-06 | 信熙缘(江苏)智能科技有限公司 | Automatic identification method for trapezoid defects of wafer back damage |
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2022
- 2022-03-14 CN CN202210246583.0A patent/CN114627072A/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115239719A (en) * | 2022-09-22 | 2022-10-25 | 南昌昂坤半导体设备有限公司 | Defect detection method, system, electronic device and storage medium |
| CN115588626A (en) * | 2022-12-12 | 2023-01-10 | 北京象帝先计算技术有限公司 | Defect mode identification method and device for wafer and storage medium |
| CN115588626B (en) * | 2022-12-12 | 2023-03-24 | 北京象帝先计算技术有限公司 | Defect mode identification method and device for wafer and storage medium |
| CN116612113A (en) * | 2023-07-17 | 2023-08-18 | 征图新视(江苏)科技股份有限公司 | Multi-image stitching detection method based on wafer |
| CN116612113B (en) * | 2023-07-17 | 2023-09-15 | 征图新视(江苏)科技股份有限公司 | Multi-image stitching detection method based on wafer |
| CN117523343A (en) * | 2024-01-08 | 2024-02-06 | 信熙缘(江苏)智能科技有限公司 | Automatic identification method for trapezoid defects of wafer back damage |
| CN117523343B (en) * | 2024-01-08 | 2024-03-26 | 信熙缘(江苏)智能科技有限公司 | Automatic identification method for trapezoid defects of wafer back damage |
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Application publication date: 20220614 |