CN114626536A - Circuit for processing combination optimization problem - Google Patents
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Abstract
The invention discloses a circuit for processing a combinatorial optimization problem, which comprises a global random number generation module, a turnover probability calculation unit, a receiving decision module, a spin updating unit, a Read Only Memory (ROM), a first selector and a plurality of local energy units, wherein the global random number generation module is used for generating a global random number; the output of the local energy unit is connected with the first selector, the output of the first selector and the output of the probability inversion calculation unit are both connected to the receiving decision module, the output of the receiving decision module is respectively connected to the spin updating unit and the local energy unit, the random number generated by the global random number generation module is output to the first selector, the ROM and the spin updating unit, and the output of the spin updating unit and the output of the ROM are both connected to the input of the local energy unit. The invention generally avoids the requirements of the quantum computer on extreme working environment and the problems encountered in the calculation process by a digital-analog mixing method, provides a circuit for solving the problem of combination optimization by simulating an Esinc model, and can be widely applied to the field of circuits.
Description
Technical Field
The invention relates to the field of circuits, in particular to a circuit for processing a combinatorial optimization problem.
Background
In recent years, as the problems of "memory wall" in the traditional von neumann computer architecture become more severe, the limited bandwidth between the processor and the memory has become one of the key bottlenecks for improving the system performance, and the concept of quantum computer has been getting hot. The quantum computer is a system for implementing mathematical and logical operations, processing and storing information by means of quantum mechanical law. A special quantum computer which is firstly introduced by Canada D-Wave company in 2007 and adopts a quantum annealing algorithm as a core principle can utilize quantum dynamics to accelerate and solve the problems which are difficult to solve by a traditional computer, such as complex discrete optimization, constraint satisfaction, combined optimization problems, simulation problems and the like.
Among the above difficulties, the combinatorial optimization problem is the most representative. The combinatorial optimization problem refers to evaluating various combinations in a limited set of objects to eventually find the best combination. Since the number of combinations increases explosively with the number of factors to be considered, it is difficult to find the best answer in a short time using a conventional von neumann type processor.
However, although in the development process of D-Wave quantum computers, the hardware requirements of the required physical devices are continuously reduced along with the continuous improvement of the construction technology and precision of the devices, the improvement of the technology and the reduction of the hardware requirements cannot solve several key problems currently encountered by D-Wave quantum computers:
firstly, ultralow temperature working environment. The D-Wave system must be kept close to absolute zero, isolated from the surrounding environment and shielded from electromagnetic interference, so as to operate in a quantum mechanical mode.
Secondly, full connection cannot be realized. The D-Wave hardware interconnection structure cannot realize coupling higher than two qubits, and the qubits inside the quantum unit are independent from each other, i.e. it is difficult to realize full connection between all qubits, as shown in fig. 1.
And thirdly, quantum decoherence phenomenon. Quantum bits can be interfered by an external environment to generate quantum entanglement, quantum coherence is easily interfered by the quantum entanglement, and collapse is a classical state, so that accuracy of a calculation result is influenced.
Disclosure of Invention
To solve at least some of the technical problems in the prior art, it is an object of the present invention to provide a circuit for handling combinatorial optimization problems.
The technical scheme adopted by the invention is as follows:
a circuit for processing a combinatorial optimization problem comprises a global random number generation module, a turnover probability calculation unit, a receiving decision module, a spin updating unit, a ROM, a first selector and a plurality of local energy units;
the output of the local energy unit is connected with a first selector, the output of the first selector and the output of the probability inversion calculation unit are both connected to a receiving decision module, the output of the receiving decision module is respectively connected to a spin updating unit and the local energy unit, the random number generated by the global random number generation module is output to the first selector, a ROM and the spin updating unit, and the output of the spin updating unit and the output of the ROM are both connected to the input of the local energy unit;
the circuit for processing the combinatorial optimization problem adopts a circuit design Esinc model connection matrix based on digital integration, maps the combinatorial optimization problem to an Esinc model, and finishes the multiplication process of a spinning matrix and a weight matrix in a digital integrated circuit mode, thereby obtaining a local field required by an annealing process through parallel calculation.
Further, the ROM is used to store weight information of connections between spins;
the ROM stores a weight matrix of size N, where N is the total number of spins; each bit of the ROM represents the connection between two spins.
Further, the turnover probability calculation unit comprises a temperature updating unit, a linear approximation unit and a first multiplier;
the output of the temperature updating unit and the output of the linear approximation unit are both connected to the input of a first multiplier, and the output of the first multiplier is connected to the receiving decision module.
Further, the linear approximation unit comprises two linear feedback shift registers and a lookup table;
the temperature updating unit comprises a second selector, a second multiplier and a format conversion circuit, the initial temperature is input into the second selector, the output of the second selector is connected to the input of the second multiplier, the fixed temperature reduction is realized through the second multiplier in each cycle, and the second multiplier is connected with the format conversion circuit for format conversion and then output.
Further, the local energy unit comprises a first inverter, a second inverter, a third selector, a fourth selector and an adder;
reading the weight from the ROM, accessing the weight obtained by reading and the weight processed by the first inverter into two inputs of a third selector, and determining an output result according to the selected spin value to realize the multiplication of the spin value and the weight; adding the multiplied result and the local energy, connecting the added result and the added result passing through the second reverser into two inputs of a fourth selector together to realize the multiplication of the weight and the selected other spin value, and then outputting the multiplied result.
Further, the spin update unit comprises a format converter, a plurality of selectors and a plurality of inverters;
each bit spin has its own path; the random number generated by the random number generation module is a 10-bit binary number, and the decimal number needs to be converted by a format converter to determine the selected spin number.
Furthermore, the circuit is provided with an expansion interface, and a single circuit module can be expanded towards a plurality of circuit modules, so that the problem of larger-scale combined optimization is solved.
Furthermore, a route, a horizontal register group and a vertical shift register group are added in the circuit to realize inter-chip interconnection, so that the size of the Isci matrix is expanded to a larger scale, and the problem of larger-scale combinatorial optimization is solved.
Further, the weights are fully connected, that is, every two spins have a connection relationship therebetween, and there is an effective weight value.
Furthermore, a hardware structure with the functions of selecting and calculating first exists in the circuit, namely, the spin is tried to be randomly selected before each cycle, and then the specific spin is calculated after the selection; rather than first computing each spin and then randomly selecting one of the spins.
The invention has the beneficial effects that: the invention generally avoids the requirements of a quantum computer on extreme working environment and the problems encountered in the calculation process by a digital-analog mixing method, and provides a circuit for solving the problem of combination optimization by simulating an Eschen model.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description is made on the drawings of the embodiments of the present invention or the related technical solutions in the prior art, and it should be understood that the drawings in the following description are only for convenience and clarity of describing some embodiments in the technical solutions of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a qubit unit connection;
FIG. 2 is an overall circuit architecture of a circuit for handling combinatorial optimization problems according to an embodiment of the present invention;
FIG. 3 is a detailed structural diagram of a receiving decision unit according to an embodiment of the present invention;
FIG. 4 is a detailed structural diagram of a linear approximation unit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating a detailed structure of a temperature updating unit according to an embodiment of the present invention;
FIG. 6 is a detailed structural schematic diagram of a local energy unit in an embodiment of the present invention;
FIG. 7 is a diagram illustrating a detailed structure of a spin update unit according to an embodiment of the present invention;
FIG. 8 is an improved simulated annealing algorithm in an embodiment of the present invention;
FIG. 9 is a flow chart of a linear approximation strategy in an embodiment of the present invention;
fig. 10 is a schematic diagram of a circuit for processing combinatorial optimization problems according to an embodiment of the present invention, which is extended from a single module to multiple modules.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention and are not to be construed as limiting the present invention. The step numbers in the following embodiments are provided only for convenience of illustration, the order between the steps is not limited at all, and the execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper, lower, front, rear, left, right, etc., is based on the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the present invention, the meaning of a plurality of means is one or more, the meaning of a plurality of means is two or more, and larger, smaller, larger, etc. are understood as excluding the number, and larger, smaller, inner, etc. are understood as including the number. If the first and second are described for the purpose of distinguishing technical features, they are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless otherwise explicitly limited, terms such as arrangement, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific contents of the technical solutions.
With the rapid development of semiconductor manufacturing technology, attempts have been made to simulate the operating principle of a quantum computer by using a digital integrated circuit method. Various hardware accelerators, hardware solvers that combine optimization problems, have also been proposed for use with these emerging intelligent computer architectures. CMOS-based eosin model annealers are receiving increasing attention from both academic and industrial circles due to their normal operating environment requirements and mature manufacturing technologies. The prior art proposes an accelerator for combinatorial optimization problems, which can implement a fully-connected eosin model with 1024 bits. The system using the architecture can solve the traveler problem of a 32 city, which is 12000 times faster than the simulated annealing program running on a common processor. Another prior art proposed a fully digital near-net annealing processor. The processor adopts an SCA (random Cellular Automata) mathematical model, improves the updating mode of each bit spin, removes redundant calculation based on single-step flip spin, and greatly improves the operation efficiency.
Based on the points, the invention provides a digital processor based on a full-connection Itanium model aiming at the problem of combination optimization. In addition, in order to reduce the possibility that the system is trapped in a local minimum and improve the calculation efficiency, an improved simulated annealing algorithm is also provided. On the basis of improving the algorithm, the corresponding acceleration hardware implementation is described, and the method has the advantages of less computing resources, low power consumption and high iteration efficiency.
As shown in fig. 2, this embodiment provides a circuit for processing a combinatorial optimization problem, which avoids the requirements of a quantum computer on extreme operating environments and problems encountered in a calculation process by using a digital integrated circuit method, and solves the combinatorial optimization problem by simulating an ixing model. The circuit comprises a global random number generation module, a turnover probability calculation unit, a receiving decision module, a spin updating unit, a ROM, a first selector and a plurality of local energy units;
the output of the local energy unit is connected with a first selector, the output of the first selector and the output of the probability inversion calculation unit are both connected to a receiving decision module, the output of the receiving decision module is respectively connected to the spin updating unit and the local energy unit, the random number generated by the global random number generation module is output to the first selector, the ROM and the spin updating unit, and the output of the spin updating unit and the output of the ROM are both connected to the input of the local energy unit.
The circuit adopts a circuit design Esino model connection matrix based on digital integration, and is an architecture for realizing the target function by combining a digital integrated circuit and an Esino model by mapping different types of specific problems onto the Esino model, and the multiplication process of a spinning matrix and a weight matrix is completed in a digital integrated circuit mode, so that a local field required by an annealing process is obtained by parallel calculation.
As an alternative embodiment, as shown in fig. 3, the reception decision module includes a subtractor and a comparator, an output of the selector is connected to a first input terminal of the comparator, an output of the inverse probability calculating unit is connected to a second input terminal of the comparator after passing through the subtractor, and an output of the comparator is used as an output of the reception decision module.
As an alternative embodiment, as shown in fig. 2, the rollover probability calculating unit includes a temperature updating unit, a linear approximation unit, and a first multiplier; the output of the temperature updating unit and the output of the linear approximation unit are both connected to the input of the first multiplier, and the output of the first multiplier is connected to the receiving decision module.
As shown in fig. 4, the Linear approximation unit is composed of two Linear Feedback Shift Registers (LFSRs) (one 11-bit and one 7-bit) and a lookup table.
As shown in fig. 5, the temperature updating unit is composed of a selector, a multiplier and a format conversion circuit, wherein the initial temperature is input to the selector, the output of the selector is connected to the input of the multiplier, the multiplier is used for realizing fixed temperature reduction in each cycle, and the multiplier is connected to the format conversion circuit for carrying out format conversion and then outputting.
As an alternative embodiment, as shown in fig. 6, the local energy unit is composed of an inverter, a selector, and an adder. The weight read from ROM and its output through an inverter are connected to two inputs of selector, and the result of output is determined by the selected spin value, so that the multiplication of spin value and weight is realized. Adding the multiplied result and the local energy, connecting the added result and the added result passing through the next reverser into two inputs of the selector together to realize the multiplication of the weight and the selected other spin value, and then outputting the multiplied result.
As an alternative embodiment, as shown in fig. 7, the spin update unit is composed of a format converter, several selectors, and an inverter. Each bit spin has its own path. The random number generated by the random number generation module is a 10-bit binary number, and the decimal number needs to be converted by a format converter to determine the selected spin number. The selected spins and the turning condition thereof are executed by the method, and the result is finally output.
As an alternative embodiment, the ROM in the circuit is used to store weight information for the connections between spins, i.e. the ROM used stores a weight matrix of size N x N, where N is the total number of spins. Each bit of the ROM represents the connection between two spins, i.e. the weight. The method for storing the weight is beneficial to the circuit to quickly lock the spin to be calculated and the weight value and calculate, and the overall efficiency of the circuit is improved.
Referring to fig. 10, as an alternative implementation, the circuit for processing the combinatorial optimization problem of this embodiment leaves an expansion interface. The single circuit module can be expanded towards the direction of the multiple circuit modules, and then the problem of larger-scale combination optimization is solved.
Referring to fig. 10, as an alternative implementation, modules such as a route, a horizontal shift register set, a vertical shift register set, and the like are added to the circuit of this embodiment to implement inter-chip interconnection, so that the size of the itaxin matrix is expanded to a larger size, and a larger-size combinatorial optimization problem is solved, for example, a 32x 32-size itaxin model calculation matrix can be implemented by using 4 single-chip schemes with a size of 16x 16.
As an optional implementation manner, the weights in the ixing model related in this embodiment are fully connected, that is, each two spins have a connection relationship, and an effective weight value exists, so that the ixing model of the present invention can simulate and solve a combination optimization problem with more conditions and more complex situations.
As an optional implementation, a hardware structure of selecting and calculating first exists in the circuit of this embodiment, that is, before each cycle, an attempt is made to randomly select spins, and then a specific spin is calculated after the selection; rather than first computing each spin and then randomly selecting one of the spins. This improvement can effectively reduce the total amount of computation and make it more possible for the system to jump out of local minima.
When the circuit of the embodiment is used for processing the combinatorial optimization problem, the specific problem can be mapped to the Esinc model by setting the specific weight in the model and the initial state of each formula, and then the circuit is used for solving the problem. When the model reaches the state with the lowest energy, the solution at the moment is the optimal solution of the problem.
The following explains the isooctane model and its calculation process in detail in this embodiment.
The isooctyl model was originally proposed to explain the phase transition of ferromagnetic materials, i.e. the phenomenon that the magnet loses its magnetic properties when heated above a certain critical temperature, and shows magnetic properties when cooled below the critical temperature. The transition between the two phases, magnetic and non-magnetic, is a continuous phase transition (also called a second-order phase transition). The Esinon model assumes that a ferromagnetic substance is composed of a stack of regularly arranged small needles (spins), each of which has only two directions (spin directions). The adjacent small magnetic needles interact through energy constraint, and the magnetic random transition (up to down or vice versa) occurs due to the interference of environmental thermal noise. The size of fluctuation is determined by key temperature parameters, the higher the temperature is, the stronger the random fluctuation interference is, the more easily the state of the small magnetic needle is disordered and changed violently, so that the magnetism in the upper direction and the lower direction is mutually counteracted, the whole system disappears the magnetism, if the temperature is very low, the small magnetic needle is relatively quiet, the system is in a state with high energy constraint, the directions of a large number of small magnetic needles are consistent, and the ferromagnetic system shows the magnetism.
And mapping the combinatorial optimization problem to an energy space of an Esin model, gradually reducing the Esin energy in an annealing mode, and when the energy of the whole model reaches the minimum value, obtaining the solution at the moment as the optimal solution of the combinatorial optimization problem.
The energy of the yixin is the value x of i and j per two spinsiAnd xjAnd a weight W between themijThe sum of the products of (a) plus the sum of the local field energies. In which the spin xiTaking 0, 1 or-1, +1, i, j all taking 1-n, WijThe connection weight of the spin ith and jth times is obtained. The local field is the variable for which each spin is affected by the external field.
If a spin flips, the total energy after flipping changes to the product of the local field and the flipped spin value. To determine whether the spins can flip, the probability of acceptance is calculated using the Gibbs sampling criterion. The gibbs sampling probability is determined by the temperature and the random number:
and T is the temperature in the annealing process, and the random number generated by the random number generation module is used as noise r and is compared with the acceptance probability of the result to determine whether the spin can be used as a candidate for overturning in the descending cycle.
The process of solving the combinatorial problem by using the annealing algorithm based on the Esinon model is as follows:
1) mapping the initial problem to an Esinc model, and setting a weight matrix WijAnd the value of the bias matrix bi;
2) initializing parameters including initial temperature, temperature scale coefficient and total iteration step number;
3) the system is annealed to a minimum energy point or a customer accepted value point;
4) the optimal point spin state is collected and converted to a solution to the problem.
The traditional simulated annealing algorithm calculates the energy change of the spin in each circulation of the system one by one, and selects a candidate self-selection according to Metropolis Hasting or Gibbs criterion. This means that for the problem of having N spins, the system must compute N energy changes and corresponding acceptance probabilities, but can only determine one spin that needs to be updated. The computation time increases linearly with the size of the problem to be solved. Another problem is that when the ixing model is iterated until the total energy is low, it is easy to fall into a local optimal solution predicament. I.e., a minimum point is found (but may not be the minimum point of the entire model), the energy in its vicinity is greater than that point, causing the system to erroneously assume that point as the optimal solution for the entire model. To alleviate the above problems, we propose an improved simulated annealing algorithm and a pre-selection scheme. The algorithm details are shown in fig. 8, where M is a set of parameters set according to the problem size and performance specification requirements. The algorithm comprises the following specific steps: first, a corresponding initial state is given according to a specific problem to be solved. And a plurality of Monte Carlo steps are carried out at the same temperature, in each Monte Carlo step, all spins are randomly extracted and calculated, and the extraction and calculation results are judged. If the inversion is possible, the local energy (field) of all spins is updated, if the inversion is not possible, the next monte carlo step is performed, after 10 monte carlo steps are completed at the same temperature, the temperature is decreased exponentially, and 10 monte carlo steps are continued. And circulating the steps until the whole annealing algorithm is completed. This method attempts to randomly select spins and then compute a particular spin after selection, rather than computing each spin first. And then randomly select one of the spins. This improvement can effectively reduce the total amount of computation and make it more possible for the system to jump out of local minima.
The circuit of the present embodiment will be described in detail with reference to the following specific embodiments and the accompanying drawings:
as shown in fig. 2, the circuit of the present embodiment is composed of several main parts, namely, a local energy unit, a global random number generation module, a rollover probability calculation unit, a reception decision module, a spin update unit, a ROM, and a selector. The output of the local energy unit is connected with the selector, the output of the selector and the output of the probability inversion calculation unit are connected into the receiving decision unit, the output of the receiving decision unit is connected into the spin updating unit and the local energy unit at the same time, the random number generated by the global random number generation module is connected with the selector, the ROM and the spin updating unit, and the outputs of the spin updating unit and the ROM are connected into the input of the local energy unit.
The implementation of this circuit is as follows:
there are two random number generation modules in the system. When the Monte Carlo iteration starts, the global random number generation module randomly selects a spin through the selector and sends the local energy value h of the spiniStored in the local energy unit for calculation. When the system is just initialized, the problem to be solved is mapped to the model by setting initial values, weights and the like, and the initial value of the local field energy is calculated in advance and input into the circuit from the ROM. This value will be provided to the next step of the receive decision unit. Another random number generation module generates a random number as noise in the flip probability calculation unit to determine whether the selected spin will be updated. The generated random number will be processed by the linear approximation unit and then multiplied by the temperature value of the temperature update unit. The accept decision unit will compare the product result with the selected local energy source and send the result to the spin update unit. The spin update unit will make a selection whether to flip the spin value or not, depending on the outcome value of the receiving decision unit. The detailed circuit of the receiving decision module is shown in fig. 3, the detailed circuit of the linear approximation unit is shown in fig. 4, the detailed circuit of the temperature updating unit is shown in fig. 5, the detailed circuit of the local energy unit is shown in fig. 6, and the detailed circuit of the spin updating unit is shown in fig. 7.
A 10-bit Linear Feedback Shift Register (LFSR) is used in the global random number generation block, which indicates the index of the selector and the address of the ROM, as shown in fig. 2. The ROM used stores a weight matrix of size N x N, where N is the total number of spins. Each bit of the ROM represents the connection between two spins, i.e., the weight. For example, if the selected address is 0b 0100100101101, i.e., decimal 301, then the n bits output will be the weight between the spin 301 and all other addresses. If we draw the ROM bit by bit in order, the graph will be a symmetric matrix.
The random number r in equation (1) is the input to the linear approximation unit. Because we want the random numbers r to be evenly distributed between 0 and 1, the simplest way to generate standard 32-bit single precision floating point format random numbers is to use a 23-bit linear feedback shift register, since the upper 8 bits simply represent the polarity of the number. Only the fractional part of r needs to be implemented with 23 registers and 26 look-up tables. The subsequent floating-point number computation process is still relatively complex. To reduce computational complexity, we expand the range of values of r from (0, 1) to (0, 2047). Thus, the value of the random r can be implemented by an 11-bit linear feedback shift register and another 7-bit linear feedback shift register with a single sign bit, as shown in FIG. 4.
The calculation of the random number r flip probability function comprises a series of complex reciprocal, subtraction and logarithm calculations. Although it is not difficult to build a full floating-point computing architecture, the explosive increase in hardware resource utilization can significantly reduce the operating efficiency of the circuit compared to integer computing. To reduce the amount of computation, a four-segment linear approximation method is used herein to implement the function. Both the input and output of the linear approximation are extended to 4096 to convert floating point calculations to integer calculations. As mentioned above, only half of the function transfer curve needs to be approximated as a straight line, since the other half is determined only by the sign bit. That is, the sign bit of r is retained until the calculation result of the probability function is inverted. There are many ways to implement linear approximations in hardware, as shown in FIG. 9. The method described in fig. 9(a) is: after the random number is generated, the random number is sent to a ROM which stores the corresponding calculation result in advance as an address signal. The approach depicted in fig. 9(b) is a compromise of (a): and (3) processing the obtained random numbers in a segmented manner, wherein each segment corresponds to a linear approximate linear function, and the segmented result is subjected to multiplication and addition calculation of a fixed coefficient to obtain a corresponding calculation result. The method of fig. 9(c) is: after the random number is generated, the corresponding calculation result is directly output through combinational logic. This approach has the advantage of saving space by optimizing the combinational logic circuit, and has the disadvantage that the propagation chain may be longer, which in turn results in a poorly controlled timing. Since the coefficients are constant in the iterative process, the optimization is performed using a linear approximation based on combinational logic, as shown in fig. 9 (c).
To improve the annealing efficiency and implementation cost, the present embodiment proposes an improved simulated annealing algorithm with a pre-selected scheme. Considering spin xjIn the case of flipping, the energy of the system is only due to the spin xjThe influence of the link with other spins, which means that the local field values for all spins do not need to be calculated. The local field hi may not necessarily pass through the entire matrix, but only the corresponding WijTo be updated. For the next cycle, the change in system energy can also be calculated in the local energy unit with the newly updated local field value h by flipping any spin value. A random selector is then added to determine which spins have the corresponding local energy, suitable for updating in this cycle. The method realizes an Esino model with 1024 fully-connected spins by using 1024 local energy units, 1 receiving decision module and 1 turnover probability calculation unit respectively. The improved architecture presented herein places the selection of spins behind the local energy unit, whereas the traditional approach requires the flip probability calculation with 1024 receive decision modules and inversion probability calculation modules.
When the circuit of the embodiment is used for processing the combinatorial optimization problem, the specific problem can be mapped to the Esinc model by setting the specific weight in the model and the initial state of each formula, and then the circuit is used for solving the problem. When the model reaches the state with the lowest energy, the solution at the moment is the optimal solution of the problem.
In the foregoing description of the specification, reference to the description of "one embodiment/example," "another embodiment/example," or "certain embodiments/examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
While the preferred embodiments of the present invention have been illustrated and described, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A circuit for processing a combinatorial optimization problem is characterized by comprising a global random number generation module, a turnover probability calculation unit, a receiving decision module, a spin updating unit, a ROM, a first selector and a plurality of local energy units;
the output of the local energy unit is connected with a first selector, the output of the first selector and the output of the probability inversion calculation unit are both connected to a receiving decision module, the output of the receiving decision module is respectively connected to a spin updating unit and the local energy unit, the random number generated by the global random number generation module is output to the first selector, a ROM and the spin updating unit, and the output of the spin updating unit and the output of the ROM are both connected to the input of the local energy unit;
the circuit for processing the combinatorial optimization problem adopts a circuit design Esinc model connection matrix based on digital integration, maps the combinatorial optimization problem to an Esinc model, and completes the multiplication process of a spin matrix and a weight matrix in a digital integrated circuit mode, thereby obtaining a local field required by an annealing process through parallel calculation.
2. A circuit for handling combinatorial optimization problems as defined in claim 1, wherein said ROM is configured to store weight information of connections between spins;
the ROM stores a weight matrix of size N, where N is the total number of spins; each bit of the ROM represents the connection between two spins.
3. The circuit for processing combinatorial optimization problems of claim 1, wherein the rollover probability calculation unit comprises a temperature update unit, a linear approximation unit, a first multiplier;
the output of the temperature updating unit and the output of the linear approximation unit are both connected to the input of a first multiplier, and the output of the first multiplier is connected to the receiving decision module.
4. A circuit for handling combinatorial-optimization problems according to claim 3, wherein said linear approximation unit comprises two linear feedback shift registers and a look-up table;
the temperature updating unit comprises a second selector, a second multiplier and a format conversion circuit, the initial temperature is input into the second selector, the output of the second selector is connected to the input of the second multiplier, the fixed temperature reduction is realized through the second multiplier in each cycle, and the second multiplier is connected with the format conversion circuit for format conversion and then output.
5. The circuit for processing a combinatorial optimization problem of claim 1, wherein the local energy unit comprises a first inverter, a second inverter, a third selector, a fourth selector, and an adder;
reading the weight from the ROM, accessing the weight obtained by reading and the weight processed by the first inverter into two inputs of a third selector, and determining an output result according to the selected spin value to realize the multiplication of the spin value and the weight; adding the multiplied result and the local energy, connecting the added result and the added result passing through the second inverter into two inputs of a fourth selector together to realize the multiplication of the weight and the selected other spin value, and outputting the multiplied result.
6. The circuit for processing combinatorial-optimization problems of claim 1, wherein the spin update unit comprises a format converter, a plurality of selectors, and a plurality of inverters;
each bit spin has its own path; the random number generated by the random number generation module is a 10-bit binary number, and the decimal number needs to be converted by a format converter to determine the selected spin number.
7. The circuit for processing combinatorial optimization problems of claim 1, wherein the circuit is configured with an expansion interface, and a single circuit module can be expanded towards multiple circuit modules, thereby solving larger-scale combinatorial optimization problems.
8. The circuit for processing combinatorial optimization problems of claim 1, wherein routing, horizontal register set and vertical shift register set are added to the circuit to realize inter-chip interconnection, so that the IshX matrix scale is expanded to a larger scale method to solve the larger scale combinatorial optimization problem.
9. A circuit for handling combinatorial optimization problems as recited in claim 1, wherein the weights are fully connected, i.e. there is a connection between every two spins, and there is an effective weight value.
10. A circuit for handling combinatorial optimization problems as claimed in claim 1, wherein there is a hardware architecture that tries to randomly select spins before each cycle and then computes specific spins after selection; rather than first computing each spin and then randomly selecting one of the spins.
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