CN114626532B - Method and device for reading data based on address, storage medium and electronic device - Google Patents
Method and device for reading data based on address, storage medium and electronic device Download PDFInfo
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Abstract
The invention discloses a method, a device, a storage medium and an electronic device for reading data based on an address, which are applied to a pre-constructed QRAM architecture of a quantum random access memory for accessing data, wherein the QRAM architecture is of a binary tree structure and comprises the following nodes: an N-layer subtree node and a 1-layer leaf node, wherein N is the address length; the method comprises the following steps: determining addresses of quantum state representations distributed and stored in each layer of subtree nodes; and transferring the data stored by the leaf node to the upper layer of subtree node through a first preset quantum line according to the address until the data corresponding to the address is output on the subtree node of the tree root part in the binary tree structure. By utilizing the embodiment of the invention, an effective QRAM architecture is provided, and the functions of storing addresses and reading data in a quantum state form are realized, so that the analysis and verification of a complex quantum algorithm are quickened.
Description
Technical Field
The invention belongs to the technical field of quantum computing, and particularly relates to a method and device for reading data based on an address, a storage medium and an electronic device.
Background
The quantum computer is a kind of physical device which performs high-speed mathematical and logical operation, stores and processes quantum information according to the law of quantum mechanics. When a device processes and calculates quantum information and operates on a quantum algorithm, the device is a quantum computer. Quantum computers are a key technology under investigation because of their ability to handle mathematical problems more efficiently than ordinary computers, for example, to accelerate the time to crack RSA keys from hundreds of years to hours.
The development of an efficient process for retrieving classical/quantum data from a database and converting it into quantum superposition states is one of the most fundamental problems in the practical implementation of quantum information processing. A quantum random access memory (Quantum Random Access Memory, abbreviated QRAM) that stores information and allows superposition queries may play a key role in greatly accelerating quantum algorithms for data analysis, including large data machine learning applications. QRAM is a storage system for quantum computers, which is a quantum version of RAM in classical computers to make quantum stacks containing information by QRAM, which can read the stacked data in the form of stacked addresses, as compared to the RAM which needs to be read one by one. However, the effective physical structure of the current QRAM is still lacking and is not easy to realize and expand, so that analysis and research of a complex quantum algorithm are difficult to a certain extent.
Disclosure of Invention
The application aims to provide a method, a device, a storage medium and an electronic device for reading data based on an address, which are used for solving the defects in the prior art, and can provide an effective QRAM architecture to realize the functions of storing the address and reading the data in a quantum state form, so that the analysis and verification of a complex quantum algorithm are quickened.
An embodiment of the present application provides a method for reading data based on an address, which is applied to a pre-constructed QRAM architecture of a quantum random access memory for accessing data, wherein the QRAM architecture is a binary tree structure and includes the following nodes: an N-layer subtree node and a 1-layer leaf node, wherein N is the address length; the method comprises the following steps:
determining addresses of quantum state representations distributed and stored in each layer of subtree nodes;
and transferring the data stored by the leaf node to the upper layer of subtree node through a first preset quantum line according to the address until the data corresponding to the address is output on the subtree node of the tree root part in the binary tree structure.
Optionally, the subtree node includes: address bits and first data bits, the leaf node comprising: a second data bit for storing data;
The determining the addresses of the quantum state representations stored in each layer of subtree nodes includes:
determining addresses represented by quantum states in address bits distributed and stored in each layer of subtree nodes; wherein a layer of subtree nodes corresponds to a one-bit address.
Optionally, transferring, according to the address, the data stored in the leaf node to a subtree node of a previous layer through a first preset quantum line until the data corresponding to the address is output on the subtree node of the tree root part in the binary tree structure, where the transferring includes:
starting from the leaf node, transferring the data stored by the leaf node to the data bit of the upper layer subtree node through a first preset quantum line;
continuing to transfer the data stored by the data bit of the current layer subtree node to the data bit of the last layer subtree node through the first preset quantum circuit until the data corresponding to the address is obtained and output on the data bit of the subtree node of the tree root part in the binary tree structure; the first preset quantum circuit corresponds to a circuit basic structure in the binary tree structure, and the circuit basic structure comprises: the address bits, data bits of a sub-tree node and the data bits in two sub-nodes of the next layer, and the data transferred to the data bits of the sub-tree node of the previous layer are determined by the address stored by the address bits in the corresponding line basic structure.
Optionally, the method further comprises:
and receiving the address represented by the quantum state, analyzing the address, and storing each bit address distribution of the address to the address bits of the subtree nodes of the corresponding layer.
Optionally, the storing the address distribution of each bit of the address on the address bits of the subtree node of the corresponding layer includes:
for each bit address of the address, starting from k=n, transferring the kth bit address into a first level subtree node at the root of the tree in the binary tree structure;
the method comprises the steps of starting from a first layer subtree node, repeatedly executing the step of transferring a k-th address in a current layer subtree node to a next layer subtree node until the step of transferring the k-th address to an address bit of the k-th subtree node, wherein k is a positive integer and takes values of 1 from N in sequence.
Optionally, the storing the address distribution of each bit of the address on the address bits of the subtree node of the corresponding layer includes:
for each bit address of the address, starting from k=1, transferring the kth bit address into a first level subtree node at the root of the tree in the binary tree structure;
starting from a first layer subtree node, repeatedly executing the step of transferring the k-th address in the current layer subtree node to the next layer subtree node until the k-th address is transferred to the address bit of the (N-k+1) -th layer subtree node, wherein k is a positive integer and is sequentially taken from 1 to N;
And after transferring the k-th bit address in the current layer subtree node to the next layer subtree node, transferring the next-bit address of the k-th bit address from the last layer subtree node of the current layer to the current layer subtree node.
Optionally, the transferring the kth bit address to the first-layer subtree node of the tree root in the binary tree structure includes:
transferring a kth bit address to a data bit of a first-layer subtree node at the root of a tree in the binary tree structure;
the step of transferring the k-th address in the current layer subtree node to the next layer subtree node is performed for a plurality of times from the first layer subtree node until the k-th address is transferred to the address bit of the k-th layer subtree node, including:
starting from a first layer of sub-tree nodes, executing a second preset sub-line corresponding to a line basic structure in the binary tree structure for a plurality of times, so as to transfer a kth bit address stored in data bits of the sub-tree nodes in the line basic structure to data bits in two next layers of sub-nodes until the kth bit address is transferred to the data bits of the kth layer of sub-tree nodes;
and exchanging data bits of the sub-tree node of the k layer with quantum states of address bits of the sub-tree node to transfer the k-th address to the address bits of the sub-tree node of the k layer.
Optionally, after outputting the data corresponding to the address on a subtree node of the tree root part in the binary tree structure, the method further includes:
and performing inverse computation processing on the QRAM architecture to restore the QRAM architecture to an initial state.
Optionally, the data stored in the leaf node is a plurality of digits, wherein the father node of a leaf node corresponding to each digit of the plurality of digits is different;
or a plurality of multi-digits, wherein the same digits of the plurality of multi-digits are continuously stored, and the father node of a leaf node corresponding to each digit of each multi-digit is different.
Yet another embodiment of the present application provides an address-based data reading apparatus applied to a pre-built QRAM architecture of a quantum random access memory for accessing data, wherein the QRAM architecture is a binary tree structure and includes the following nodes: an N-layer subtree node and a 1-layer leaf node, wherein N is the address length; the method comprises the following steps:
the determining module is used for determining addresses of quantum state representations stored in each layer of subtree nodes in a distributed manner;
and the output module is used for transferring the data stored by the leaf node to the upper layer of subtree node through a first preset quantum line according to the address until the data corresponding to the address is output on the subtree node of the tree root part in the binary tree structure.
A further embodiment of the application provides a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of the preceding claims when run.
Yet another embodiment of the application provides an electronic device comprising a memory having a computer program stored therein and a processor configured to run the computer program to perform the method described in any of the above.
Compared with the prior art, the method for reading data based on the address is applied to a pre-constructed QRAM architecture of a Quantum Random Access Memory (QRAM) for accessing data, wherein the QRAM architecture is of a binary tree structure and comprises the following nodes: an N-layer subtree node and a 1-layer leaf node, wherein N is the address length; firstly, determining the addresses represented by quantum states distributed and stored in each layer of subtree nodes, and then transferring the data stored by the leaf nodes to the last layer of subtree nodes through a first preset quantum line according to the addresses until the data corresponding to the addresses are output on the subtree nodes of the tree root part in the binary tree structure. Therefore, by providing an effective QRAM architecture, the functions of storing addresses and reading data in a quantum state form can be realized, so that the analysis and verification of a complex quantum algorithm are quickened.
Drawings
Fig. 1 is a hardware block diagram of a computer terminal according to a method for reading data based on an address according to an embodiment of the present invention;
FIG. 2 is a flow chart of a method for reading data based on an address according to an embodiment of the present invention;
fig. 3 is a schematic diagram of QRAM architecture according to an embodiment of the present invention;
fig. 4 is a schematic diagram of QRAM architecture of 3 subtree layer according to an embodiment of the present invention;
fig. 5 is a schematic diagram of QRAM architecture of another 3 sub-tree layer according to an embodiment of the present invention;
fig. 6 is a schematic diagram of QRAM architecture of a 3-subtree layer according to an embodiment of the present invention
Fig. 7 is a schematic diagram of a basic quantum circuit for implementing a basic circuit structure according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of an address-based data reading device according to an embodiment of the present invention.
Detailed Description
The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
The embodiment of the invention firstly provides a method for reading data based on an address, which can be applied to electronic equipment such as a computer terminal, in particular to a common computer, a quantum computer and the like.
The following describes the operation of the computer terminal in detail by taking it as an example. Fig. 1 is a block diagram of a hardware structure of a computer terminal according to a method for reading data based on an address according to an embodiment of the present application. As shown in fig. 1, the computer terminal may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 104 for storing data, and optionally, a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the configuration shown in fig. 1 is merely illustrative and is not intended to limit the configuration of the computer terminal described above. For example, the computer terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the address-based data reading method in the embodiment of the present application, and the processor 102 executes the software programs and modules stored in the memory 104 to perform various functional applications and data processing, i.e., implement the above-mentioned method. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the computer terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission means 106 is arranged to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module for communicating with the internet wirelessly.
It should be noted that a real quantum computer is a hybrid structure, which includes two major parts: part of the computers are classical computers and are responsible for performing classical computation and control; the other part is quantum equipment, which is responsible for running quantum programs so as to realize quantum computation. The quantum program is a series of instruction sequences written by a quantum language such as the qlunes language and capable of running on a quantum computer, so that the support of quantum logic gate operation is realized, and finally, quantum computing is realized. Specifically, the quantum program is a series of instruction sequences for operating the quantum logic gate according to a certain time sequence.
In practical applications, quantum computing simulations are often required to verify quantum algorithms, quantum applications, etc., due to the development of quantum device hardware. Quantum computing simulation is a process of realizing simulated operation of a quantum program corresponding to a specific problem by means of a virtual architecture (namely a quantum virtual machine) built by resources of a common computer. In general, it is necessary to construct a quantum program corresponding to a specific problem. The quantum program, namely the program for representing the quantum bit and the evolution thereof written in the classical language, wherein the quantum bit, the quantum logic gate and the like related to quantum computation are all represented by corresponding classical codes.
Quantum circuits, which are one embodiment of quantum programs, also weigh sub-logic circuits, are the most commonly used general quantum computing models, representing circuits that operate on qubits under an abstract concept, the composition of which includes qubits, circuits (timelines), and various quantum logic gates, and finally the results often need to be read out by quantum measurement operations.
Unlike conventional circuits, which are connected by metal lines to carry voltage or current signals, in a quantum circuit, the circuit can be seen as being connected by time, i.e., the state of the qubit naturally evolves over time, as indicated by the hamiltonian operator, during which it is operated until a logic gate is encountered.
One quantum program is corresponding to one total quantum circuit, and the quantum program refers to the total quantum circuit, wherein the total number of quantum bits in the total quantum circuit is the same as the total number of quantum bits of the quantum program. It can be understood that: one quantum program may consist of a quantum circuit, a measurement operation for the quantum bits in the quantum circuit, a register to hold the measurement results, and a control flow node (jump instruction), and one quantum circuit may contain several tens to hundreds or even thousands of quantum logic gate operations. The execution process of the quantum program is a process of executing all quantum logic gates according to a certain time sequence. Note that the timing is the time sequence in which a single quantum logic gate is executed.
It should be noted that in classical computation, the most basic unit is a bit, and the most basic control mode is a logic gate, and the purpose of the control circuit can be achieved by a combination of logic gates. Similarly, the way in which the qubits are handled is a quantum logic gate. Quantum logic gates are used, which are the basis for forming quantum circuits, and include single-bit quantum logic gates, such as Hadamard gates (H gates, ada Ma Men), bery-X gates (X gates), bery-Y gates (Y gates), bery-Z gates (Z gates), RX gates, RY gates, RZ gates, and the like; multi-bit quantum logic gates such as CNOT gates, CR gates, iSWAP gates, toffoli gates, and the like. Quantum logic gates are typically represented using unitary matrices, which are not only in matrix form, but also an operation and transformation. The effect of a general quantum logic gate on a quantum state is calculated by multiplying the unitary matrix by the matrix corresponding to the right vector of the quantum state.
QRAM is a storage system for quantum computers, which is a quantum version of RAM in classical computers. The quantum stack containing the information can be fabricated by QRAM, and the stacked data can be read at the stacked address, as compared to RAM which needs to be read one by one. E.g. storing e in address [0, N ] 0 ,e 1 ,…,e n-1 Input address i and output data e by classical RAM i The method comprises the steps of carrying out a first treatment on the surface of the For QRAM of quantum version, the following quantum states can be entered as addresses:
∑|i＞
the following outputs are obtained by QRAM:
∑|i＞|e i ＞
this process of inputting addresses, outputting data may be referred to as a query or access.
QRAM plays a role in the conversion of classical data into quantum data in many quantum algorithms (as an intermediate memory for converting classical data into quantum data), and an important condition for these algorithms to have quantum acceleration is that QRAM cannot perform query for too long. Specifically, if the problem is of size N, the generally acceptable query time should be O (1) or O (polylogN), but not O (N).
There are a number of possible physical implementations of QRAM, such as the optical system proposed earlier, and the acoustic system later. These systems all make it possible to implement QRAM of O (polylogN) access time, which can be considered as an effective scheme. The application provides a QRAM physical architecture designed based on a Nearest-neighbor premise.
Such QRAM architecture does not specify what physical architecture needs to be implemented, for example, in optical, semiconductor quantum dots, superconducting wires, ion traps, etc. physical architectures that have proven to be possible to implement quantum computing.
Referring to fig. 2, fig. 2 is a flow chart of a method for reading data based on an address, which is applied to a pre-constructed QRAM architecture of a quantum random access memory for accessing data, wherein the QRAM architecture is a binary tree structure and includes the following nodes: an N-layer subtree node and a 1-layer leaf node, wherein N is the address length; the address-based data reading method may include the steps of:
s201, determining addresses of quantum state representations distributed and stored in each layer of subtree nodes;
specifically, the subtree node may include: address bits and first data bits, the leaf node may include: the second data bit is used for storing data, and addresses which are distributed and stored in the quantum state representation in the address bits of each layer of subtree nodes are determined; wherein a layer of subtree nodes corresponds to a one-bit address.
In particular, the entire pre-constructed QRAM may exhibit a binary tree structure. As shown in fig. 3, each small box in the figure represents a Qubit (Qubit), which has two types: a, address Qubit; d, i.e., data bit (Data Qubit). One a bit and one D bit in the continuous longitudinal direction form a group, called a node, i.e. a basic unit in a binary tree. All nodes form a binary tree, the root of which is the output part of the QRAM, and each leaf node (the last layer, not shown) records a binary data bit. Basic Block is a two-layer line infrastructure consisting of a node and D bits (called m respectively) in its two children 0 、m 1 ) Constitute a total of 4 bits.
For a QRAM with an address length N (e.g., a typical data word length … … of 32 bits, 64 bits, etc.), the maximum addressing space for the QRAM is from 0 up to 2 N -1. Such QRAM has a total N-layer subtree nodes plus the last 1-layer leaf nodes, which can store up to 2 N A binary bit. Of course, the definition can be amplified in the "byte" (1 byte=8 bit) way of a conventional classical computer, so that for an N-bit QRAM, 2 needs to be stored 3+N Binary bits correspond to a binary tree having a height (number of sub-tree node levels) of 3+ n.
Before the QRAM architecture operates, firstly, an initialization is needed, the initialization is actually a data importing process of the QRAM, the data are imported into leaf nodes one by one, and then the needed corresponding data are read according to the received address.
In practical applications, before determining the addresses represented by the quantum states distributed and stored in each layer of subtree nodes, the addresses represented by the quantum states may also be received and resolved, and then each bit address distribution of the addresses is stored in the address bits of the corresponding layer of subtree nodes.
Specifically, for each bit address of the address, starting from k=n, the kth bit address is transferred to the first-layer subtree node at the root of the tree in the binary tree structure; wherein the kth bit address can be transferred to the data bit of the first layer subtree node;
And starting from the first layer subtree node, repeatedly executing the step of transferring the k-th address in the current layer subtree node to the next layer subtree node until the k-th address is transferred to the address bit of the k-th subtree node, wherein k is a positive integer and takes 1 from N in sequence, so that the propagation of the address is realized.
Or, starting from k=1, transferring the kth bit address to a first-layer subtree node of the tree root part in the binary tree structure; the step of transferring the k-th address in the current layer subtree node to the next layer subtree node is executed for a plurality of times from the first layer subtree node until the k-th address is transferred to the address bit of the (N-k+1) -th layer subtree node, wherein k is a positive integer and the values are sequentially from 1 to N.
Preferably, the next-bit address of the k-th bit address is transferred from the last-layer subtree node of the current layer to the current-layer subtree node immediately after the k-th bit address in the current-layer subtree node is transferred to the next-layer subtree node.
In one implementation, first, individual line base structures in the binary tree structure may be determined, wherein the line base structures include: address bits, data bits of a sub-tree node and data bits in two sub-nodes of the next layer;
Starting from a first layer of sub-tree nodes, executing a second preset sub-line corresponding to the line basic structure for a plurality of times, so as to transfer a kth bit address stored in data bits of the sub-tree nodes in the line basic structure to data bits in two sub-nodes of the next layer until the kth bit address is transferred to the data bits of the k layer of sub-tree nodes;
the data bits of the sub-tree node of the k-th layer are exchanged with the quantum states of the address bits of the sub-tree node to move the k-th address to the address bits of the sub-tree node of the k-th layer.
In practical applications, the equivalent sub-address is issued into the QRAM, which receives and then resolves the address, and then writes the address information in the a bits in the overall architecture. For a binary tree of height N (number of subtree node levels), starting from the tree root, the N-th bit of the N-bit address is transferred into the D-qubit, and the value in the D-bit is transferred into m 0 And m 1 Is a kind of medium. Then, respectively for m 0 Or m 1 Basic Block of D bits to m of the next layer 0 And m 1 The transition is made to the D bit of the last level subtree node, i.e., the nth level, and finally the address data is moved from D to a bit by exchanging A, D values. Next, the transfer of bit N-1 to layer N-1 … … is performed until bit 1 is transferred to layer 1.
Preferably, the process is performed in a staggered manner, and when an address bit has been moved from layer 1 to layer 2, the next address bit is immediately started to move to layer 1, so that the time required for the entire moving step does not exceed the time that the nth address has been moved to layer N.
Exemplary, as shown in FIG. 4, FIG. 4 shows a topology of the QRAM architecture, including layer 3 sub-tree nodes and layer 1 leaf nodes, the qubits in the initial sub-tree nodes may be set to 0 state, m 000 、m 001 ……m 111 For data stored by a leaf node, the leaf node may comprise a data bit (i.e. the second data bit), the kind may be a qubit or a classical bit. Address Register means an Address Register, representing Address bits; data Register means a Data Register representing a Data bit.
Due to the superposition nature of quanta, a quantum state is a superposition of a set of eigenstates, for example: 3-bit quantum state |f>＝b 0 |000>+b 1 |001>+b 2 |010>+b 3 |011>+b 4 |100>+b 5 |101>+b 6 |110>+b 7 |111>Wherein, |000>、|001>、……、|111>Is eigen state, number is 2 to the power of 3，b 0 …b 7 Representing amplitude (probability amplitude) satisfying |b 0 | 2 +|b 1 | 2 +|b 2 | 2 +|b 3 | 2 +|b 4 | 2 +|b 5 | 2 +|b 6 | 2 +|b 7 | 2 ＝1，|>Is a dirac symbol. When the probability amplitude of the other state is 0, i.e. in a certain one of the states.
Let the received quantum state address |f > = |101>, |101> have an amplitude of 1, from right to left, 3 rd bit to 1 st bit. Firstly, transferring the 3 rd bit address 1 to the D bit of the first layer subtree node, executing a second preset quantum circuit which spans the first layer and corresponds to the Basic Block of the second layer, transferring the address 1 to two D bits of the second layer, continuously executing a second preset quantum circuit which spans the second layer and corresponds to the 2 Basic blocks of the third layer, transferring the address 1 to 4D bits of the third layer, and finally exchanging the A, D bit quantum states of the same subtree node by utilizing a SWAP gate or an equivalent quantum logic gate, and moving the address 1 to 4A bits of the third layer, wherein the quantum states of the 4A bits of the third layer are 1 state.
Similarly, the 2 nd address 0 is finally moved to the 2 nd A bits, the 1 st address 1 is finally moved to the 1 st A bits of the 2 nd layers, the result shown in FIG. 5 is finally obtained, and the address |101> is propagated to the A bits of the 1 st to 3 rd layers. Preferably, the propagation process may be performed in a staggered manner, for example, when moving the 3 rd bit address 1 from layer 2 to layer 3, while simultaneously moving the next address bit 0 from layer 1 to layer 2.
S202, transferring the data stored by the leaf nodes to the sub-tree node of the upper layer through a first preset quantum line according to the address until the data corresponding to the address is output on the sub-tree node of the tree root part in the binary tree structure.
Specifically, from the leaf node, the data stored in the leaf node can be transferred to the data bit of the upper layer subtree node through a first preset quantum line;
continuing to transfer the data stored by the data bit of the current layer subtree node to the data bit of the last layer subtree node through the first preset quantum circuit until the data corresponding to the address is obtained and output on the data bit of the subtree node of the tree root part in the binary tree structure;
The first preset quantum circuit corresponds to a circuit basic structure in the binary tree structure, and the circuit basic structure comprises: the address bits, data bits of a sub-tree node and the data bits in two sub-nodes of the next layer, and the data transferred to the data bits of the sub-tree node of the previous layer are determined by the address stored by the address bits in the corresponding line basic structure.
This process may be referred to as data copy, i.e., data copy. At this time, starting from the leaf node of the leaf part, each Basic Block line Basic structure executes a corresponding first preset quantum line, after each layer is executed, the next layer is directly executed, and the function of the first preset quantum line is to transfer data from the child node to the father node. Since the address is stored in the a-bit, the data transfer process for each layer must retain the correct required data. Thus, the D bit to the root subtree node must be the data bit indicated by the address, thereby successfully extracting the data.
Illustratively, continuing to take fig. 5 as an example, address 101 is stored in fig. 5. At this time, two leaf nodes and the subtree node of the upper layer constitute a line basic structure. And simultaneously executing the first preset quantum circuits corresponding to the 4 Basic blocks crossing the third layer and the leaf layer. In the 1 st Basic Block from the top, since A of the parent node is 3 rd bit address 1, data m with 3 rd bit as 1 index in 2 child nodes is obtained 001 Move into D of the father node; similarly, in the 2 nd, 3 rd and 4 th Basic blocks, the moving data is m 011 、m 101 、m 111 Finally, the D bit of the 3 rd layer subtree node reads the data m with 4 subscript 3 rd bit being 1 (corresponding to 3 rd bit address 1 in the written address 101) 001 、m 011 、m 101 、m 111 。
Continuing to execute across the second layer and the third layerAnd the first preset quantum circuits corresponding to the 2 Basic blocks of the layer. In the 1 st Basic Block above, since A of the parent node is the 2 nd address 0, the data m with the subscript 2 nd bit 0 in the 2 child nodes is obtained 001 Move into D of the father node; similarly, in the 2 nd Basic Block, the moving data is m 101 Finally, the D bit of the layer 2 subtree node reads out the data m with 2 subscript bits 2 being 0 (corresponding to the 2 nd bit address 0 in the written address 101) 001 、m 101 。
And finally executing a first preset quantum circuit corresponding to the 1 Basic Block crossing the first layer and the second layer. Wherein, because A of the father node is 1 st bit address 1, the data m with 1 st bit index in 2 child nodes is 1 st bit 101 Move into D of the father node; finally, 2 data m with subscript 2 and bit 1 (corresponding to 1 st address 1 in written address 101) are read from the D bit of the root subtree node of the 1 st layer 101 Thereby realizing quantum state address|101 >Corresponding data m 101 As shown in fig. 6.
In one specific implementation, 2 Basic quantum wires are required in a Basic Block, which are called a sub-wire a (corresponding to a second preset quantum wire) and a sub-wire b (corresponding to a first preset quantum wire).
The sub-line a, as shown in FIG. 7 (a), whose function does not involve the A bit, moves the address data addr in the D bit to m 0 And m 1 Is a kind of medium. Before running this line, m 0 And m 1 The quantum state in (2) is guaranteed to be 0 state. After the line is run, the state in the D bit is guaranteed to be 0 state. Wherein 4 CNOT gates are used in the line, represented in FIG. 7 (a) by the icon on one bit plus a wire connecting to another bit.
The sub-line b, as shown in FIG. 7 (b), has a function of selectively transferring m according to the address data addr of A bits 0 Or m 1 Into the D bits of the upper layer. If A is 0, then m will be through the Toffoli gate 0 Data d (corresponding to subscript 0) 0 Move into the D bits; if A is 1, then m will be through the Toffoli gate 1 Data d (corresponding to subscript 1) 1 Move into D bits. If m is 0 、m 1 Is unchanged, namely: a is 0, move m 0 Into D bits; a is 1, move m 1 Into D bits. The Toffoli gate is shown in fig. 7 (b) with the # -icon on one bit coupled with the connection of the other two bits, the solid indicates the real control, i.e. the quantum gate is implemented when the quantum state of the bit is 1; the open space indicates a dummy control, i.e. the quantum logic gate is implemented when the quantum state of the bit is 0.
In addition, the same functions are preferably implemented by the sub-line c and the sub-line b, as shown in fig. 7 (c), and in contrast, only 1 Toffoli gate, 3 CNOT gates and 2 NOT gates are used, and the relative optimization (Toffoli gate implementation is very complex) can be equivalently replaced. Wherein the # -icon on one bit represents a NOT gate. It should be noted that the Basic quantum circuit construction required by Basic Block is not specifically limited here, and other quantum circuits capable of implementing the functions of the sub-circuit a and the sub-circuit b fall within the protection scope of the present application. The sub-line a needs to be executed for N times after the completion of one-time production, and the required time is 4Nt, wherein t is the time required by the execution of one CNOT gate; completing one data copy requires that sub-line c be performed N times, with the required time being 3nt+nt ', where t' is the time required for one Toffoli gate.
Specifically, in an actual application, after outputting the data corresponding to the address on the subtree node of the tree root part in the binary tree structure, inverse calculation processing may be further performed on the QRAM architecture, so as to restore the QRAM architecture to an initial state.
The whole system architecture takes out the data, but the original state is not recovered yet, and the recovery of the original state is very important, because the query in one quantum algorithm often needs to be executed many times. Therefore, the uncomputing inverse calculation process is to reversely execute the data copy and the generation process, so as to restore the whole system to the initial state. The total calculation time required is N (14t+2t').
Specifically, the data stored in the leaf node includes a plurality of digits, wherein the father node of a leaf node corresponding to each of the plurality of digits is different;
or the data stored by the leaf node comprises a plurality of multi-bit numbers, wherein the same bits of the plurality of multi-bit numbers are continuously stored, and the father node of a leaf node corresponding to each bit of each multi-bit number is different.
For multi-bit data storage and reading, the same architecture as the original architecture can be used, and a new memory storage mode can be adopted. When a plurality of digits are needed to be stored, each digit of the digits can be stored in different places, so that father nodes of leaf nodes corresponding to each digit of the plurality of digits are different; if 1024 64-bit floating point numbers are required to be stored, only all 0 th bits of the 1024 numbers are required to be stored in a centralized manner, and all 1 st bits are required to be stored in a centralized manner … … so that the father node of a leaf node corresponding to each bit of each multi-bit number is different.
When reading, because of the parallel characteristic of quanta, each bit of the multi-bit number is not in the same basic block in the previous log (1024) =10 steps from the last layer node, so that all the wanted numbers are obtained on all the data bits of the log (64) =6 layers, then the data are sequentially fetched, and finally the uncompusting inverse calculation process is completed. Therefore, by storing the data in this way, it is possible to realize parallel processing of all bits of all numbers at the same time, and a certain acceleration effect is achieved with respect to continuous storage. The continuous storage means that the 0 th bit to the last bit of one number are continuously stored, the 0 th bit to the last bit of the other number are continuously stored, and so on.
It can be seen that by proposing an efficient QRAM physical architecture design, the QRAM architecture can be implemented in an ideal noiseless physical system and has planar, nearest neighbor interaction requirements only for the arrangement of qubits. The running time of the QRAM does not exceed the O (log (N)) level, so the requirement of a quantum algorithm can be fully met. And the quantum circuit based on the QRAM only uses the most basic quantum logic gate which can be reasonably realized, thereby realizing the functions of storing addresses and reading data in a quantum state form and accelerating the analysis and verification of a complex quantum algorithm.
Referring to fig. 8, fig. 8 is a schematic structural diagram of an address-based data reading device according to an embodiment of the present invention, which is applied to a pre-constructed QRAM architecture of a quantum random access memory for accessing data, wherein the QRAM architecture is in a binary tree structure and includes the following nodes: an N-layer subtree node and a 1-layer leaf node, wherein N is the address length; the method comprises the following steps:
a determining module 801, configured to determine addresses of quantum state representations stored in each layer of subtree nodes in a distributed manner;
and an output module 802, configured to transfer, according to the address, the data stored in the leaf node to a subtree node of a previous layer through a first preset quantum line until the data corresponding to the address is output on the subtree node of the tree root part in the binary tree structure.
Specifically, the subtree node includes: address bits and first data bits, the leaf node comprising: a second data bit for storing data;
the determining module is specifically configured to:
determining addresses represented by quantum states in address bits distributed and stored in each layer of subtree nodes; wherein a layer of subtree nodes corresponds to a one-bit address.
Specifically, the output module includes:
the data transfer unit is used for transferring the data stored by the leaf node to the data bit of the upper layer of subtree node through a first preset quantum line from the leaf node;
the data output unit is used for continuously transferring the data stored in the data bit of the current layer of subtree node to the data bit of the last layer of subtree node through the first preset quantum circuit until the data corresponding to the address is obtained and output on the data bit of the subtree node of the tree root part in the binary tree structure; the first preset quantum circuit corresponds to a circuit basic structure in the binary tree structure, and the circuit basic structure comprises: the address bits, data bits of a sub-tree node and the data bits in two sub-nodes of the next layer, and the data transferred to the data bits of the sub-tree node of the previous layer are determined by the address stored by the address bits in the corresponding line basic structure.
Specifically, the device further comprises:
and the receiving and storing module is used for receiving the address represented by the quantum state, analyzing the address and storing each bit address distribution of the address to the address bit of the subtree node of the corresponding layer.
Specifically, the receiving and storing module includes:
a first transferring unit, configured to, for each bit address of the address, start from k=n, transfer a kth bit address to a first-level subtree node at a tree root in the binary tree structure;
and the second transferring unit is used for repeatedly executing the step of transferring the k-th address in the current layer subtree node to the next layer subtree node from the first layer subtree node until the k-th address is transferred to the address bit of the k-th layer subtree node, wherein k is a positive integer and takes the value of 1 from N in sequence.
Specifically, the receiving and storing module includes:
a third transferring unit, configured to, for each bit address of the address, start from k=1, transfer a kth bit address to a first-level subtree node at a tree root in the binary tree structure;
a fourth transferring unit, configured to, starting from the first layer subtree node, perform the step of transferring the kth address in the current layer subtree node to the next layer subtree node multiple times until transferring to the address bit of the (N-k+1) th layer subtree node, where k is a positive integer and the values are sequentially taken from 1 to N;
And after transferring the k-th bit address in the current layer subtree node to the next layer subtree node, transferring the next-bit address of the k-th bit address from the last layer subtree node of the current layer to the current layer subtree node.
Specifically, the first transfer unit is specifically configured to:
transferring a kth bit address to a data bit of a first-layer subtree node at the root of a tree in the binary tree structure;
the second transfer unit is specifically configured to:
starting from a first layer of sub-tree nodes, executing a second preset sub-line corresponding to a line basic structure in the binary tree structure for a plurality of times, so as to transfer a kth bit address stored in data bits of the sub-tree nodes in the line basic structure to data bits in two next layers of sub-nodes until the kth bit address is transferred to the data bits of the kth layer of sub-tree nodes;
and exchanging data bits of the sub-tree node of the k layer with quantum states of address bits of the sub-tree node to transfer the k-th address to the address bits of the sub-tree node of the k layer.
Specifically, the device further comprises:
and the inverse calculation module is used for carrying out inverse calculation processing on the QRAM architecture so as to restore the QRAM architecture to an initial state.
Specifically, the data stored in the leaf nodes are a plurality of digits, wherein the father node of a leaf node corresponding to each digit of the plurality of digits is different;
or a plurality of multi-digits, wherein the same digits of the plurality of multi-digits are continuously stored, and the father node of a leaf node corresponding to each digit of each multi-digit is different.
Therefore, by providing an effective QRAM architecture, the functions of storing addresses and reading data in a quantum state form can be realized, so that the analysis and verification of a complex quantum algorithm are quickened.
The embodiment of the invention also provides a storage medium in which a computer program is stored, wherein the computer program is arranged to perform the steps of the method embodiment of any of the above when run.
Specifically, in the present embodiment, the above-described storage medium may be configured to store a computer program for executing the steps of:
s1, determining addresses of quantum state representations distributed and stored in each layer of subtree nodes;
s2, transferring the data stored by the leaf nodes to the upper layer of subtree nodes through a first preset quantum line according to the address until the data corresponding to the address are output on the subtree nodes of the tree root part in the binary tree structure.
Specifically, in the present embodiment, the storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.
An embodiment of the invention also provides an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of the method embodiment of any of the above.
Specifically, the electronic apparatus may further include a transmission device and an input/output device, where the transmission device is connected to the processor, and the input/output device is connected to the processor.
Specifically, in the present embodiment, the above-described processor may be configured to execute the following steps by a computer program:
s1, determining addresses of quantum state representations distributed and stored in each layer of subtree nodes;
s2, transferring the data stored by the leaf nodes to the upper layer of subtree nodes through a first preset quantum line according to the address until the data corresponding to the address are output on the subtree nodes of the tree root part in the binary tree structure.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
Claims (9)
1. A method for reading data based on an address, which is applied to a pre-built QRAM architecture of a Quantum Random Access Memory (QRAM) for accessing data, wherein the QRAM architecture is in a binary tree structure and comprises the following nodes: an N-layer subtree node and a 1-layer leaf node, wherein N is the address length; the method comprises the following steps:
receiving an address represented by a quantum state, analyzing the address, and for each bit address of the address, starting from k=N, transferring the kth bit address to a data bit of a first-layer subtree node at the root of a tree in the binary tree structure;
starting from a first layer of sub-tree nodes, executing a second preset sub-line corresponding to a line basic structure in the binary tree structure for a plurality of times, so as to transfer a kth bit address stored in data bits of the sub-tree nodes in the line basic structure to data bits in two next layers of sub-nodes until the kth bit address is transferred to the data bits of the kth layer of sub-tree nodes; wherein, the circuit basic structure includes: address bits, data bits of a sub-tree node and data bits in two sub-nodes of the next layer;
Exchanging data bits of a subtree node of a k layer with quantum states of address bits of the subtree node to transfer the k-th address to the address bits of the subtree node of the k layer, wherein k is a positive integer and takes 1 from N in sequence;
determining addresses of quantum state representations distributed and stored in each layer of subtree nodes;
and transferring the data stored by the leaf node to the upper layer of subtree node through a first preset quantum line corresponding to the line basic structure in the binary tree structure according to the address until the data corresponding to the address is output on the subtree node of the tree root part in the binary tree structure.
2. The method of claim 1, wherein the subtree nodes comprise: address bits and first data bits, the leaf node comprising: a second data bit for storing data;
the determining the addresses of the quantum state representations stored in each layer of subtree nodes includes:
determining addresses represented by quantum states in address bits distributed and stored in each layer of subtree nodes; wherein a layer of subtree nodes corresponds to a one-bit address.
3. The method according to claim 2, wherein transferring the data stored in the leaf node to the last sub-tree node through the first preset sub-line corresponding to the line basic structure in the binary tree structure according to the address until the data corresponding to the address is output on the sub-tree node of the tree root part in the binary tree structure includes:
Starting from the leaf node, transferring the data stored by the leaf node to the data bit of the upper layer subtree node through a first preset quantum line;
continuing to transfer the data stored by the data bit of the current layer subtree node to the data bit of the last layer subtree node through the first preset quantum circuit until the data corresponding to the address is obtained and output on the data bit of the subtree node of the tree root part in the binary tree structure; wherein the data transferred to the data bit of the upper subtree node is determined by the address stored by the address bit in the corresponding line basic structure.
4. The method according to claim 1, wherein the method further comprises:
and after transferring the k-th bit address in the current layer subtree node to the next layer subtree node, transferring the next-bit address of the k-th bit address from the last layer subtree node of the current layer to the current layer subtree node.
5. The method of claim 1, wherein after outputting the data corresponding to the address on a subtree node of a tree root in the binary tree structure, the method further comprises:
and performing inverse computation processing on the QRAM architecture to restore the QRAM architecture to an initial state.
6. The method of claim 1, wherein the leaf node stores data in a plurality of bits, and wherein a parent node of a leaf node corresponding to each of the plurality of bits is different;
or a plurality of multi-digits, wherein the same digits of the plurality of multi-digits are continuously stored, and the father node of a leaf node corresponding to each digit of each multi-digit is different.
7. An address-based data reading device, which is applied to a pre-built QRAM architecture of a Quantum Random Access Memory (QRAM) for accessing data, wherein the QRAM architecture is in a binary tree structure and comprises the following nodes: an N-layer subtree node and a 1-layer leaf node, wherein N is the address length; the device comprises:
the resolving module is used for receiving the address represented by the quantum state and resolving the address, and for each bit address of the address, starting from k=N, transferring the kth bit address to the data bit of the first layer subtree node at the root of the tree in the binary tree structure;
a transfer module, configured to execute, from a first layer of sub-tree nodes, a second preset sub-line corresponding to a line basic structure in the binary tree structure for multiple times, so as to transfer a kth bit address stored in a data bit of a sub-tree node in the line basic structure to a data bit in two sub-nodes in a next layer until the kth bit address is transferred to the data bit of the kth layer of sub-tree node; wherein, the circuit basic structure includes: address bits, data bits of a sub-tree node and data bits in two sub-nodes of the next layer;
The switching module is used for switching the data bit of the subtree node of the k layer with the quantum state of the address bit of the subtree node so as to transfer the k-th address to the address bit of the subtree node of the k layer, wherein k is a positive integer and takes the value of 1 from N in sequence;
the determining module is used for determining addresses of quantum state representations stored in each layer of subtree nodes in a distributed manner;
and the output module is used for transferring the data stored by the leaf node to the subtree node of the upper layer through a first preset quantum line corresponding to the line basic structure in the binary tree structure according to the address until the data corresponding to the address is output on the subtree node of the tree root part in the binary tree structure.
8. A storage medium having a computer program stored therein, wherein the computer program is arranged to perform the method of any of claims 1 to 6 when run.
9. An electronic device comprising a memory and a processor, characterized in that the memory has stored therein a computer program, the processor being arranged to run the computer program to perform the method of any of the claims 1 to 6.
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| EP21896214.0A EP4254275A4 (en) | 2020-11-30 | 2021-05-26 | Data reading method and apparatus, storage medium and electronic apparatus |
| PCT/CN2021/096095 WO2022110704A1 (en) | 2020-11-30 | 2021-05-26 | Data reading method and apparatus, storage medium and electronic apparatus |
| US18/039,429 US20240095565A1 (en) | 2020-11-30 | 2021-05-26 | Method, Device, Storage Medium and Electronic Device for Data Reading |
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