CN114625323A - Safe NAND flash memory device - Google Patents

Safe NAND flash memory device Download PDF

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Publication number
CN114625323A
CN114625323A CN202210317785.XA CN202210317785A CN114625323A CN 114625323 A CN114625323 A CN 114625323A CN 202210317785 A CN202210317785 A CN 202210317785A CN 114625323 A CN114625323 A CN 114625323A
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flash memory
nand flash
memory device
module
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张体奎
吴涛
韩健
马永坤
李汝峰
王子奇
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/062—Securing storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0647—Migration mechanisms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Quality & Reliability (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The present invention relates to flash memory devices, and more particularly to a secure NAND flash memory device for SLC and MLC flash memory granules; aiming at the problem of private data leakage caused by the fact that after the NAND flash memory executes the operation of remote updating, a large number of invalid pages for storing user data are reserved, the safe NAND flash memory device arranges a page confusion module in firmware, adopts the proposed SLC and MLC page confusion technology, and executes page confusion operation on the invalid pages in a background operation mode, so that malicious and illegal accesses are difficult to acquire the valid user data. The technology adopted by the invention does not change the interaction mode of the existing general NAND flash memory device and the host, does not influence the traditional security enhancement schemes such as data storage encryption and the like, and can be suitable for various storage devices adopting SLC and MLC storage particles so as to solve the security problem of the off-site update of NAND storage.

Description

Safe NAND flash memory device
Technical Field
The present invention relates to flash memory devices, and more particularly, to a secure NAND flash memory device.
Background
One physical block in the NAND flash memory comprises a plurality of physical pages, the data reading and writing operation takes the page as a unit, the erasing operation takes the block as a unit, and the physical block where the page data is located needs to be in an erasing state before the page data is written; because the erasing and writing granularity is different and the erasing times is limited, the NAND Flash adopts a remote updating strategy and uses a Flash Translation Layer (FTL) mapping table to map the logical address into a physical page; when the logical address D performs the page data update, the corresponding physical page P0 in the FTL mapping table is marked as invalid, the target data is written into a physical page P1 in an idle state, and P1 is mapped to the logical address D in the FTL table. The off-site updating strategy enables the NAND flash memory device to have better write operation performance, however, the strategy causes that a large number of invalid pages containing user data exist in a NAND flash memory chip, and the feasibility of illegally and maliciously reading the invalid pages causes greater hidden danger of private data leakage.
Disclosure of Invention
The invention aims to provide a safe NAND flash memory device, which aims to solve the technical problems and solve the problem that the NAND flash memory device has hidden danger of private data leakage due to a remote updating strategy.
In order to achieve the purpose, the invention adopts the following technical scheme:
a kind of safe NAND flash memory apparatus, including host controller, host processor, memory controller, NAND memory chip and firmware, the said host controller is used for setting up the data interaction bridge of host computer and said safe NAND flash memory apparatus, receive the order that the host computer sends, finish state inquiry, data read/write and other control of the said safe NAND flash memory apparatus; the main processor is a core operation unit of the safe NAND flash memory device, loads and executes the firmware, completes initialization of each component in the safe NAND flash memory device, schedules each component to realize storage management internally, and provides data reading, writing and deleting operations externally; the firmware is a software running resource of the safe NAND flash memory device, and the function of the safe NAND flash memory device is realized under the execution of the main processor; the storage controller is used for realizing the management of the secure NAND storage chip; the NAND memory chip is used for storing data.
As a further aspect of the present invention, the firmware includes a host controller driver, a flash translation layer, and a storage controller driver, where the host controller driver is configured to operate the host controller to implement data interaction with a host; the flash translation layer is used for realizing the functions of linear logic address and physical page mapping management, wear leveling management, garbage recovery, invalid page confusion, data reading error correction and the like; the memory controller driver is used for operating the memory controller to realize data interaction with the NAND memory chip.
As a further scheme of the present invention, the flash translation layer includes a command receiving module, a real-time task queue, a background task queue, a task scheduler, an address mapping module, an abrasion balancing module, a garbage collection module, an ECC module, and a page confusion module, where the command receiving module is configured to receive a command sent by a host controller in real time and add the command to the real-time task or the background task queue according to a command type; the real-time task queue is used for storing tasks needing real-time processing; the background task queue stores tasks processed when the main processor is idle; the task scheduler is used for scheduling and executing the real-time task and the task in the background task queue; the address mapping module also comprises an FTL mapping table, and the FTL mapping table is used for mapping the linear logic address into a physical page address by adopting a page mapping method so as to realize the dynamic mapping of the linear logic address and the physical page; the wear leveling module is used for mapping the physical page for the target linear logic address according to the principle of balanced writing of the physical page; when the main processor is idle, the garbage collection module scans physical blocks with a large number of invalid physical pages in a background operation mode, and migrates the valid pages and the erasing blocks in the target physical blocks to realize garbage collection; the ECC module adopts a polar code coding mode and is used for data error correction when NAND page data are read; the page obfuscating module executes page obfuscation operation on an invalid physical page based on a page obfuscating technology, so that data in the page is randomized, and the problem of target page data leakage is technically solved.
Compared with the prior art, the invention has the following advantages: according to the safe NAND flash memory device, page confusion operation is implemented during page updating, so that user data in invalid pages are destroyed, hidden danger of private data leakage in the pages is eliminated, and the safe NAND flash memory device has high data safety characteristic; the adopted page confusion operation runs in the background idle time, so that the time consumption of the data updating operation is less influenced; the adopted technology does not change the interaction mode of the current universal host equipment and the NAND flash memory equipment, does not influence the implementation of the traditional security enhancement schemes such as identity authentication, data storage encryption and the like, and has the universality of application and operation.
Drawings
Fig. 1 is a system configuration diagram of an embodiment of the present invention.
FIG. 2 is a diagram of a firmware architecture for an embodiment of the present invention.
Fig. 3 is a structure diagram of a flash translation layer FTL of the firmware according to the embodiment of the present invention.
FIG. 4 is a distribution diagram of threshold voltages for two states of a type of SLC NAND flash memory.
FIG. 5 is a graph of threshold voltage distribution for four states of a type of MLC-type NAND flash memory.
10 denotes device firmware, 20 denotes a host controller of the device, 30 denotes a host processor of the device, 40 denotes a memory controller of the device, 50 denotes a memory chip of the device, 11 denotes a host controller driver, 12 denotes a flash translation layer FTL, 13 denotes a memory controller driver,
121 denotes a command receiving module, 122 denotes a real-time task queue, 123 denotes a background task queue, 124 denotes a task scheduler, 125 denotes an address mapping module, 126 denotes a wear leveling module, 127 denotes a garbage collection module, 128 denotes an ECC module, and 129 denotes a page obfuscation module.
Detailed Description
The invention is explained in further detail below with reference to the figures and the specific embodiments.
As shown in the figure, the secure NAND flash memory device comprises a host controller, a main processor, a storage controller, a NAND memory chip and firmware, wherein the host controller is used for establishing a data interaction bridge between a host and the secure NAND flash memory device, receiving an instruction sent by the host, and completing state query, data read/write and other control of the secure NAND flash memory device; the main processor is a core operation unit of the safe NAND flash memory device, loads and executes the firmware, completes initialization of each component in the safe NAND flash memory device, schedules each component to realize storage management internally, and provides data reading, writing and deleting operations externally; the firmware is a software running resource of the safe NAND flash memory device, and the function of the safe NAND flash memory device is realized under the execution of the main processor; the storage controller is used for realizing the management of the secure NAND storage chip; the NAND memory chip is used for storing data.
As shown in fig. 2, the firmware includes a host controller driver, a flash translation layer, and a storage controller driver, where the host controller driver is configured to operate the host controller to implement data interaction with a host; the flash translation layer is used for realizing the functions of linear logic address and physical page mapping management, wear leveling management, garbage recovery, invalid page confusion, data reading error correction and the like; the memory controller driver is used for operating the memory controller to realize data interaction with the NAND memory chip.
As shown in fig. 3, the flash translation layer includes a command receiving module, a real-time task queue, a background task queue, a task scheduler, an address mapping module, a wear leveling module, a garbage collection module, an ECC module, and a page confusion module, where the command receiving module is configured to receive a command sent by a host controller in real time and add the command to the real-time task or the background task queue according to a command type; the real-time task queue is used for storing tasks needing real-time processing; the background task queue stores tasks processed when the main processor is idle; the task scheduler is used for scheduling and executing the real-time tasks and the tasks in the background task queue; the address mapping module also comprises an FTL mapping table, and the FTL mapping table is used for mapping the linear logic address into a physical page address by adopting a page mapping method so as to realize the dynamic mapping of the linear logic address and the physical page; the wear leveling module is used for mapping the physical page for the target linear logic address according to the principle of balanced writing of the physical page; the garbage collection module scans physical blocks with a large number of invalid physical pages in a background operation mode when a main processor is idle, and migrates effective pages and erase blocks in a target physical block to realize garbage collection; the ECC module adopts a polar code coding mode and is used for data error correction when NAND page data are read; the page obfuscating module executes page obfuscation operation on an invalid physical page based on a page obfuscating technology, so that data in the page is randomized, and the problem of target page data leakage is technically solved.
The page confusion technical principle of the SLC flash memory used by the embodiment of the invention is as follows:
SLC memory chips store 1 bit of information per memory cell, including both 0 and 1 states. After a physical block is subjected to an erasing operation, all memory cells in the physical block are in a state 1; after a certain memory cell is programmed (data written), its state becomes 0.
For an invalid physical page to be obfuscated, the number of cells in state 1 isN 0Selecting a threshold, and applying an Incremental Step Pulse Programming (ISPP) method to the threshold
Figure DEST_PATH_IMAGE002
Each memory cell performs reprogramming to state 0. Programming is stopped when the number of cells successfully reprogrammed. The reprogramming operation causes the data in the page to be in the 0 and 1 states with a certain randomness, so as to achieve the purpose of data confusion. To reduce the interference of the reprogramming operation on the adjacent pages and ensure the page aliasing effect, the memory cell needs to be set properly for the specific memory cellp 0The value is obtained.
The MLC flash page confusion technical principle used by the embodiment of the invention is as follows:
MLC flash memory uses four different states to represent 2-bit information per memory cellab(including 11, 10, 00 and 01 states in total), whereinaMost Significant Bit (MSB),
Figure DEST_PATH_IMAGE004
is the Least Significant Bit (LSB). All MSB bits of the same word line are mapped to an upper page of the word line, and all LSB bits are mapped to a lower page of the word line. After the physical block is erased, all memory cells therein are in state 11.
Based on the structural characteristics, the MLC flash page confusion area is executed in three conditions of word confusion, upper page confusion and lower page confusion.
For a wordline to be obfuscated, the number of cells in states 11 and 10 is
Figure DEST_PATH_IMAGE006
Selecting a threshold value for theN 1Each memory cell is reprogrammed to state 00 using the ISPP method. Programming is stopped when the number of memory cells successfully reprogrammed. The reprogramming operation enables the data in the upper page and the lower page of the word to be in the four states with certain randomness, so that the purpose of data confusion is achieved.
For an upper page to be confused, all memory cells in the page in the state 10 are reprogrammed to the state 00 by the ISPP method until all the cells complete the program stop operation. Under the condition that the reprogramming operation does not affect the lower page data of the same word line, all the memory cells with 10 states in the target upper page are programmed to be in the state 00, and the effect of confusing the target page is achieved.
For a lower page to be confused, a threshold value is selected for all pages in the pageN 2Is in state 11 andN 3the memory cells in state 00 are reprogrammed to state 10 and state 01, respectively, using the ISPP method. Programming is stopped when all cells in state 11 have been programmed successfully and the number of cells in state 00 have been reprogrammed successfully. The reprogramming operation obfuscates the data of the target lower page without affecting the data of the upper page of the same worline.
To reduce interference of reprogramming operation on adjacent page while ensuring wordline and page aliasing effect, need to be set properly for specific memory particlesp 1Andp 2the value is obtained.
On the basis of the technical scheme, after the safe NAND flash memory device is powered on and started, the firmware is loaded and all modules are initialized. Read, write and state query and control instructions sent by a host are driven by the host controller and the host controller to reach a command receiving module of the flash translation layer FTL, then are added into the real-time task queue and are executed in a preemptive mode under the scheduling of the task scheduler; and the background task is executed in a priority fusion processing mode under the scheduling of the task scheduler.
On the basis of the technical scheme, when the page write operation task is executed, the address mapping module detects the FTL mapping table. If the physical mapping page P0 corresponding to the target linear logical address D already exists, marking the invalid page by P0, and adding a page obfuscating task taking P0 as a target to the background task queue.
The wear leveling module selects an idle physical page P1 according to a leveling algorithm, and adds a garbage collection task to the background task queue if the number of idle pages reaches an alert threshold; the address mapping module maps the logical address D to a physical page P1, and the memory controller writes target data into a physical page P1, completing the data writing operation.
On the basis of the technical scheme, when the garbage collection task is executed, the garbage collection module selects the target collection physical flash memory block B according to the proportion size of the invalid page in the physical flash memory block. Removing a page obfuscating task of any invalid physical page Px in the flash memory block B from the background task queue; and starting page data migration operation for any effective physical page Py in the flash memory block B. The memory controller performs a block erase operation on the flash block B.
On the basis of the technical scheme, when the page obfuscating task is executed, for the SLC memory chip, page obfuscating operation is executed on each target page in the background task queue according to the SLC obfuscating principle. For an MLC memory chip, combining an upper page and a lower page belonging to the same word in a background task queue into one word, and executing confusion operation according to the MLC flash memory word confusion principle; and respectively executing page aliasing operation on the page which cannot be merged according to the aliasing principle of the upper page and the lower page of the MLC flash memory.
The secure NAND flash memory device of the present invention may be a flash disk, a SATA interface solid state disk, or an M2 interface solid state disk device.
The foregoing is a preferred embodiment of the present invention, and it will be apparent to those skilled in the art that variations, modifications, substitutions and alterations can be made in the embodiment without departing from the principles and spirit of the invention.

Claims (3)

1. A safe NAND flash memory device is characterized by comprising a host controller, a main processor, a storage controller, NAND memory chips and firmware, wherein the host controller is used for establishing a data interaction bridge between a host and the safe NAND flash memory device, receiving an instruction sent by the host and completing state query, data read/write and other control of the safe NAND flash memory device; the main processor is a core operation unit of the safe NAND flash memory device, loads and executes the firmware, completes initialization of each component in the safe NAND flash memory device, schedules each component to realize storage management internally, and provides data reading, writing and deleting operations externally; the firmware is a software running resource of the safe NAND flash memory device, and the function of the safe NAND flash memory device is realized under the execution of the main processor; the storage controller is used for realizing the management of the secure NAND storage chip; the NAND memory chip is used for storing data.
2. The secure NAND flash memory device of claim 1 wherein the firmware comprises a host controller driver, a flash translation layer, and a storage controller driver, the host controller driver being operative to operate the host controller to enable data interaction with a host; the flash translation layer is used for realizing the functions of linear logic address and physical page mapping management, wear leveling management, garbage recovery, invalid page confusion and data reading error correction; the memory controller driver is used for operating the memory controller to realize data interaction with the NAND memory chip.
3. The secure NAND flash memory device of claim 2 wherein the flash translation layer comprises a command receiving module, a real-time task queue, a background task queue, a task scheduler, an address mapping module, a wear leveling module, a garbage collection module, an ECC module, and a page obfuscation module, the command receiving module is configured to receive a command from the host controller in real-time and add to the real-time task or the background task queue according to a type of the command; the real-time task queue is used for storing tasks needing real-time processing; the background task queue stores tasks processed when the main processor is idle; the task scheduler is used for scheduling and executing the real-time task and the task in the background task queue; the address mapping module also comprises an FTL mapping table, and the FTL mapping table is used for mapping the linear logic address into a physical page address by adopting a page mapping method so as to realize the dynamic mapping of the linear logic address and the physical page; the wear leveling module is used for mapping the physical page for the target linear logic address according to the principle of balanced writing of the physical page; the garbage collection module scans physical blocks with a large number of invalid physical pages in a background operation mode when a main processor is idle, and migrates effective pages and erase blocks in a target physical block to realize garbage collection; the ECC module adopts a polar code coding mode and is used for data error correction when NAND page data are read; the page obfuscating module executes page obfuscation operation on an invalid physical page based on a page obfuscating technology, so that data in the page is randomized, and the problem of target page data leakage is technically solved.
CN202210317785.XA 2022-03-29 2022-03-29 Safe NAND flash memory device Withdrawn CN114625323A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116909495A (en) * 2023-09-14 2023-10-20 合肥康芯威存储技术有限公司 Storage device and control method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116909495A (en) * 2023-09-14 2023-10-20 合肥康芯威存储技术有限公司 Storage device and control method thereof
CN116909495B (en) * 2023-09-14 2023-12-15 合肥康芯威存储技术有限公司 Storage device and control method thereof

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Application publication date: 20220614