CN114624932A

CN114624932A - Array substrate, display panel and display device

Info

Publication number: CN114624932A
Application number: CN202210140949.6A
Authority: CN
Inventors: 梁斌; 康报虹
Original assignee: HKC Co Ltd; Changsha HKC Optoelectronics Co Ltd
Current assignee: HKC Co Ltd; Changsha HKC Optoelectronics Co Ltd
Priority date: 2022-02-16
Filing date: 2022-02-16
Publication date: 2022-06-14

Abstract

The utility model belongs to the technical field of show, concretely relates to array substrate, display panel and display device, including substrate base plate and sub-pixel, the sub-pixel includes pixel electrode, data line, scanning line, main transistor and vice transistor, and the pixel electrode includes main electrode and the vice electrode that sets up at interval in the direction of being listed as, and the first pole of main transistor and vice transistor is connected with same data line, and the second pole of main transistor is connected with main electrode, and the second pole of vice transistor is connected with vice electrode; the sub-pixel also comprises a voltage division line and a voltage division transistor, wherein the first pole of the voltage division transistor is connected with the voltage division line, the second pole of the voltage division transistor is connected with the auxiliary electrode, and the grids of the voltage division transistor, the main transistor and the auxiliary transistor are connected with the same scanning line; the orthographic projection of the voltage dividing line on the substrate base plate and the orthographic projection of the main electrode and the auxiliary electrode on the substrate base plate are not overlapped; the aperture opening ratio of the sub-pixels is improved, the transmittance of the display panel is improved, and the display effect is improved.

Description

Array substrate, display panel and display device

Technical Field

The disclosure belongs to the technical field of display, and particularly relates to an array substrate, a display panel and a display device.

Background

With the development of liquid crystal display technology, the size of the display screen is larger and larger, and the poor appearance of color shift of the viewing angle is highlighted by the conventional PSVA (polymer stabilized vertical alignment) pixel adopting 4 domains (4 domains). In order to improve the visual angle performance of the panel, the PSVA pixel with 8 domains (8 domains) is gradually applied to the design of a large-sized television panel, so that 4 domains of a main pixel area and 4 domains of a sub pixel area in the same sub pixel area reduce the difference of the front view/test through the characteristic of the spatial and liquid crystal orientation differentiation, namely, the characteristics of the test color cast and the like are improved.

However, in the 8-domain (8-domain) design, the voltage of the sub-pixels needs to be pulled down, but the traditional pulling down of the voltage of the sub-pixels easily affects the aperture ratio and the transmittance of the sub-pixels.

Disclosure of Invention

The present disclosure is directed to an array substrate, a display panel and a display device, so as to overcome the problem that when the voltage of a sub-pixel is lowered, the aperture ratio and the transmittance of the sub-pixel are affected.

The present disclosure provides an array substrate, including a substrate and a sub-pixel, where the sub-pixel includes a pixel electrode, a data line, a scan line, a main transistor and an auxiliary transistor, the pixel electrode includes a main electrode and an auxiliary electrode that are arranged at an interval in a column direction, first electrodes of the main transistor and the auxiliary transistor are connected to the same data line, a second electrode of the main transistor is connected to the main electrode, and a second electrode of the auxiliary transistor is connected to the auxiliary electrode;

the sub-pixel further comprises a voltage division line and a voltage division transistor, wherein a first pole of the voltage division transistor is connected with the voltage division line, a second pole of the voltage division transistor is connected with the auxiliary electrode, and grid electrodes of the voltage division transistor, the main transistor and the auxiliary transistor are connected with the same scanning line;

and the orthographic projection of the dividing line on the substrate does not overlap with the orthographic projection of the main electrode and the auxiliary electrode on the substrate.

In one exemplary embodiment of the present disclosure,

the scanning lines extend in the row direction and are positioned between the main electrodes and the auxiliary electrodes; the data lines and the dividing lines extend in the column direction.

In one exemplary embodiment of the present disclosure,

the data line and the voltage dividing line are located on opposite sides of the pixel electrode in the row direction.

In one exemplary embodiment of the present disclosure,

the data line and the voltage dividing line are located on the same side of the pixel electrode in the row direction.

In one exemplary embodiment of the present disclosure,

the orthographic projection of the dividing line on the substrate base plate is positioned in the orthographic projection of the data line on the substrate base plate.

In one exemplary embodiment of the present disclosure,

the main electrode, the auxiliary electrode and the voltage dividing line are arranged on the same layer and are positioned on one side of the transistor far away from the substrate;

the voltage division line is connected with the first pole of the voltage division transistor through a through hole.

In one exemplary embodiment of the present disclosure,

the main electrode and the sub electrode each include four slit pattern regions arranged in a row direction and a column direction in an array, in which: two adjacent rows of the slit pattern areas are in mirror symmetry, and two adjacent columns of the slit pattern areas are in mirror symmetry; and/or

The size of the main electrode in the column direction is smaller than the size of the sub-electrode in the column direction.

In one exemplary embodiment of the present disclosure,

the first pole and the second pole of the voltage division transistor are arranged in the same layer as the first pole and the second pole of the main transistor and the auxiliary transistor; and/or

The dividing line, the main electrode and the auxiliary electrode are made of indium tin oxide.

The present disclosure also provides a display panel, which includes the array substrate described in any one of the above, an opposite substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the opposite substrate.

The present disclosure further provides a display device, which includes a backlight module and the display panel, where the display panel is located on the light-emitting side of the backlight module.

The scheme disclosed by the invention has the following beneficial effects:

the voltage of the sub-pixels is reduced by connecting the voltage dividing line with the first electrode of the voltage dividing transistor, and the orthographic projection of the voltage dividing line on the substrate and the orthographic projection of the main electrode and the orthographic projection of the auxiliary electrode on the substrate do not overlap, namely the voltage dividing line does not shield the pixel electrode, so that the aperture opening ratio of the pixel is effectively improved, the penetration ratio of the array substrate is improved, and the display effect is improved.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows, or in part will be obvious from the description, or may be learned by practice of the disclosure.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic structural diagram illustrating voltage dividing lines and data lines on an array substrate on two opposite sides of a pixel electrode according to a first embodiment of the present disclosure;

fig. 2 is a schematic structural diagram illustrating a voltage dividing line and a data line on an array substrate on the same side of a pixel electrode according to a first embodiment of the disclosure;

fig. 3 is a schematic structural diagram illustrating a connection manner of sub-pixels, data lines, scan lines and voltage dividing lines according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram illustrating another connection manner of sub-pixels, data lines, scan lines, and voltage dividing lines according to an embodiment of the disclosure;

FIG. 5 shows a schematic cross-sectional view along A-A of FIG. 1;

FIG. 6 shows a schematic cross-sectional view along B-B of FIG. 2;

FIG. 7 is a schematic structural diagram of a second display panel according to an embodiment of the disclosure;

fig. 8 shows a schematic structural diagram of a third display device according to an embodiment of the disclosure.

Description of reference numerals:

1. a display panel; 10. an array substrate; 101. a substrate base plate; 102. a sub-pixel; 1021. a main pixel region; 10211. a main electrode; 1022. a sub-pixel region; 10221. a secondary electrode; 1023. a data line; 1024. scanning a line; 1025. a main transistor; 1026. a sub-transistor; 1027. dividing lines; 10271. a via hole; 1028. a voltage dividing transistor; 1029. a common electrode; 11. an opposing substrate; 12. a liquid crystal layer; 2. a backlight module is provided.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the disclosure.

The present disclosure is described in further detail below with reference to the figures and the specific embodiments. It should be noted that the technical features involved in the embodiments of the present disclosure described below may be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the drawings are exemplary and intended to be illustrative of the present disclosure, and should not be construed as limiting the present disclosure.

Example one

Referring to fig. 1 or 2, an embodiment of the present disclosure provides an array substrate 10, and the array substrate 10 may include a substrate 101 and a sub-pixel 102.

The substrate 101 may be a glass substrate, but is not limited thereto, and may also be a substrate made of other materials, such as PI (polyimide) material, etc.

In addition, referring to fig. 3 or fig. 4, a plurality of sub-pixels 102 may be arranged and arrayed along the row direction X and the column direction Y; the sub-pixel 102 may include a pixel electrode, a data line 1023, a scan line 1024, a main transistor 1025 and a sub-transistor 1026, as shown in fig. 1 or 2.

Specifically, referring to fig. 1 or fig. 2, each sub-pixel 102 includes a main pixel region 1021 and a sub-pixel region 1022; the main pixel region 1021 includes a main electrode 10211, the sub-pixel region 1022 includes a sub-electrode 10221, the main electrode 10211 and the sub-electrode 10221 may be disposed at the same layer and spaced in the column direction Y, it should be understood that the main electrode 10211 and the sub-electrode 10221 respectively correspond to a pixel electrode of the main pixel region 1021 and a pixel electrode in the sub-pixel region 1022.

More specifically, the main transistor 1025 may include a gate electrode, an active layer, and first and second electrodes disposed at the same layer, and a gate insulating layer may be disposed between the gate electrode and the active layer to insulate the gate electrode and the active layer from each other; the first and second electrodes may be respectively connected to the source and drain doped regions of the active layer, and the connection relationship between the first and second electrodes and the source and drain doped regions of the active layer may be determined according to whether the transistor is N-type or P-type, which is not described in detail herein.

For example, the main transistor 1025 of embodiments of the present disclosure may be of the bottom-gate type, i.e.: the gate may be formed on the substrate base plate 101 first; then, a gate insulating layer is formed on the substrate 101, and the gate insulating layer covers the gate electrode; an active layer is then formed on the side of the gate insulating layer facing away from the substrate 101, i.e.: the active layer is positioned on the side of the gate electrode away from the substrate 101, and the active layer overlaps with the orthographic projection of the gate electrode on the substrate 101, for example, the orthographic projection of the active layer on the substrate 101 can be positioned in the orthographic projection of the gate electrode on the substrate 101; the first pole and the second pole can be formed after the active layer is formed, and at least part of the first pole can be lapped on a doping area of the source and drain doping areas of the active layer; at least a portion of the second pole may overlap another doped region of the source and drain doped regions of the active layer.

It should be noted that the main transistor 1025 in the embodiments of the present disclosure is not limited to the aforementioned bottom gate type, and may also be a top gate type. It should be noted that the gate of the main transistor 1025 can be understood as a control terminal thereof, the first pole can be understood as a first terminal, and the second pole can be understood as a second terminal.

Accordingly, the sub-transistor 1026 can be designed with the same structure as the main transistor 1025, and will not be described herein.

The scan lines 1024 may extend in the row direction X, wherein the scan lines 1024 may be connected to control terminals of the transistors to control the transistors to be turned on or turned off. Alternatively, the scan lines 1024 may be disposed on the same layer as the gates of the transistors and integrally connected; and the scan line 1024 is located between the main pixel region 1021 and the sub-pixel region 1022, that is, the main transistor 1025 and the sub-transistor 1026 share the same scan line 1024, as shown in fig. 1 or fig. 2.

In the present disclosure, "same layer arrangement" refers to a layer structure formed by forming a film layer for forming a specific pattern using the same film formation process and then performing a patterning process once using the same mask plate. That is, one mask (also called as a photomask) is corresponding to one patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and the specific patterns may be at different heights or have different thicknesses. Thereby simplifying the manufacturing process, saving the manufacturing cost and improving the production efficiency.

For example, the scan lines 1024 can be made of metal or alloy material, such as molybdenum, aluminum, titanium, etc., to ensure good conductivity, but not limited thereto, and can also be made of other material with good conductivity.

Referring to fig. 1 and 3, the data line 1023 may extend in the column direction Y, wherein the data line 1023 may be connected to the second terminal of the main transistor 1025 and the second terminal (i.e., the aforementioned second pole) of the sub-transistor 1026 to write a data signal to the second terminal of the main transistor 1025 and the second terminal of the sub-transistor 1026. Alternatively, the data line 1023 may be provided in the same layer as the second pole of the main transistor 1025 and the second pole of the sub transistor 1026, and integrally connected.

The data line 1023 may be made of metal or alloy material, such as molybdenum, aluminum, titanium, etc., to ensure good conductivity, but is not limited thereto, and may be made of other material with good conductivity.

Referring to fig. 1 or fig. 2, as shown in a dotted line frame, a main electrode 10211 in a main pixel region 1021 may be connected to a first terminal (i.e., the aforementioned first pole) of a main transistor 1025, a sub-electrode 10221 in a sub-pixel region 1022 may be connected to a first terminal (i.e., the aforementioned first pole) of a sub-transistor 1026, when the main transistor 1025 and the sub-transistor 1026 are turned on in response to a scan signal provided by a scan line 1024, a data signal provided by a data line 1023 may flow into the first pole of the main transistor 1025 through a second pole of the main transistor 1025, and a data signal provided by a data line 1023 may flow into the first pole of the sub-transistor 1026 through the second pole of the sub-transistor 1026, thereby writing into the main electrode 10211 and the sub-electrode 10221 to deflect liquid crystal molecules between the counter substrate 11 and the array substrate 10, thereby implementing a display function.

The main electrode 10211 and the sub-electrode 10221 of the present disclosure may be transparent electrodes, for example, they may be made of ITO (indium tin oxide) material to improve light transmittance, but are not limited thereto, and they may also be made of other transparent conductive materials, for example: indium Zinc Oxide (IZO), zinc oxide (ZnO), and the like.

For example, main electrode 10211 may be formed after the formation of the first and second electrodes of main transistor 1025, and an insulating layer may be disposed between main electrode 10211 and the metal layer of the first and second electrodes of main transistor 1025, main electrode 10211 may be connected to the first electrode of main transistor 1025 through a via structure penetrating the insulating layer; the sub-electrode 10221 may be formed after the first and second poles of the sub-transistor 1026 are formed, an insulating layer may be disposed between the sub-electrode 10221 and the metal layer where the first and second poles of the sub-transistor 1026 are located, and the sub-electrode 10221 may be connected to the first pole of the sub-transistor 1026 through a via structure penetrating through the insulating layer.

More specifically, referring to fig. 1 or fig. 2, the size of the main electrode 10211 in the column direction Y may be smaller than the size of the sub-electrode 10221 in the column direction Y, so as to increase the difference between the liquid crystal molecule flip angle corresponding to the main electrode 10211 and the liquid crystal molecule flip angle corresponding to the sub-electrode 10221 when aligning, and improve the viewing angle of the liquid crystal display panel 1; however, the size of the main electrode 10211 in the column direction Y may be smaller than or equal to the size of the sub-electrode 10221 in the column direction Y.

As described with reference to fig. 1 or fig. 2, in the sub-pixel 102, each of the main electrode 10211 and the sub-electrode 10221 may include four slit pattern regions arranged in a row direction X and a column direction Y in an array, where the slit pattern regions are slit (slit), and in the four slit pattern regions: two adjacent rows of slit pattern regions are mirror symmetric, two adjacent columns of slit pattern regions are mirror symmetric, so that the main electrode 10211 and the auxiliary electrode 10221 are both 4Domain (4-Domain) designs, that is: in alignment, the liquid crystal molecules corresponding to the main electrode 10211 and the sub-electrode 10221 have 4 directions, that is, the entire sub-pixel 102 adopts an 8-Domain (8Domain) design, so that the 4+4 direction control of the liquid crystal molecules can be realized, thereby further improving the viewing angle.

It should be understood that the main electrode 10211 and the sub-electrode 10221 are not limited to include four slit pattern regions, two slit pattern regions may be provided, and the number of the slit pattern regions of the main electrode 10211 and the sub-electrode 10221 may be different, as the case may be.

Further, as shown in fig. 1 or fig. 2, the sub-pixel 102 further includes a voltage dividing line 1027 and a voltage dividing transistor 1028.

Specifically, referring to fig. 1 or fig. 2, as shown in a dotted line frame, a second pole of the voltage dividing transistor 1028 is connected to the sub-electrode 10221, a first pole of the voltage dividing transistor 1028 is connected to the voltage dividing line 1027 to discharge a part of the voltage of the sub-pixel region 1022 onto the voltage dividing line 1027, so that the display luminance of the main pixel region 1021 and the sub-pixel region 1022 are different, the color shift is improved, and the voltage flowing to the voltage dividing line 1027 is determined by the size of the voltage dividing transistor 1028; in addition, the gates of the voltage dividing transistor 1028, the main transistor 1025, and the sub transistor 1026 are connected to the same scanning line 1024, and the voltage dividing line 1027 is arranged to extend in the column direction Y.

In addition, the orthographic projection of the voltage dividing line 1027 on the substrate base plate 101 is not overlapped with the orthographic projection of the main electrode 10211 and the orthographic projection of the auxiliary electrode 10221 on the substrate base plate 101, that is, the voltage dividing line 1027 does not shield the pixel electrode, so that the aperture opening ratio of the pixel is effectively improved, and the penetration ratio of the array base plate 10 is improved to improve the display effect.

The voltage dividing line 1027 may be located on one side in the row direction of the pixel electrode, and the voltage dividing line 1027 is disposed on the same layer as the main electrode 10211 and the sub-electrode 10221, and located on one side of the main transistor 1025, the sub-transistor 1026, and the voltage dividing transistor 1028 away from the substrate 101, where the position of the voltage dividing line 1027 in the row direction of the pixel electrode may include the following embodiments:

in an alternative embodiment, referring to fig. 1, the data line 1023 and the voltage dividing line 1027 are respectively disposed at two opposite sides of the pixel electrode in the row direction, as shown by the dashed line box in fig. 5, which represents that the data line 1023 and the voltage dividing line 1027 are respectively disposed at two opposite sides of the pixel electrode in the row direction; and the orthographic projection of the voltage dividing line 1027 on the array substrate 10 is located in the orthographic projection of the data line 1023 in the adjacent sub-pixel 102, that is, the voltage dividing line 1027 is located at the upper layer of the data line 1023 in the adjacent sub-pixel 102, as shown in fig. 5, in-plane metal routing in the main pixel area 1021 and the sub-pixel area is reduced, the aperture ratio of the sub-pixel 102 is increased, and further the penetration rate of the array substrate 10 is increased; in addition, the voltage dividing line 1027 is connected to the first electrode of the voltage dividing transistor 1028 to pull down the voltage in the sub-pixel region 1022, so that the deflection angles of the liquid crystal molecules in the main pixel region 1021 and the sub-pixel region 1022 are different, the display luminance of the main pixel region 1021 and the display luminance of the sub-pixel region 1022 are different, the color shift is improved, and the display effect is improved. Note that the data line 1023 and the voltage dividing line 1027 in the same sub-pixel 102 are not located in the same metal layer.

In another alternative embodiment, referring to fig. 2, the data line 1023 and the voltage dividing line 1027 are both located on the same side of the pixel electrode in the row direction, as shown by the dashed line in fig. 6, which represents that the data line 1023 and the voltage dividing line 1027 are located on the same side of the pixel electrode in the row direction; and the orthographic projection of the voltage dividing line 1027 on the substrate base plate 101 is located in the orthographic projection of the data line 1023 on the substrate base plate 101, that is, the voltage dividing line 1027 is located at the upper layer of the data line 1023, as shown in fig. 6, the in-plane metal routing in the main pixel area 1021 and the sub-pixel area is reduced, the aperture ratio of the sub-pixel 102 is increased, and further the penetration rate of the array base plate 10 is increased; in addition, the voltage dividing line 1027 is connected to the first electrode of the voltage dividing transistor 1028 to pull down the voltage in the sub-pixel region 1022, so that the deflection angles of the liquid crystal molecules in the main pixel region 1021 and the sub-pixel region 1022 are different, the display luminance of the main pixel region 1021 and the display luminance of the sub-pixel region 1022 are different, the color shift is improved, and the display effect is improved.

It should be noted that in fig. 5 and 6, an insulating layer may be disposed between the common electrode 1029 and the data line 1023 and between the data line 1023 and the voltage dividing line 1027 to avoid mutual interference and improve the display effect.

In addition, referring to fig. 1 or fig. 2, since the voltage dividing line 1027 is not located in the same metal layer as the first pole of the voltage dividing transistor 1028, the voltage dividing line 1027 is connected to the first pole of the voltage dividing transistor 1028 by means of a via 10271 to communicate with the voltage dividing transistor 1028 to reduce the voltage in the sub-pixel region 1022.

It should be noted that the process of forming via 10271 on voltage divider line 1027 can be designed and completed at the same time as the process of forming via on main electrode 10211 and connecting to the first electrode of main transistor 1025, without adding an additional mask, thereby saving the manufacturing cost.

Wherein, the voltage dividing line 1027 can be made of ITO (indium tin oxide) material; also, the voltage dividing transistor 1028 and the sub-transistor 1026 may share a second pole, as shown in fig. 1 or 2.

In addition, as shown in fig. 1 or fig. 2, in the present embodiment, the sub-pixel may further include a common electrode 1029 disposed opposite to the pixel electrode, it should be understood that the common electrode 1029 may be disposed in an insulating manner with the pixel electrode, and the common electrode 1029 may form a storage capacitor with the pixel electrode.

When the pixel electrode includes a main electrode 10211 and a sub-electrode 10221, the common electrode 1029 may be provided with a main electrode 10211 and a sub-electrode 10221, which are respectively disposed corresponding to the main electrode 10211 and the sub-electrode 10221.

Specifically, the common electrode 1029 may be disposed on the same layer as the scanning line 1024, and since the scanning line 1024 is usually made of a metal material, in order to avoid the influence of the common electrode on the light transmittance, when designing the main electrode and the sub-electrode of the common electrode 1029, the main electrode and the sub-electrode may be disposed as an annular frame, that is, the common electrode 1029 includes a main annular electrode frame and a sub-annular electrode frame; the main ring-shaped electrode frame overlaps with the main electrode 10211 in the thickness direction of the array substrate 10, specifically, the main ring-shaped electrode frame is opposite to the edge of the main electrode 10211 and can form a main storage capacitor; the sub ring electrode frame is opposite to the sub electrode 10221 with an overlap in a thickness direction of the array substrate 10, and particularly, the sub ring electrode frame is opposite to an edge of the sub electrode 10221 and may form a sub storage capacitor.

It should be understood that, when the common electrode 1029 and the scanning line 1024 are disposed in the same layer, the common electrode 1029 and the scanning line 1024 may be formed by the same film forming process, and then formed by one patterning process using the same mask, so that the design may simplify the manufacturing process, save the manufacturing cost, and improve the production efficiency, and in addition, the common electrode 1029 and the scanning line 1024 may be disposed in the same layer, compared with a scheme in which the common electrode is disposed in different layers, so as to reduce the overall thickness of the array substrate, which is beneficial to realizing the lightness and thinness of the display product.

In addition, the common electrode 1029 and the scanning line 1024 are disconnected from each other to ensure that the scanning signal and the common signal are independent from each other, thereby avoiding the situation of shot (mottle and flash) caused by crosstalk between the signals and improving the display effect.

In this embodiment, by designing the main and sub electrodes of the common electrode 1029 as an annular frame, the storage capacitance can be formed at the main electrode 10211 and the sub electrode 10221 while ensuring the aperture ratio.

In addition, in the present embodiment, the corresponding color resists of the same column of sub-pixels 102 are the same, wherein the color resists may include red R, green G, blue B, etc., but not limited thereto, a column of R sub-pixels, a column of G sub-pixels, and a column of B sub-pixels are alternately arranged in the row direction X in sequence, as shown by the sub-pixels indicated by the dashed line boxes in fig. 3 or fig. 4.

Example two

Referring to fig. 7, the second embodiment provides a display panel 1, and the display panel 1 may be a liquid crystal display panel 1. The display panel 1 may include the array substrate 10 described in any of the foregoing embodiments, and the description thereof is not repeated here. The display panel 1 further includes a counter substrate 11 provided to face the array substrate 10, and a liquid crystal layer 12 located between the array substrate 10 and the counter substrate 11.

The opposite substrate 11 may include a glass substrate, and a color resist layer, a BM (black matrix) layer, a common electrode plate, an alignment film, etc. formed on the glass substrate, which will not be described in detail herein.

It should be understood that the color-resist layer may also be disposed on the array substrate 10, as the case may be; further, providing a BM (black matrix) layer on the counter substrate 11 can shield the divided voltage line 1027 from light, shield light leakage due to signal interference, and does not affect the aperture ratio of the sub-pixel 102.

EXAMPLE III

Referring to fig. 8, a third embodiment provides a display device, which includes the display panel 1 described in the second embodiment, and may further include a backlight module 2, wherein the display panel 1 is located on the light emitting side of the backlight module 2.

According to the embodiment of the present disclosure, the specific type of the display device is not particularly limited, and the types of the display devices commonly used in the art may be any, specifically, for example, a liquid crystal display, a mobile device such as a mobile phone and a notebook computer, a wearable device such as a watch, a VR device, and the like, and those skilled in the art may select the display device accordingly according to the specific use of the display device, which is not described herein again.

It should be noted that the display device includes other necessary components and components besides the display panel 1, taking the display as an example, the display device may further include a housing, a main circuit board, a power line, and the like, and those skilled in the art may supplement the display device according to the specific use requirements of the display device, and details are not described herein.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.

In the present disclosure, unless expressly stated or limited otherwise, the terms "mounted," "connected," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral connections; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

In the description herein, references to the description of the terms "some embodiments," "exemplary," etc. mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or exemplary is included in at least one embodiment or exemplary of the present disclosure. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Although embodiments of the present disclosure have been shown and described, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure, and that changes, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present disclosure, and therefore all changes and modifications that are intended to be covered by the claims and the specification of this disclosure are within the scope of the patent disclosure.

Claims

1. An array substrate comprises a substrate and sub-pixels, wherein each sub-pixel comprises a pixel electrode, a data line, a scanning line, a main transistor and an auxiliary transistor, the pixel electrode comprises a main electrode and an auxiliary electrode which are arranged at intervals in the column direction, the first electrodes of the main transistor and the auxiliary transistor are connected with the same data line, the second electrode of the main transistor is connected with the main electrode, and the second electrode of the auxiliary transistor is connected with the auxiliary electrode; the method is characterized in that:

2. The array substrate of claim 1,

3. The array substrate of claim 2,

the data line and the voltage dividing line are located at opposite sides of the pixel electrode in the row direction.

4. The array substrate of claim 2,

5. The array substrate of claim 3 or 4,

6. The array substrate of claim 5,

7. The array substrate of claim 6,

8. The array substrate of claim 7,

9. A display panel comprising the array substrate according to any one of claims 1 to 8, a counter substrate provided in a cell-to-cell relation with the array substrate, and a liquid crystal layer interposed between the array substrate and the counter substrate.

10. A display device comprising a backlight module and the display panel of claim 9, wherein the display panel is located at a light emitting side of the backlight module.