CN114624617A - Low-voltage direct-current power supply monitoring device and monitoring method - Google Patents
Low-voltage direct-current power supply monitoring device and monitoring method Download PDFInfo
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Abstract
The invention belongs to the technical field of power supply monitoring equipment, and particularly relates to a low-voltage direct-current power supply monitoring device which is connected with a plurality of power supplies to be monitored; the device includes: the device comprises a hardware mainboard, a plurality of voltage detection chip arrays (1), a plurality of signal isolation chips (2), a central processing unit (3), a power supply (4) and an RS232 interface circuit (5), wherein the voltage detection chip arrays, the signal isolation chips, the power supply (4) and the RS232 interface circuit are arranged on the hardware mainboard; each power supply to be monitored is connected with a corresponding voltage detection chip array (1), each voltage detection chip array (1) and the input side of a signal isolation chip (2) connected with the voltage detection chip array form an isolation power domain to be monitored, and the output side of the signal isolation chip (2) supplies power, and a central processing unit (3), a power supply (4) and an RS232 interface circuit (5) form a monitoring isolation power domain.
Description
Technical Field
The invention belongs to the technical field of power supply monitoring equipment, and particularly relates to a low-voltage direct-current power supply monitoring device and a monitoring method.
Background
With the continuous development of monitoring, communication and power supply technologies, low-voltage direct-current power utilization equipment is widely popularized. The low-voltage direct-current power supply is widely applied to production and life, such as an LED table lamp and a mobile phone charging lamp, the existing low-voltage direct-current power supply generally converts 220V mains supply into direct current through a full-bridge rectifier circuit, and then performs corresponding voltage stabilizing circuit processing to form required direct current, such as LED street lamps, household LED illuminating lamps, computer hosts and the like which need the processing process. In addition, with the rapid development of automation control technology, various automation control components such as Programmable Logic Controllers (PLCs), signal acquisition sensors, intelligent display screens, photoelectric converters, signal converters, etc. are widely used, and for stable, convenient, safe and fast use, the power supply of these automation control components also mostly adopts a low-voltage dc power supply device.
Therefore, the stable low-voltage direct-current power supply is an important condition for ensuring stable and reliable operation of electronic circuits, low-voltage direct-current electric equipment and automatic control components. In the high-low voltage mixed electronic circuit, if the low-voltage power supply is obtained by converting the high-voltage power supply through a power supply, the current fluctuation of the high-voltage circuit often brings stronger electromagnetic interference to the low-voltage circuit, even the instantaneous voltage output of the low-voltage direct-current power supply can not meet the power consumption requirement, and the reliable working power supply can not be provided for the power consumption equipment.
When the oscilloscope is used for observing the power output, the waveform within a period of time can only be observed, and the power instantaneous voltage drop and recovery caused by random interference are faced, so that long-time observation and analysis cannot be carried out. In addition, the prior art cannot accurately evaluate the working reliability of the low-voltage direct-current power supply of the electronic circuit, cannot judge whether the critical working state occurs or not, cannot continuously monitor the voltage output of the low-voltage direct-current power supply, and cannot count and analyze the monitoring result.
Disclosure of Invention
In order to solve the defects in the prior art, the invention provides a low-voltage direct-current power supply monitoring device which can monitor the output of a low-voltage direct-current power supply in real time so as to evaluate the working reliability of the low-voltage direct-current power supply in an electronic circuit; the device is connected with a plurality of power supplies to be monitored;
the device includes: the device comprises a hardware mainboard, a plurality of voltage detection chip arrays, a plurality of signal isolation chips, a central processing unit, a power supply and an RS232 interface circuit, wherein the voltage detection chip arrays, the signal isolation chips, the central processing unit, the power supply and the RS232 interface circuit are arranged on the hardware mainboard;
each power supply to be monitored is connected with a corresponding voltage detection chip array, each voltage detection chip array and the input side of a signal isolation chip connected with the voltage detection chip array supply power to form an isolation power supply domain to be monitored, and the output side of the signal isolation chip supply power, a central processing unit, a power supply and an RS232 interface circuit form a monitoring isolation power supply domain;
the voltage detection chip array comprises a plurality of detection chips and is used for selecting the number of the required detection chips according to a selection standard, wherein each detection chip carries out real-time monitoring on a power supply to be monitored according to a respective set voltage detection threshold, and when the voltage of the power supply to be monitored is lower than each preset voltage detection threshold, each detection chip outputs a corresponding reset pulse with a falling edge, and the reset pulse can be kept for a period of time;
the signal isolation chip supports multi-voltage multi-channel conversion and is used for carrying out level conversion on reset pulses output by each detection chip connected with the signal isolation chip to obtain corresponding reset pulses which can be identified and processed by the central processing unit and have a falling edge, an output pin of the signal isolation chip is connected to a general input/output pin of the central processing unit, the input side of the signal isolation chip is powered by a power supply to be monitored, and the output side of the signal isolation chip and the central processing unit are powered by the same power supply;
the central processing unit is used for configuring a GPIO pin of the central processing unit which is connected with the signal isolation chip as input, enabling GPIO interruption and configuring the GPIO pin as a falling edge trigger mode, counting the number of falling edges of reset pulses output by each detection chip connected with each signal isolation chip through corresponding GPIO interruption times, and further determining the number of times that the voltage of the power supply to be monitored falls below a corresponding voltage detection threshold value as the voltage falling times of the power supply to be monitored; the central processing unit also records the running time of the whole monitoring device;
the power supply is used for being directly connected with an external direct current power supply and providing a normal working power supply for each device in the monitoring isolation power supply domain;
and the RS232 interface circuit is used for uploading the power supply voltage dropping times to be monitored counted by the central processing unit and the running time of the whole monitoring device to an upper computer according to the provided RS232 interface.
As one improvement of the above technical solution, the selection criterion is that the output tolerance of the power supply voltage to be monitored is 0-10%, and the output of the power supply voltage to be monitored is at least 90% U; wherein, U is the nominal value of the power supply voltage to be monitored.
As one improvement of the technical scheme, the difference between the voltage detection threshold values set by each detection chip is 0.1V.
As an improvement of the technical scheme, each detection chip is provided with a CMOS output pin VOUT, the CMOS output pin VOUT is externally connected with a 100pf capacitor, and the holding time of the reset pulse with the falling edge is controlled.
As one improvement of the above technical solution, the plurality of power supplies to be monitored have nominal operating voltages of 5V, 3.3V and 2.5V.
As one improvement of the above technical solution, the power supply to be monitored provides a nominal operating voltage of 5V, the selection criterion is that the output tolerance of the power supply voltage to be monitored is 10%, and the output of the power supply voltage to be monitored is at least 4.5V according to the nominal operating voltage of the power supply to be monitored and the selection criterion; the voltage detection chip array comprises 5 detection chips; the preset voltage detection threshold values of the detection chips are 4.9V, 4.8V, 4.7V, 4.6V and 4.5V in sequence;
an output pin of the detection chip with the voltage detection threshold value of 4.9V is connected to a second pin of the signal isolation chip;
an output pin of the detection chip with the voltage detection threshold value of 4.8V is connected to a third pin of the signal isolation chip;
an output pin of the detection chip with the voltage detection threshold value of 4.7V is connected to a fourth pin of the signal isolation chip;
an output pin of the detection chip with the voltage detection threshold value of 4.6V is connected to a fifth pin of the signal isolation chip;
and an output pin of the detection chip with the voltage detection threshold of 4.5V is connected to a sixth pin of the signal isolation chip.
As one improvement of the above technical solution, the power supply to be monitored provides a nominal operating voltage of 3.3V, the selection criterion is that the output tolerance of the power supply voltage to be monitored is 10%, and the output of the power supply voltage to be monitored is at least 3.0V according to the nominal operating voltage of the power supply to be monitored and the selection criterion; the voltage detection chip array comprises 3 detection chips; the preset voltage detection threshold of each detection chip is 3.2V, 3.1V and 3.0V in sequence;
an output pin of the detection chip with the voltage detection threshold value of 3.2V is connected to a second pin of the signal isolation chip;
an output pin of the detection chip with the voltage detection threshold value of 3.1V is connected to a third pin of the signal isolation chip;
and an output pin of the detection chip with the voltage detection threshold value of 3.0V is connected to a fourth pin of the signal isolation chip.
As one improvement of the above technical solution, the power supply to be monitored provides a nominal operating voltage of 2.5V, the selection criterion is that the output tolerance of the power supply voltage to be monitored is 10%, and the output of the power supply voltage to be monitored is at least 2.3V according to the nominal operating voltage of the power supply to be monitored and the selection criterion; the voltage detection chip array comprises 2 detection chips; the preset voltage detection threshold of each detection chip is 2.4V and 2.3V in sequence;
an output pin of the detection chip with the voltage detection threshold value of 2.4V is connected to a second pin of the signal isolation chip;
and an output pin of the detection chip with the voltage detection threshold of 2.3V is connected to a third pin of the signal isolation chip.
As one improvement of the above technical solution, the central processing unit is a single chip microcomputer, each detection chip has an output pin, and the output pin outputs a level signal to a GPIO pin of the single chip microcomputer after being subjected to level conversion by the signal isolation chip;
when the voltage of a power supply to be monitored is lower than the voltage detection threshold of each detection chip, the output pin of the corresponding detection chip generates reset pulse with a falling edge, the holding time of the reset pulse with the falling edge is set to be less than 10ms, the reset pulse with the falling edge is captured by the single chip microcomputer, and GPIO of the single chip microcomputer is interrupted once;
the single chip microcomputer counts the GPIO interruption times, and further counts the number of falling edges of reset pulses output by each detection chip connected with each signal isolation chip, so that the times that the power supply voltage to be monitored falls below the corresponding voltage detection threshold voltage are determined and serve as the times that the power supply voltage to be monitored falls, and the central processing unit also records the operation time of the whole monitoring device; and the two are uploaded to an upper computer;
the upper computer comprises an evaluation module for evaluating the stability and reliability of the power supply to be monitored according to the received power supply voltage drop times to be monitored and the operation time of the whole monitoring device;
if the frequency that the 5V, 3.3V and 2.5V power supplies to be monitored respectively fall below 4.9V, 3.2V and 2.4V in the working period of the product to which the power supplies belong is 0, the power supplies can be considered to work stably and reliably; (ii) a
If the frequency that the 5V, 3.3V and 2.5V power supplies to be monitored respectively fall below 4.6V, 3.1V and 2.4V in the working period of the product to which the power supplies belong is more than 0, the working stability and reliability of the power supplies can be considered to be relatively poor;
a one-to-one mapping relation is established between each GPIO of the single chip microcomputer and each corresponding voltage detection threshold value.
The invention also provides a low-voltage direct-current power supply monitoring method, which comprises the following steps:
each power supply to be monitored is connected with a corresponding voltage detection chip array, each voltage detection chip array and the input side of a signal isolation chip connected with the voltage detection chip array supply power to form an isolation power supply domain to be monitored, and the output side of the signal isolation chip supply power, a central processing unit, a power supply and an RS232 interface circuit form a monitoring isolation power supply domain;
each power supply to be monitored provides a power supply for normal operation for each detection chip in the voltage detection chip array connected with the power supply;
the voltage detection chip array selects the number of required detection chips according to the selection standard of the power supply to be monitored, wherein each detection chip carries out real-time monitoring on the power supply to be monitored according to a respective set voltage detection threshold, and when the voltage of the power supply to be monitored is lower than each preset voltage detection threshold, each detection chip outputs a corresponding reset pulse with a falling edge, and the reset pulse can be kept for a period of time;
the signal isolation chip supports multi-voltage multi-channel conversion, level conversion is carried out on reset pulses output by each detection chip connected with the signal isolation chip, corresponding reset pulses which can be identified and processed by the central processing unit and are provided with falling edges are obtained, an output pin of the signal isolation chip is connected to a general input/output pin of the central processing unit, the input side of the signal isolation chip is powered by a power supply to be monitored, and the output side of the signal isolation chip and the central processing unit are powered by the same power supply;
the central processing unit configures a GPIO pin of the central processing unit, which is connected with the signal isolation chip, as an input, enables GPIO interruption and configures the GPIO interruption into a falling edge trigger mode, counts the number of falling edges of reset pulses output by each detection chip connected with each signal isolation chip through corresponding GPIO interruption times, and further determines the times that the voltage of a power supply to be monitored falls below a corresponding voltage detection threshold as the voltage falling times of the power supply to be monitored; the central processing unit also records the running time of the whole monitoring device;
and the frequency of the power supply voltage drop to be monitored counted by the central processing unit and the running time of the whole monitoring device are sent to the terminal equipment connected with the outside for analysis through an RS232 interface provided by the RS232 interface circuit.
Compared with the prior art, the invention has the beneficial effects that:
the device can continuously monitor the working states of a plurality of power supplies to be monitored for a long time; the unattended monitoring is realized; meanwhile, the device can provide the interval distribution statistical value falling below each detection voltage in the power supply operation process.
Drawings
FIG. 1 is a schematic structural diagram of a low-voltage DC power supply monitoring device according to the present invention;
fig. 2 is a schematic structural diagram of the working cooperation and connection relationship between the detection chip with the voltage detection threshold of 4.9V-4.5V and the signal isolation chip in an embodiment of the voltage detection chip array of the low-voltage dc power supply monitoring device of the invention shown in fig. 1;
fig. 3 is a schematic structural diagram of the working cooperation and connection relationship between the detection chip with the voltage detection threshold of 3.2V-3.0V and the signal isolation chip in an embodiment of the voltage detection chip array of the low-voltage dc power supply monitoring device of fig. 1;
fig. 4 is a schematic structural diagram of the working cooperation and connection relationship between the detection chip with the voltage detection threshold of 2.4V-2.3V and the signal isolation chip in an embodiment of the voltage detection chip array of the low-voltage dc power supply monitoring device of fig. 1;
fig. 5 is a flow chart of a method for monitoring power supply of a low-voltage dc power supply according to the present invention.
Detailed Description
The invention will now be further described with reference to the accompanying drawings.
As shown in fig. 1, the present invention provides a low voltage dc power supply monitoring device, which can provide the monitoring function of 5V, 3.3V and 2.5V low voltage dc power supply, and is connected to the power supply to be monitored; the device includes: the device comprises a hardware mainboard, a plurality of voltage detection chip arrays 1 arranged on the hardware mainboard, a plurality of signal isolation chips 2, a central processing unit 3, a power supply 4 and an RS232 interface circuit 5;
the power supplies to be monitored are connected with the voltage detection chip arrays 1, and each power supply to be monitored provides a power supply which normally works for the voltage detection chip array 1 which is correspondingly connected; each voltage detection chip array 1 and the input side of the signal isolation chip 2 correspondingly connected with the voltage detection chip array 1 supply power to form an isolation power domain to be detected, and the isolation power domain to be detected is used as a power domain of a circuit to be detected; the output side of the signal isolation chip 2 supplies power, the central processing unit 3, the power supply 4 and the RS232 interface chip 5 form a monitoring isolation power domain, and the monitoring isolation power domain is used as a power domain of a monitoring circuit;
the voltage detection chip array 1 comprises a plurality of detection chips, and each power supply to be monitored provides a power supply for normal operation for the plurality of detection chips which are correspondingly connected; in this embodiment, the detection chip is the voltage detection chip shown in fig. 1.
The voltage detection chip array 1 is used for selecting the number of required detection chips according to a selection standard, wherein each detection chip monitors a power supply to be monitored in real time according to a respective set voltage detection threshold, and when the voltage of the power supply to be monitored is lower than each preset voltage detection threshold, each detection chip outputs a corresponding reset pulse with a falling edge, and the reset pulse can be kept for a period of time;
when the voltage of the monitoring power supply is lower than the respective detection threshold, the voltage detection chip outputs a reset pulse with a falling edge and can keep for a period of time for the central processing unit 3 to detect and capture the reset pulse with the falling edge;
specifically, the selection criterion is that the output tolerance of the power supply voltage to be monitored is 0-10%, preferably 10% and 5%; the output of the power supply voltage to be monitored is at least 90% U; wherein, U is the nominal operating voltage of the power supply to be monitored.
The difference between the voltage detection threshold values set by each detection chip is 0.1V.
Each of the sense chips has a CMOS output pin VOUT externally connected to a 100pf capacitor, and is configured to have a reset pulse hold time of 100us, which enables the cpu 3 to detect and capture the reset pulse with a falling edge. In other embodiments, any prior art that can maintain the reset pulse signal for a period of time is within the scope of the present invention.
In this embodiment, the voltage detecting chip array 1 shown in fig. 1 may be a BD49Kxx series of detecting chips, where the suffix xx represents the detected voltage threshold, the supply voltage of the BD49Kxx can be supported up to 10V, each of the detecting chips has a CMOS output pin VOUT externally connected with a 100pf capacitor, the detecting chips are configured to have a reset pulse low-level holding time of 100us, and the voltage detecting threshold set by each detecting chip differs by 0.1V. For example, BD49K54 indicates that the detected voltage threshold is 5.4V, BD49K32 indicates that the detected voltage threshold is 3.2V, BD49K31 indicates that the detected voltage threshold is 3.1V, BD49K30 indicates that the detected voltage threshold is 3.0V, BD49K24 indicates that the detected voltage threshold is 2.4V, and BD49K23 indicates that the detected voltage threshold is 2.3V; as shown in fig. 2-4, BD49K49 indicates that the detected voltage threshold is 4.9V, BD49K48 indicates that the detected voltage threshold is 4.8V, BD49K47 indicates that the detected voltage threshold is 4.7V, BD49K46 indicates that the detected voltage threshold is 4.6V, BD49K45 indicates that the detected voltage threshold is 4.5V, and so on.
The signal isolation chip 2 supports multi-voltage multi-channel conversion, because the power supply voltage to be monitored can be different from the power supply voltage of the central processing unit, the signal isolation chip 2 is used for carrying out level conversion on reset pulses output by each detection chip connected with the signal isolation chip to obtain corresponding reset pulses with falling edges and capable of being recognized and processed by the central processing unit, namely low levels are converted into low levels and high levels which can be recognized and processed by the central processing unit and are converted into high levels which can be recognized and processed by the central processing unit, the output pin of the signal isolation chip 2 is connected into a general input/output pin (GPIO pin) of the central processing unit 3, the input side of the signal isolation chip 2 is powered by the power supply to be monitored, and the output side of the signal isolation chip 2 and the central processing unit 3 are powered by the same power supply;
as shown in fig. 2-4, the signal isolation chip 2 has a model of ADuM160N 1;
as shown in fig. 2-4, the voltage detection chip array 1 and the signal isolation chip 2 work together schematically. In fig. 2-4, U1, U2, and U3 respectively convert the input level signal into a 3.3V level signal through the unidirectional conversion channel for the signal isolation chip 2, and output the level signal to the single chip microcomputer, so as to provide a level signal for the single chip microcomputer to identify and detect; the U1, U2 and U3 respectively process the level conversion output by the voltage detection chip array corresponding to the power supply voltage to be monitored being +5V, +3.3V, + 2.5V.
U4, U5, and U6 are BD49Kxx series detection chips with voltage detection thresholds of 4.9V, 3.2V, and 2.4V, respectively, specifically, U4 is a BD49K49 detection chip, and U5 is a BD49K32 detection chip; u6 is a BD49K24 detection chip.
In this embodiment, the plurality of power sources to be monitored are nominal operating voltages of 5V, 3.3V and 2.5V. In the whole monitoring device, 3 voltage detection chip arrays 1 and 3 signal isolation chips 2 are required to be arranged; the specific connection relationship is as follows:
the 5V power supply to be monitored is connected with one of the voltage detection chip arrays 1, the selection standard is that the voltage output tolerance of the power supply to be monitored is 10%, and the voltage detection chip array 1 determines 5 required detection chips according to the 5V nominal working voltage and the selection standard, namely, the voltage detection threshold values are respectively 4.9V, 4.8V, 4.7V, 4.6V and 4.5V detection chips; each detection chip is connected with the same signal isolation chip 2, and the signal isolation chip 2 is connected with the central processing unit;
the 3.3V power supply to be monitored is connected with the other voltage detection chip array 1, the selection standard is that the output tolerance of the voltage of the power supply to be monitored is 10%, and the voltage detection chip array 1 determines that 3 detection chips are needed according to the 3.3V nominal working voltage and the selection standard, namely, the voltage detection threshold values are 3.2V, 3.1V and 3.0V detection chips respectively; each detection chip is connected with the same signal isolation chip 2, and the signal isolation chip 2 is connected with the central processing unit;
the 2.5V power supply to be monitored is connected with the rest voltage detection chip array 1, the selection standard is that the output tolerance of the voltage of the power supply to be monitored is 10%, and the voltage detection chip array 1 determines 2 detection chips according to the 2.5V nominal working voltage and the selection standard, namely, the voltage detection threshold is 2.4V and 2.3V detection chips respectively; each detection chip is connected with the same signal isolation chip 2, and the signal isolation chip 2 is connected with the central processing unit;
in fig. 2, a CMOS output pin VOUT of the detection chip with a voltage detection threshold of 4.9V is externally connected with a 100pf capacitor, and the detection chip is configured to have a holding time of a reset pulse of 100 us; in addition, the CMOS output pin VOUT of the detection chip with the voltage detection threshold of 4.9V is correspondingly connected to the second pin 2 of U1, and the detection chips with the voltage detection thresholds of 4.8V, 4.7V, 4.6V, and 4.5V and their connection modes are not shown, and their connection modes are as follows:
the CMOS output pins VOUT of the detection chips with voltage detection threshold values of 4.8V, 4.7V, 4.6V and 4.5V are respectively and correspondingly connected with an external 100pf capacitor, and each detection chip is configured to have reset pulse low-level retention time of 100 us; the CMOS output pins VOUT of the detection chips with voltage detection thresholds of 4.8V, 4.7V, 4.6V, and 4.5V are respectively connected to the third pin 3, the fourth pin 4, the fifth pin 5, and the sixth pin 6 of U1, and have corresponding signal names of 4V8, 4V7, 4V6, and 4V 5.
In this embodiment, as shown in fig. 2, the detection chips with the preset voltage detection thresholds of 4.9V, 4.8V, 4.7V, 4.6V and 4.5V respectively form a voltage detection chip array of a power supply voltage 5V to be monitored;
in fig. 3, a CMOS output pin VOUT of the detection chip with a voltage detection threshold of 3.2V is externally connected with a 100pf capacitor, and the detection chip is configured to have a holding time of a reset pulse of 100 us; in addition, the CMOS output pin VOUT of the detection chip with the voltage detection threshold of 3.2V is correspondingly connected to the second pin 2 of U2, while the detection chip with the detection thresholds of 3.1V and 3.0V is not shown, and the connection manner is as follows:
in fig. 3, external 100pf capacitors are respectively corresponding to the CMOS output pins VOUT of the detection chips with voltage detection thresholds of 3.1V and 3.0V, and the detection chips are configured to have a holding time of a reset pulse of 100 us; the CMOS output pins VOUT of the detection chips with the voltage detection threshold values of 3.1V and 3.0V are respectively and correspondingly connected to the third pin 3 and the fourth pin 4 of U2, the corresponding signal names are 3V1 and 3V0, the voltage detection threshold values of 3.2V and the detection chips with the voltage detection threshold values of 3.1V and 3.0V form a voltage detection chip array of the power supply voltage to be monitored, wherein the voltage detection chip array is 3.3V;
in fig. 4, a CMOS output pin VOUT of the detection chip with a voltage detection threshold of 2.4V is externally connected with a 100pf capacitor, and the detection chip is configured to have a holding time of a reset pulse of 100 us; in addition, the CMOS output pin VOUT of the detection chip with the voltage detection threshold of 2.4V is correspondingly connected to the second pin 2 of U3, while the detection chip with the voltage detection threshold of 2.3V is not shown, and the connection manner is as follows:
a CMOS output pin VOUT of a detection chip with a voltage detection threshold value of 2.3V is externally connected with a 100pf capacitor, and the detection chip is configured to have a holding time of a reset pulse of 100 us; in addition, the CMOS output pin VOUT of the detection chip with the voltage detection threshold of 2.3V is correspondingly connected to the third pin 3 of U3, and the corresponding signal name is 2V 3. The detection chips with the voltage detection threshold values of 2.4V and 2.3V form a voltage detection chip array with the power supply voltage to be monitored of 2.5V.
In this embodiment, the voltage detection chip array in the apparatus is a group of detection chips, and has different voltage detection thresholds, the selected voltage detection threshold is slightly lower than the output voltage of the power supply to be monitored, and the voltage detection thresholds are uniformly distributed. For example, when the output voltage of the power supply to be monitored is 5V, the voltage detection thresholds corresponding to the selected group of detection chips are respectively 4.9V, 4.8V, 4.7V, 4.6V and 4.5V, and according to the selection standard, the output voltage tolerance of the power supply to be monitored is usually within 10%, that is, the selection standard is not satisfied when the output voltage tolerance is lower than 4.5V, so that the detection chips corresponding to the above 5 power supply detection thresholds are selected; when the output voltage of the power supply to be monitored is 3.3V, the voltage detection threshold values corresponding to the selected group of detection chips are respectively 3.2V, 3.1V and 3.0V; when the output voltage of the power supply to be monitored is 2.5V, the voltage detection threshold values corresponding to the selected group of detection chips are respectively 2.4V and 2.3V.
Each detection chip is powered by a low-voltage direct-current power supply to be monitored, namely a power supply to be monitored, each detection chip is provided with an output pin, if the voltage drops below a corresponding voltage detection threshold value instantaneously, a low-level reset pulse is generated, has certain holding time and can be captured by a single chip machine. The signal isolation chip converts the level of the signal of the output pin of the detection chip and then accesses the GPIO pin of the central processing unit, the power supply on one side of the central processing unit is stable and reliable, and the power supply is isolated from the power supply to be monitored. And configuring the GPIO corresponding to the central processing unit into an input mode, enabling GPIO interruption, and triggering the mode to be level falling edge triggering. When the power supply voltage to be monitored is lower than a voltage detection threshold value, a chip output pin generates a low-level reset pulse, the low-level retention time is generally configured to be less than 10ms, and on the premise of ensuring that the low-level retention time can be captured by a single chip computer, the shorter the time is, the faster the voltage drop and recovery can be quickly responded next time.
The central processing unit 3 is a single chip microcomputer, the specific model of the central processing unit is STM32F429ZI, a single chip microcomputer GPIO pin which is connected with the signal isolation chip 2 is configured to be input, GPIO interruption is enabled, and the single chip microcomputer GPIO pin is configured to be in a falling edge trigger mode, the number of reset pulses of each detection chip connected with each signal isolation chip 2 is counted through the corresponding GPIO interruption times, and the times that the monitored power supply voltage falls below the corresponding voltage detection threshold value is further determined to be used as the falling times of the monitored power supply; the singlechip also records the running time of the whole monitoring device; and the voltage drop times of the monitored power supply and the operation time of the whole monitoring device are uploaded to an upper computer.
And a one-to-one mapping relation is established between each GPIO of the single chip microcomputer and each corresponding voltage detection threshold.
The single chip microcomputer starts timing after being powered on, counts the interruption times of each GPIO in real time, and uploads the interruption times of all the GPIOs and the running time of the current monitoring circuit to an upper computer through an RS232 interface provided by an RS232 interface circuit in a preset fixed period;
the upper computer comprises an evaluation module for evaluating the stability and reliability of the power supply to be monitored according to the received power supply voltage drop times to be monitored and the running time;
if the frequency that the 5V power supply, the 3.3V power supply and the 2.5V power supply to be monitored respectively drop below 4.9V, 3.2V and 2.4V in the work period of the product to which the power supply belongs is 0, namely the frequency that the voltage of the power supply to be monitored drops is 0, the power supply to be monitored works stably and reliably;
if the frequency that the 5V power supply, the 3.3V power supply and the 2.5V power supply to be monitored respectively drop below 4.6V, 3.1V and 2.4V in the work period of the product to which the power supply belongs is greater than 0, namely the frequency that the voltage of the power supply to be monitored drops is greater than 0, the power supply to be monitored is evaluated to be unstable in work and relatively poor in reliability;
the power supply 4 is used as a power supply domain of the monitoring circuit, provides 3.3V power supply voltage, is directly connected with an external low-voltage direct-current power supply through a wiring terminal, and provides a normal working power supply for each device in the power supply domain of the monitoring circuit;
the RS232 interface circuit 5 comprises an RS232 interface chip and a connector, wherein the specific model of the RS232 interface chip is MAX3232, the interface level of an RS232 interface mode connected with external equipment is provided, and the number of times of power supply voltage drop to be monitored and the running time of the whole monitoring device, which are counted by the central processing unit 3, are uploaded to an upper computer through the provided RS232 interface level.
The invention also provides a low-voltage direct-current power supply monitoring method, which comprises the following steps:
each power supply to be monitored is connected with a corresponding voltage detection chip array 1, each voltage detection chip array 1 and the input side of a signal isolation chip 2 connected with the voltage detection chip array 1 supply power to form an isolation power supply domain to be monitored, and the output side of the signal isolation chip 2 supply power, a central processing unit 3, a power supply 4 and an RS232 interface circuit 5 form a monitoring isolation power supply domain;
each power supply to be monitored provides a power supply for normal operation for each detection chip in the voltage detection chip array 1 connected with the power supply;
the voltage detection chip array 1 selects the number of required detection chips according to a selection standard, wherein each detection chip carries out real-time monitoring on a power supply to be monitored according to a respective set voltage detection threshold, and when the voltage of the power supply to be monitored is lower than each preset voltage detection threshold, each detection chip outputs a corresponding reset pulse with a falling edge, and the reset pulse can be kept for a period of time;
the signal isolation chip 2 supports multi-voltage multi-channel conversion, level conversion is carried out on reset pulses output by each detection chip connected with the signal isolation chip 2, corresponding reset pulses which can be identified and processed by the central processing unit and are provided with falling edges are obtained, output pins of the signal isolation chip 2 are connected to general input and output pins (GPIO pins) of the central processing unit 3, the input side of the signal isolation chip 2 is powered by a power supply to be monitored, and the output side of the signal isolation chip 2 and the central processing unit 3 are powered by the same power supply;
the central processing unit 3 configures a GPIO pin of the central processing unit which is connected with the signal isolation chip as input, enables GPIO interruption and configures the GPIO interruption into a falling edge trigger mode, counts the number of falling edges of reset pulses output by each detection chip connected with each signal isolation chip 2 through corresponding GPIO interruption times, and further determines the times that the voltage of the power supply to be monitored falls below a corresponding voltage detection threshold value as the voltage falling times of the power supply to be monitored; the central processing unit 3 also records the running time of the whole monitoring device;
the frequency of power supply voltage drop to be monitored counted by the central processing unit and the running time of the whole monitoring device are uploaded to an upper computer through an RS232 interface provided by the RS232 interface circuit 5.
As shown in fig. 5, the operation process of the central processing unit specifically includes:
and (3) initializing a configuration process: setting an initial value of a timer count value variable arranged in the central processing unit 3 to be 0; setting an initial value of a GPIO interruption count value variable to be 0, and correspondingly defining a plurality of variables if a plurality of GPIOs are used for detection, wherein the initial values are all set to be 0; carrying out initialization configuration on RS232 communication parameters; the GPIO used for detection is configured as input, and the interrupt mode is that the falling edge triggers interrupt; configuring the interrupt cycle of a timer to be 1 millisecond and starting the timer;
in the operation process, when the voltage of a power supply to be monitored falls below a voltage detection threshold value set by a corresponding detection chip, the corresponding GPIO of the central processing unit is driven to generate interruption, and the GPIO interruption processing method comprises the following steps: judging which GPIO pin generates interruption; clearing the interrupt flag; and adding 1 to the corresponding GPIO interrupt count value according to the interrupt source.
In the running process, the timer generates an interrupt every 1 millisecond, and the interrupt processing method comprises the following steps: clearing a timer interrupt flag; adding 1 to the count value of the timer; the timer count value is the remainder of 1000, if the remainder is 0, the timer count value indicates that 1 second of time has elapsed, the interrupt count value of each GPIO is sent to externally connected terminal equipment through an RS232 interface, and the running time of the current monitoring circuit is sent to the externally connected terminal equipment through RS232 for analysis; if the remainder is not 0, exiting the process.
By the monitoring method, the low-voltage direct-current power supply with the power supply voltage to be measured being 5V, 3.3V and 2.5V can be continuously monitored, the reliability of the low-voltage direct-current power supply can be better known through the statistical interval distribution of the power supply voltage falling below each voltage detection threshold value, and the influence of electromagnetic interference on the power supply output in the operation process of the circuit to be measured is accurately known.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not limited. Although the present invention has been described in detail with reference to the embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A low-voltage DC power supply monitoring device is characterized in that the device is connected with a plurality of power supplies to be monitored; the device includes: the device comprises a hardware mainboard, a plurality of voltage detection chip arrays (1), a plurality of signal isolation chips (2), a central processing unit (3), a power supply (4) and an RS232 interface circuit (5), wherein the voltage detection chip arrays, the signal isolation chips, the power supply and the RS232 interface circuit are arranged on the hardware mainboard;
each power supply to be monitored is connected with a corresponding voltage detection chip array (1), each voltage detection chip array (1) and the input side of a signal isolation chip (2) connected with the voltage detection chip array form an isolation power supply domain to be monitored, and the output side of the signal isolation chip (2) supplies power, and a central processing unit (3), a power supply (4) and an RS232 interface circuit (5) form a monitoring isolation power supply domain;
the voltage detection chip array (1) comprises a plurality of detection chips and is used for selecting the number of the required detection chips according to a selection standard, wherein each detection chip carries out real-time monitoring on a power supply to be monitored according to a respective set voltage detection threshold, and when the voltage of the power supply to be monitored is lower than each preset voltage detection threshold, each detection chip outputs a corresponding reset pulse with a falling edge, and the reset pulse can be kept for a period of time;
the signal isolation chip (2) supports multi-voltage multi-channel conversion and is used for carrying out level conversion on reset pulses output by each detection chip connected with the signal isolation chip to obtain corresponding reset pulses which can be identified and processed by the central processing unit and have a falling edge, an output pin of the signal isolation chip (2) is connected with a general input/output pin of the central processing unit (3), the input side of the signal isolation chip (2) is powered by a power supply to be monitored, and the output side of the signal isolation chip (2) and the central processing unit (3) are powered by the same power supply;
the central processing unit (3) is used for configuring GPIO pins of the central processing unit which are connected with the signal isolation chips into input, enabling GPIO interruption and configuring the GPIO interruption into a falling edge trigger mode, counting the number of falling edges of reset pulses output by each detection chip connected with each signal isolation chip (2) through corresponding GPIO interruption times, and further determining the times that the voltage of the power supply to be monitored falls below a corresponding voltage detection threshold value as the voltage falling times of the power supply to be monitored; the central processing unit (3) also records the running time of the whole monitoring device;
the power supply (4) is directly connected with an external direct current power supply and provides a normal working power supply for each device in the monitoring and isolating power supply domain;
and the RS232 interface circuit (5) is used for uploading the power supply voltage dropping times to be monitored counted by the central processing unit and the running time of the whole monitoring device to an upper computer according to the provided RS232 interface.
2. A low voltage dc power supply monitoring device according to claim 1, wherein the selection criteria is that the power supply voltage output tolerance to be monitored is 0-10%, and the power supply voltage output to be monitored is at least 90% U; wherein, U is the nominal value of the power supply voltage to be monitored.
3. The device for monitoring the power supply of the low-voltage direct-current power supply according to claim 2, wherein the difference between the voltage detection thresholds set by each detection chip is 0.1V.
4. A low voltage dc power supply monitoring device according to claim 3, wherein each of the detecting chips has a CMOS output pin VOUT externally connected to a 100pf capacitor for controlling the hold time of the reset pulse with the falling edge.
5. A low voltage DC power supply monitoring device according to claim 1 or 4, wherein the plurality of power supplies to be monitored are rated for 5V, 3.3V and 2.5V operating voltage.
6. The low voltage dc power supply monitoring device according to claim 5, wherein the power supply to be monitored provides a nominal operating voltage of 5V, the selection criterion is that the output tolerance of the power supply voltage to be monitored is 10%, and the output of the power supply voltage to be monitored is at least 4.5V according to the nominal operating voltage of the power supply to be monitored and the selection criterion; the voltage detection chip array (1) comprises 5 detection chips; the preset voltage detection threshold values of the detection chips are 4.9V, 4.8V, 4.7V, 4.6V and 4.5V in sequence;
the output pin of the detection chip with the voltage detection threshold value of 4.9V is connected to the second pin (2) of the signal isolation chip;
the output pin of the detection chip with the voltage detection threshold of 4.8V is connected to the third pin (3) of the signal isolation chip;
the output pin of the detection chip with the voltage detection threshold of 4.7V is connected to the fourth pin (4) of the signal isolation chip;
the output pin of the detection chip with the voltage detection threshold value of 4.6V is connected to the fifth pin (5) of the signal isolation chip;
the output pin of the detection chip with the voltage detection threshold of 4.5V is connected to the sixth pin (6) of the signal isolation chip.
7. A low voltage DC power supply monitoring device according to claim 5, wherein the power supply to be monitored provides a nominal operating voltage of 3.3V, the selection criterion being that the output tolerance of the power supply voltage to be monitored is 10%, the output of the power supply voltage to be monitored being at least 3.0V according to the nominal operating voltage of the power supply to be monitored and the selection criterion; the voltage detection chip array (1) comprises 3 detection chips; the preset voltage detection threshold of each detection chip is 3.2V, 3.1V and 3.0V in sequence;
the output pin of the detection chip with the voltage detection threshold value of 3.2V is connected to the second pin (2) of the signal isolation chip;
the output pin of the detection chip with the voltage detection threshold value of 3.1V is connected to the third pin (3) of the signal isolation chip;
the output pin of the detection chip with the voltage detection threshold of 3.0V is connected to the fourth pin (4) of the signal isolation chip.
8. The low voltage dc power supply monitoring device according to claim 5, wherein the power supply to be monitored provides a nominal operating voltage of 2.5V, the selection criterion is that the output tolerance of the power supply voltage to be monitored is 10%, and the output of the power supply voltage to be monitored is at least 2.3V according to the nominal operating voltage of the power supply to be monitored and the selection criterion; the voltage detection chip array (1) comprises 2 detection chips; the preset voltage detection threshold of each detection chip is 2.4V and 2.3V in sequence;
the output pin of the detection chip with the voltage detection threshold of 2.4V is connected to the second pin (2) of the signal isolation chip;
the output pin of the detection chip with the voltage detection threshold of 2.3V is connected to the third pin (3) of the signal isolation chip.
9. The low-voltage direct-current power supply monitoring device according to claim 1, wherein the central processing unit (3) is a single chip microcomputer, each detection chip is provided with an output pin, and an output level signal of the output pin is subjected to level conversion by the signal isolation chip (2) and then is output to a GPIO pin of the single chip microcomputer;
when the voltage of a power supply to be monitored is lower than the voltage detection threshold value of each detection chip, the output pin of the corresponding detection chip generates a reset pulse with a falling edge, the holding time of the reset pulse with the falling edge is set to be less than 10ms, the single chip microcomputer captures the reset pulse with the falling edge, and the GPIO of the single chip microcomputer is interrupted once;
a one-to-one mapping relation is established between each GPIO of the single chip microcomputer and each corresponding voltage detection threshold;
the single chip microcomputer counts the GPIO interruption times, and further counts the number of falling edges of reset pulses output by each detection chip connected with each signal isolation chip (2), so that the times that the power supply voltage to be monitored falls below the corresponding voltage detection threshold voltage are determined and serve as the times that the power supply voltage to be monitored falls, and the central processing unit (3) also records the operation time of the whole monitoring device; and the two are uploaded to an upper computer;
the upper computer comprises an evaluation module for evaluating the stability and reliability of the power supply to be monitored according to the received power supply voltage drop times to be monitored and the operation time of the whole monitoring device.
10. A method for monitoring the power supplied by a low-voltage dc power supply, which is implemented based on the device for monitoring the power supplied by a low-voltage dc power supply of any one of claims 1 to 9, and which comprises:
each power supply to be monitored is connected with a corresponding voltage detection chip array (1), each voltage detection chip array (1) and the input side of a signal isolation chip (2) connected with the voltage detection chip array form an isolation power supply domain to be monitored, and the output side of the signal isolation chip (2) supplies power, and a central processing unit (3), a power supply (4) and an RS232 interface circuit (5) form a monitoring isolation power supply domain;
each power supply to be monitored provides a power supply for normal operation for each detection chip in the voltage detection chip array (1) connected with the power supply to be monitored;
the voltage detection chip array (1) selects the number of required detection chips according to the selection standard of a power supply to be monitored, wherein each detection chip monitors the power supply to be monitored in real time according to a respective set voltage detection threshold, and when the voltage of the power supply to be monitored is lower than each preset voltage detection threshold, each detection chip outputs a corresponding reset pulse with a falling edge, which can be kept for a period of time;
the signal isolation chip (2) supports multi-voltage multi-channel conversion, level conversion is carried out on reset pulses output by each detection chip connected with the signal isolation chip, corresponding reset pulses which can be identified and processed by the central processing unit and are provided with falling edges are obtained, an output pin of the signal isolation chip (2) is connected to a general input/output pin of the central processing unit (3), the input side of the signal isolation chip (2) is powered by a power supply to be monitored, and the output side of the signal isolation chip (2) and the central processing unit (3) are powered by the same power supply;
the central processing unit (3) configures a GPIO pin of the central processing unit which is connected with the signal isolation chip as input, enables GPIO interruption and configures the GPIO interruption into a falling edge trigger mode, counts the number of falling edges of reset pulses output by each detection chip connected with each signal isolation chip (2) through corresponding GPIO interruption times, and further determines the times that the voltage of the power supply to be monitored falls below a corresponding voltage detection threshold value as the voltage falling times of the power supply to be monitored; the central processing unit (3) also records the running time of the whole monitoring device;
and the RS232 interface provided by the RS232 interface circuit (5) sends the power supply voltage dropping times to be monitored counted by the central processing unit and the running time of the whole monitoring device to terminal equipment connected with the outside for analysis.
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