CN114624571A - Converter chip test circuit and system - Google Patents
Converter chip test circuit and system Download PDFInfo
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- CN114624571A CN114624571A CN202210238785.0A CN202210238785A CN114624571A CN 114624571 A CN114624571 A CN 114624571A CN 202210238785 A CN202210238785 A CN 202210238785A CN 114624571 A CN114624571 A CN 114624571A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2894—Aspects of quality control [QC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R15/00—Details of measuring arrangements of the types provided for in groups G01R17/00 - G01R29/00, G01R33/00 - G01R33/26 or G01R35/00
- G01R15/14—Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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Abstract
The application relates to a converter chip test circuit and a system. In the converter chip test circuit, a logic control unit is used for sending digital waveform test data to a digital-to-analog conversion circuit after receiving the digital waveform test data sent by an upper computer, the digital-to-analog conversion circuit is used for converting the digital waveform test data into analog waveform test data and sending the analog waveform test data to a signal conditioning circuit, the signal conditioning circuit is used for sending the analog waveform test data to a target chip to be tested after the signal-to-noise ratio of the analog waveform test data is improved, so that the target chip to be tested converts the analog waveform test data into digital waveform test feedback data and sends the digital waveform test feedback data to the upper computer, and the upper computer is used for obtaining the test result of the target chip to be tested according to the digital waveform test data and the digital waveform test feedback data. The converter chip test circuit and the converter chip test system provided by the embodiment of the application can ensure the accuracy of the test result of the target chip to be tested.
Description
Technical Field
The application relates to the field of integrated circuit automated testing, in particular to a converter chip testing circuit and system.
Background
In the field of automatic test of integrated circuits, analog-to-digital conversion (ADC) test is carried out on a chip, which is an important test content in the quality inspection process of the chip, and a signal source used in the test is an important component of a test system, and has important significance for ensuring the accuracy of a test result. However, in the prior art, the quality of the test signal provided by the signal source is relatively general. Under the condition that the quality of the test signal cannot be guaranteed, the accuracy of the test result is directly influenced.
Disclosure of Invention
It is an object of the present application to provide a converter chip test circuit and system for providing a high quality test signal of any form with high accuracy and high bandwidth to solve the above problems.
The converter chip test circuit provided by the embodiment of the application comprises a logic control unit, a digital-to-analog conversion circuit and a signal conditioning circuit, wherein the digital-to-analog conversion circuit is respectively connected with the logic control unit and the signal conditioning circuit;
the logic control unit is used for sending the digital waveform test data to the digital-to-analog conversion circuit after receiving the digital waveform test data sent by the upper computer;
the digital-to-analog conversion circuit is used for converting the digital waveform test data into analog waveform test data and sending the analog waveform test data to the signal conditioning circuit;
the signal conditioning circuit is used for sending the analog waveform test data to a target chip to be tested after the signal-to-noise ratio of the analog waveform test data is improved, so that the target chip to be tested converts the analog waveform test data into digital waveform test feedback data and sends the digital waveform test feedback data to the upper computer, and the upper computer is used for obtaining a test result of the target chip to be tested according to the digital waveform test data and the digital waveform test feedback data.
In the process of testing a target chip to be tested by the converter chip test circuit provided by the embodiment of the application, the logic control unit is used for sending digital waveform test data to the digital-to-analog conversion circuit after receiving the digital waveform test data sent by the upper computer, the digital-to-analog conversion circuit is used for converting the digital waveform test data into analog waveform test data and sending the analog waveform test data to the signal conditioning circuit, and the signal conditioning circuit is used for sending the analog waveform test data to the target chip to be tested after improving the signal-to-noise ratio of the analog waveform test data, so that the signal quality of the analog waveform test data can be ensured, then the subsequent target chip to be tested converts the analog waveform test data into digital waveform test feedback data and sends the digital waveform test feedback data to the upper computer, and the upper computer compares the digital waveform test data with the digital waveform test feedback data, and after the difference between the target chip and the target chip is analyzed to obtain the test result of the target chip to be tested, the accuracy of the test result can be ensured.
With reference to the first aspect, an embodiment of the present application further provides a first optional implementation manner of the first aspect, where the converter chip test circuit further includes a data storage, and the data storage is connected to the logic control unit;
the logic control unit is used for storing the digital waveform test data in the data memory after receiving the digital waveform test data sent by the upper computer, acquiring the digital waveform test data from the data memory after receiving an initial test signal sent by the upper computer, and sending the digital waveform test data to the digital-to-analog conversion circuit, wherein the initial test signal carries identification information of the digital waveform test data.
In the above embodiment, the converter chip test circuit further includes a data storage connected to the logic control unit, so that the upper computer can send a plurality of pieces of digital waveform test data first and store the digital waveform test data in the data storage, and thereafter, the logic control unit extracts the identification information from the initial test signal when receiving an initial test signal, and then obtains the digital waveform test data indicated by the identification information from the data storage, and sends the digital waveform test data to the digital-to-analog conversion circuit, so that the storage and subsequent tests of the digital waveform test data are divided in stages, thereby reducing the operational complexity of the test system and improving the generation efficiency of the test signal.
With reference to the first aspect, an embodiment of the present application further provides a second optional implementation manner of the first aspect, where the digital-to-analog conversion circuit includes a plurality of digital-to-analog converters, the digital-to-analog converters have different bit depths, and the digital-to-analog converters are respectively connected to the signal conditioning circuit through corresponding first switching devices.
In the above embodiment, the digital-to-analog conversion circuit includes a plurality of digital-to-analog converters, and the plurality of digital-to-analog converters have different bit depths, so that the test requirements of target chips to be tested with different bit depths can be met, and the applicable range of the conversion chip test circuit is increased.
With reference to the first aspect, an embodiment of the present application further provides a third optional implementation manner of the first aspect, where the signal conditioning circuit includes a driving circuit and a filter circuit, and the driving circuit is connected to the digital-to-analog conversion circuit and the filter circuit, respectively;
the drive circuit is used for amplifying the analog waveform test data and then sending the analog waveform test data to the filter circuit;
the filter circuit is used for carrying out filtering processing on the analog waveform test data so as to improve the signal-to-noise ratio of the analog waveform test data, and then sending the analog waveform test data to a target chip to be tested.
In the above embodiment, the signal conditioning circuit is designed by a simple driving circuit and a simple filter circuit, and therefore, the design and manufacturing cost of the converter test circuit can be reduced.
With reference to the third optional implementation manner of the first aspect, an embodiment of the present application further provides a fourth optional implementation manner of the first aspect, where the filter circuit includes multiple sets of filters, the multiple sets of filters have different filtering frequency parameters, and the multiple sets of filters are respectively connected to the driving circuit through corresponding second switching devices.
In the above embodiment, the filter circuit includes multiple sets of filters having different filtering frequency parameters, so that the test requirements of the target chip to be tested with different required signal frequencies can be met, thereby increasing the applicable range of the conversion chip test circuit.
With reference to the first aspect, an embodiment of the present application further provides a fifth optional implementation manner of the first aspect, where the converter chip test circuit further includes an analog-to-digital conversion acquisition circuit, and an input end of the analog-to-digital conversion acquisition circuit is connected to an output end of the signal conditioning circuit through a third switching device;
the logic control unit is also used for sending the digital waveform calibration data to the digital-to-analog conversion circuit after receiving the digital waveform calibration data sent by the upper computer;
the digital-to-analog conversion circuit is also used for converting the digital waveform calibration data into analog waveform calibration data and sending the analog waveform calibration data to the signal conditioning circuit;
when the third switching device is turned on, the signal conditioning circuit is further used for sending the analog waveform calibration data to the analog-to-digital conversion acquisition circuit after the signal-to-noise ratio of the analog waveform calibration data is improved;
the analog-to-digital conversion acquisition circuit is used for converting the analog waveform calibration data into digital waveform calibration feedback data and sending the digital waveform calibration feedback data to the upper computer, and the upper computer is used for obtaining linear calibration parameters according to the digital waveform calibration data and the digital waveform calibration feedback data and sending digital waveform test data and the linear calibration parameters to the logic control unit;
the logic control unit is specifically configured to send the digital waveform test data to the digital-to-analog conversion circuit after the digital waveform test data is linearly calibrated by the linear calibration parameter.
Through the embodiment, the target digital waveform test data expected to be input into the converter chip test circuit can be ensured to be basically consistent with the actual analog waveform test signal output by the converter chip test circuit as much as possible, namely, the target digital waveform test data has basically consistent signal amplitude and signal period, so that the nonlinear problem of analog waveform test data subsequently output by the converter chip test circuit is reduced, and finally, the accuracy of the test result can be further improved.
With reference to the first aspect, an embodiment of the present application further provides a sixth optional implementation manner of the first aspect, where the converter chip test circuit further includes a dc offset calibration circuit, and the dc offset calibration circuit is connected to the logic control unit and the signal conditioning circuit, respectively;
the direct current offset calibration circuit is used for converting the direct current offset calibration parameters into analog direct current offset calibration data after receiving the direct current offset calibration parameters sent by the upper computer, and applying the analog direct current offset calibration data to the signal conditioning circuit;
the signal conditioning circuit is further used for carrying out direct current offset calibration on the analog waveform test data according to the analog quantity direct current offset calibration data and then carrying out signal to noise ratio improvement on the analog waveform test data.
In the above embodiment, the converter chip test circuit further includes a dc offset calibration circuit, the dc offset calibration circuit is configured to convert the dc offset calibration parameter into analog dc offset calibration data after receiving the dc offset calibration parameter sent by the upper computer, and apply the analog dc offset calibration data to the signal conditioning circuit, and the signal conditioning circuit is further configured to perform dc offset calibration on the analog waveform test data according to the analog dc offset calibration data, so as to improve the signal accuracy of the analog waveform test data, and finally, the accuracy of the test result can be further improved.
With reference to the first aspect or any one of the foregoing optional implementations of the first aspect, this application example further provides a seventh optional implementation of the first aspect, and multiple sets of the digital-to-analog conversion circuit and the signal conditioning circuit are provided.
In the above embodiment, the digital-to-analog conversion circuit and the signal conditioning circuit are provided with multiple sets, which can simultaneously meet the test of multiple target chips to be tested, thereby improving the test efficiency.
With reference to the seventh optional implementation manner of the first aspect, an embodiment of the present application further provides an eighth optional implementation manner of the first aspect, where the signal conditioning circuit is disposed on a mother board formed by the logic control unit and the digital-to-analog conversion circuit in a daughter board manner.
In the above embodiment, the signal conditioning circuit is disposed on the motherboard card formed by the logic control unit and the digital-to-analog conversion circuit in a daughter board card manner, so that when the daughter board card is damaged, a new daughter board card can be replaced conveniently, so as to avoid scrapping the whole converter chip test circuit, thereby reducing the test cost.
In a second aspect, a converter chip test system provided in an embodiment of the present application includes an upper computer and the first aspect, or a converter chip test circuit provided in any optional implementation manner of the first aspect, where the converter chip test circuit is connected to the upper computer;
the upper computer is used for generating digital waveform test data and sending the digital waveform test data to the converter chip test circuit.
The converter chip test system provided in the embodiment of the present application has the same beneficial effects as the converter chip test circuit provided in the first aspect, or any optional implementation manner of the first aspect, and details are not repeated here.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a converter chip test circuit according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of another converter chip test circuit according to an embodiment of the present disclosure.
Fig. 3 is a schematic structural diagram of another converter chip test circuit according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of another converter chip test circuit according to an embodiment of the present disclosure.
Fig. 5 is a schematic diagram of a high-performance signal generated by a signal conditioning circuit in a converter chip test circuit according to an embodiment of the present disclosure.
Fig. 6 is a schematic diagram of a high-precision signal generated by a signal conditioning circuit in a converter chip test circuit according to an embodiment of the present disclosure.
Fig. 7 is a schematic structural diagram of another converter chip test circuit according to an embodiment of the present disclosure.
Fig. 8 is a schematic diagram of another structure of a converter chip test circuit according to an embodiment of the present disclosure.
Fig. 9 is a schematic structural diagram of another converter chip test circuit according to an embodiment of the present disclosure.
Fig. 10 is a schematic structural diagram of another converter chip test circuit according to an embodiment of the present disclosure.
Fig. 11 is a schematic structural diagram of a converter chip test system according to an embodiment of the present disclosure.
Fig. 12 is a schematic structural diagram of another converter chip test system according to an embodiment of the present disclosure.
Reference numerals: 10-converter chip test system; 100-converter chip test circuit; 110-a logic control unit; 120-a digital-to-analog conversion circuit; 130-a signal conditioning circuit; 131-a drive circuit; 1311 — a first buffer; 1312-an amplifying circuit; 132-a filter circuit; 140-a data memory; 150-a first switching device; 160-a second switching device; 170-a third switching device; 180-analog-to-digital conversion acquisition circuitry; 190-a fourth switching device; 200-a fifth switching device; 210-a dc offset calibration circuit; 220-a second buffer; 400-an upper computer; 700-target chip to be tested; 1000-digital control board card.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Furthermore, it should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
Referring to fig. 1, a converter chip testing circuit 100 provided in the present embodiment includes a logic control unit 110, a digital-to-analog conversion circuit 120 and a signal conditioning circuit 130, where the digital-to-analog conversion circuit 120 is connected to the logic control unit 110 and the signal conditioning circuit 130, respectively.
The logic control unit 110 is configured to send the digital waveform test data to the digital-to-analog conversion circuit 120 after receiving the digital waveform test data sent by the upper computer. The digital-to-analog conversion circuit 120 is configured to convert the digital waveform test data into analog waveform test data and send the analog waveform test data to the signal conditioning circuit 130. The signal conditioning circuit 130 is configured to send the analog waveform test data to the target chip to be tested 700 after the signal-to-noise ratio of the analog waveform test data is increased, so that the target chip to be tested 700 converts the analog waveform test data into digital waveform test feedback data and sends the digital waveform test feedback data to the upper computer, and the upper computer is configured to obtain a test result of the target chip to be tested 700 according to the digital waveform test data and the digital waveform test feedback data.
The logic control unit 110 may be, but is not limited to, a Field Programmable Gate Array (FPGA), and the upper computer may be a server or a terminal device, which is not limited in this embodiment of the present disclosure. In practical implementation, the logic control unit 110 may be connected to the upper computer through a communication interface module (not shown), such as a Gigabit communication interface module, so that the upper computer can send digital waveform test data to the logic control unit 110 through the Gigabit communication interface module after responding to user operations to generate the digital waveform test data.
In addition, in this embodiment of the application, after receiving the digital waveform test feedback data sent by the target chip to be tested 700, the upper computer may specifically determine whether the digital waveform test data and the digital waveform test feedback data are consistent, so as to obtain a test result of the target chip to be tested 700. For example, if the digital waveform test data and the digital waveform test feedback data are consistent, the target chip 700 to be tested is considered to have good performance, and if the digital waveform test data and the digital waveform test feedback data are not consistent, the target chip 700 to be tested is considered to be unqualified. The consistency of the digital waveform test data and the digital waveform test feedback data is understood to mean that the signal amplitude and the signal period of the digital waveform test data and the digital waveform test feedback data are consistent.
In the process of testing the target chip 700 to be tested by the converter chip test circuit 100 provided in the embodiment of the present application, since the signal conditioning circuit 130 is configured to send the analog waveform test data to the target chip 700 to be tested after the signal-to-noise ratio of the analog waveform test data is increased, the signal quality of the analog waveform test data can be ensured, then, the subsequent target chip 700 to be tested converts the analog waveform test data into digital waveform test feedback data and sends the digital waveform test feedback data to the upper computer, and the upper computer can ensure the accuracy of the test result after obtaining the test result of the target chip 700 to be tested according to the digital waveform test data and the digital waveform test feedback data.
Referring to fig. 2, in the embodiment of the present application, the converter chip test circuit 100 may further include a Data Memory 140, for example, a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), and the Data Memory 140 is connected to the logic control unit 110.
The logic control unit 110 may be configured to store the digital waveform test data in the data memory 140 after receiving the digital waveform test data sent by the upper computer, obtain the digital waveform test data from the data memory 140 after receiving an initial test signal sent by the upper computer, and send the digital waveform test data to the digital-to-analog conversion circuit 120, where the initial test signal carries identification information of the digital waveform test data.
Through the above arrangement, the upper computer may first send a plurality of pieces of digital waveform test data and store the digital waveform test data in the data memory 140, and then, when each piece of initial test signal is received by the logic control unit 110, the identification information is extracted from the initial test signal, the digital waveform test data indicated by the identification information is obtained from the data memory 140, and the digital waveform test data is sent to the digital-to-analog conversion circuit 120, so that the storage and subsequent tests of the digital waveform test data are divided in stages, thereby reducing the operation complexity of the test system.
Referring to fig. 3, in the embodiment of the present disclosure, the digital-to-analog converting circuit 120 may include a plurality of digital-to-analog converters having different bit depths, and the plurality of digital-to-analog converters are respectively connected to the signal conditioning circuit 130 through the corresponding first switching devices 150.
Illustratively, the plurality of digital-to-analog converters may include a first digital-to-analog converter with a depth of 16 bits, and may also include a second digital-to-analog converter with a depth of 24 bits. The first digital-to-analog converter with the depth of 16 bits is matched with the signal conditioning circuit 130 to form a high-performance signal generation module, the signal bandwidth of the high-performance signal generation module is 80M and can meet the test of a video target chip 700 to be tested, and the second digital-to-analog converter with the depth of 24 bits is matched with the signal conditioning circuit 130 to form a high-precision signal generation module, the signal bandwidth of the high-precision signal generation module is 22K and can meet the test of the audio target chip 700 to be tested.
In addition, it can be understood that, in the embodiment of the present application, in the multiple digital-to-analog converters, the first switching device 150 corresponding to each digital-to-analog converter may be implemented by multiple controllable switch contact groups included in one relay, or by at least one controllable switch contact group included in each relay in the multiple relays, and the on/off of the controllable switch contact group may be automatically controlled by the logic control unit 110, which is not described herein again in this embodiment of the present application.
For example, in the case of a first digital-to-analog converter with a depth of 16bit and a second digital-to-analog converter with a depth of 24bit included in the plurality of digital-to-analog converters, one set of differential signals output by the first digital-to-analog converter may be switchably connected to the dynamic switch contacts included in the first relay through two static switch contacts included in the first relay, respectively, so as to be further connected to the signal conditioning circuit 130, and another set of differential signals output by the second digital-to-analog converter may be switchably connected to the dynamic switch contacts included in the second relay through two static switch contact sets included in the second relay, respectively, so as to be further connected to the signal conditioning circuit 130.
Based on the above analysis, it can be understood that, in the embodiment of the present application, through the above setting, the test requirements of the target chip 700 to be tested with different bit depths can be met, so that the applicable range of the conversion chip test circuit is increased.
Referring to fig. 4, in the embodiment of the present application, the signal conditioning circuit 130 may include a driving circuit 131 and a filtering circuit 132, and the driving circuit 131 is connected to the digital-to-analog converting circuit 120 and the filtering circuit 132, respectively. The driving circuit 131 is configured to send the analog waveform test data to the filter circuit 132 after performing amplification processing on the analog waveform test data. The filter circuit 132 is configured to perform filtering processing on the analog waveform test data to improve a signal-to-noise ratio of the analog waveform test data, and then send the analog waveform test data to the target chip 700 to be tested.
Through the above arrangement, the converter chip test circuit 100 provided in the embodiment of the present application realizes the design of the signal conditioning circuit 130 through the simple driving circuit 131 and the simple filtering circuit 132, and therefore, the design and manufacturing cost of the converter chip test circuit can be reduced.
In the signal conditioning circuit 130, the driving circuit 131 may include two first buffers 1311(Buffer amplifiers) and an amplifying circuit 1312, an output signal of the first Buffer 1311 may always follow an input signal thereof to perform an impedance conversion function, and the amplifying circuit 1312 may be implemented by a differential operational Amplifier such as an LMH 6552. Based on this, taking the amplification circuit 1312 implemented by an LMH6552 differential operational amplifier as an example, in practical implementation, in a plurality of digital-to-analog converters included in the digital-to-analog conversion circuit 120, a set of differential signals output by each digital-to-analog converter is respectively connected to the input ends of two first buffers 1311 through corresponding first switching devices 150, and the output ends of the two first buffers 1311 are respectively connected to two input pins (Pin1 and Pin8) of the LMH6552 differential operational amplifier, and two output pins (Pin4 and Pin5) of the LMH6552 differential operational amplifier are respectively connected to two filters included in the filtering circuit 132, and these two filters can be regarded as a set of filters. Of course, in the plurality of digital-to-analog converters included in the digital-to-analog conversion circuit 120, the signal output by each digital-to-analog converter may also be a single-ended signal, and at this time, the signal conditioning circuit 130 may be modified adaptively, which is not described in detail in this embodiment of the application.
Further, in the embodiment of the present application, the filter circuit 132 may include a plurality of sets of filters, the plurality of sets of filters have different filtering frequency parameters, and the plurality of sets of filters are respectively connected to the driving circuit 131 through the corresponding second switching devices 160. Continuing with the example where the amplifying circuit 1312 is implemented by an LMH6552 differential operational amplifier, two filters included in each group of filters are connected to two output pins (Pin4 and Pin5) of the LMH6552 differential operational amplifier through corresponding second switching devices 160, respectively.
For example, the multiple sets of filters may include a set of first filters with a filtering frequency parameter of 80MHz, a set of second filters with a filtering frequency parameter of 15MHz, a set of third filters with a filtering frequency parameter of 2.5MHz, and a set of fourth filters with a filtering frequency parameter of 20KHz, which is not limited by the embodiment of the present application.
In addition, it can also be understood that, in the embodiment of the present application, in multiple groups of filters, the second switch device 160 corresponding to each group of filters may be implemented by multiple controllable switch contact groups included in one relay, or by at least one controllable switch contact group included in each relay in multiple relays, and the on/off of the controllable switch contact group may be automatically controlled by the logic control unit 110, which is not described in detail in this embodiment of the present application.
For example, in the case where a set of first filters, a set of second filters, a set of third filters, and a set of fourth filters are included in the plurality of sets of filters, one first filter in the first filter set, one second filter in the second filter set, one third filter in the third filter set, and one fourth filter in the fourth filter set may be switchably engaged to a dynamic switch contact included in the third relay through four static switch contacts included in the third relay, respectively, to further connect with the drive circuit 131, and another first filter in the first filter set, another second filter in the second filter set, another third filter in the third filter set, and another fourth filter in the fourth filter set may be switchably engaged to a dynamic switch contact included in the fourth relay through four static switch contact sets included in the fourth relay, respectively, to be further connected with the driving circuit 131.
When a high-performance signal needs to be generated, a first filter with a filtering frequency parameter of 80MHz, a second filter with a filtering frequency parameter of 15MHz or a third filter with a filtering frequency parameter of 2.5MHz can be connected to the driving circuit 131 by switching on and off of four controllable switch contact sets in a third relay and a fourth relay according to the signal frequency required by the target chip 700 to be tested, so that the high signal-to-noise ratio of the video signal is ensured. For example, when the signal frequency required by the target chip 700 to be tested is greater than 15MHz, the first filter with the filtering frequency parameter of all 80MHz is connected to the driving circuit 131 by switching on and off the four controllable switch contact sets in the third relay and the fourth relay. For another example, when the signal frequency required by the target chip 700 to be tested is a 10MHz signal, the second filter with the filtering frequency parameter of 15MHz is connected to the driving circuit 131 by switching on and off the four controllable switch contact sets in the third relay and the fourth relay. For another example, when the signal frequency required by the target chip 700 to be tested is a 1MHz signal, the third filter with the filtering frequency parameter of 2.5MHz is connected to the driving circuit 131 by switching on and off the four controllable switch contact sets in the third relay and the fourth relay.
When a high-precision signal needs to be generated, the fourth filter with the filtering frequency parameter of 20KHz can be connected into the driving circuit 131 by switching on and off the four controllable switch contact sets in the third relay and the fourth relay, so that high-frequency noise is filtered, and the high signal-to-noise ratio of the audio signal is ensured.
Please combine the following equations:
SNR＝PSignal,dBm-PNoise,dBm (2)
PNoise,dBm＝10logPNoise,dBm/Hz+10log BWHz (3)
wherein SNR is the signal-to-noise ratio, PSignalIs the signal power, PNoiseBW is the signal bandwidth, the signal-to-noise ratio, i.e., the ratio of the signal power to the noise power, can be seen from equation (1), and the 10log reduction can be seen from equations (2) and (3) by using the low pass filterPnoise,dbm/HzThat is, the power spectral density of the noise is reduced, thereby improving the signal-to-noise ratio.
Finally, a high performance signal generated by the signal conditioning circuit 130 provided by the embodiment of the present application is shown in fig. 5, and a high precision signal generated by the signal conditioning circuit 130 provided by the embodiment of the present application is shown in fig. 6, which both have a high signal-to-noise ratio.
Based on the above analysis, it can be understood that, in the embodiment of the present application, through the above setting, the converter chip test circuit 100 provided in the embodiment of the present application can not only improve the signal-to-noise ratio of the analog waveform test data, but also meet the test requirements of the target to-be-tested chip 700 with different required signal frequencies, thereby improving the applicable range of the converter chip test circuit.
Further, in the embodiment of the present application, in the case that the filter circuit 132 includes multiple sets of filters, the multiple sets of filters may be respectively connected to the target chip 700 to be tested through the corresponding third switching devices 170, and by switching the third switching devices, which set of filters of the multiple sets of filters is connected to the target chip 700 to be tested can be selected. Similarly, it can be understood that, in the embodiments of the present application, in multiple groups of filters, the third switching device 170 corresponding to each group of filters may be implemented by multiple controllable switch contact groups included in one relay, or by at least one controllable switch contact group included in each relay in multiple relays, and the on/off of the controllable switch contact group may be automatically controlled by the logic control unit 110, which is not described in detail in this application.
For example, in the case where the plurality of sets of filters include a set of first filters, a set of second filters, a set of third filters, and a set of fourth filters, one first filter in the first filter set, one second filter in the second filter set, one third filter in the third filter set, and one fourth filter in the fourth filter set may be switchably connected to the dynamic switch contact included in the fifth relay through four static switch contact sets included in the fifth relay, respectively, to further connect with the target chip under test 700, and another first filter in the first filter set, another second filter in the second filter set, another third filter in the third filter set, and another fourth filter in the fourth filter set may be switchably connected to the dynamic switch contact included in the sixth relay through four static switch contact sets included in the sixth relay, respectively, for further connection with the target chip 700 to be tested.
Referring to fig. 7, in the embodiment of the present application, the converter chip test circuit 100 may further include an analog-to-digital conversion acquisition circuit 180, and an input terminal of the analog-to-digital conversion acquisition circuit 180 is connected to an output terminal of the signal conditioning circuit 130 through the third switching device 170. The analog-to-digital conversion acquisition circuit 180 may be a 24-bit deep analog-to-digital conversion chip.
Under the condition that the converter chip test circuit 100 further includes the analog-to-digital conversion acquisition circuit 180, the logic control unit 110 is further configured to send the digital waveform calibration data to the digital-to-analog conversion circuit 120 after receiving the digital waveform calibration data sent by the upper computer, and the digital-to-analog conversion circuit 120 is further configured to convert the digital waveform calibration data into analog waveform calibration data and send the analog waveform calibration data to the signal conditioning circuit 130. When the third switching device 170 is turned on, the signal conditioning circuit 130 is further configured to send the analog waveform calibration data to the analog-to-digital conversion acquisition circuit 180 after the signal-to-noise ratio of the analog waveform calibration data is raised, and the analog-to-digital conversion acquisition circuit 180 is configured to convert the analog waveform calibration data into digital waveform calibration feedback data and send the digital waveform calibration feedback data to the upper computer. Wherein the digital waveform calibration data may be generated in response to a user manipulation, and the digital waveform calibration data is a sequence of alternating signal quantities.
Thereafter, the upper computer is configured to obtain a linear calibration parameter according to the digital waveform calibration data and the digital waveform calibration feedback data, and send the digital waveform test data and the linear calibration parameter to the logic control unit 110, based on which the logic control unit 110 is specifically configured to send the digital waveform test data to the digital-to-analog conversion circuit 120 after performing linear calibration on the digital waveform test data through the linear calibration parameter. The linear calibration parameters may include Gain (Gain) and Offset (Offset), among others.
Through the above arrangement, the converter chip test circuit 100 provided in the embodiment of the present application can ensure that the target digital waveform test data expected to be input to the converter chip test circuit 100 is substantially consistent with the actual analog waveform test signal output by the converter chip test circuit 100, that is, the target digital waveform test data has substantially consistent signal amplitude and signal period, so that the non-linearity problem of the analog waveform test data subsequently output by the converter chip test circuit 100 is reduced, and finally, the accuracy of the test result can be further improved. In addition, as described above, the third switching device 170 may be implemented by a plurality of controllable switch contact groups included in one relay, or by at least one controllable switch contact group included in each relay among the plurality of relays, and the on/off of the controllable switch contact group may be automatically controlled by the logic control unit 110, which is not described in this embodiment.
Referring to fig. 8, for example, in a case where the signal conditioning circuit 130 includes a driving circuit 131 and a filtering circuit 132, the filtering circuit 132 may include a plurality of sets of filters, and the plurality of sets of filters include a set of first filter, a set of second filter, a set of third filter and a set of fourth filter, one first filter in the first filter set, one second filter in the second filter set, one third filter in the third filter set and one fourth filter in the fourth filter set may be switchably connected to a dynamic switch contact included in the fifth relay through four static switch contact sets included in the fifth relay, respectively, so as to be further connected to the analog-to-digital conversion acquisition circuit 180, and another first filter in the first filter set, another second filter in the second filter set, another third filter in the third filter set and another fourth filter in the fourth filter set may be divided into two The dynamic switch contacts included in the sixth relay can be switched on and off through four static switch contact groups included in the sixth relay, so as to be further connected with the analog-to-digital conversion acquisition circuit 180.
In addition, it should be noted that, in order to avoid that the signal conditioning circuit 130 sends the analog waveform calibration data to the target chip 700 to be tested in the early calibration stage, and meanwhile, in order to avoid that the signal conditioning circuit 130 sends the analog waveform test data to the analog-to-digital conversion acquisition circuit 180 in the subsequent test stage, in this embodiment of the application, the third switching device 170 may be connected to the target chip 700 to be tested through the fourth switching device 190, similarly, the analog-to-digital third switching device 170 may be connected to the analog-to-digital conversion acquisition circuit 180 through the fifth switching device 200, and on and off of the fourth switching device 190 and the fifth switching device 200 may be automatically controlled through the logic control unit 110.
In the case where the third switching device 170 between the signal conditioning circuit 130 and the analog-to-digital conversion acquisition circuit 180 is implemented by the aforementioned fifth relay and sixth relay, two fourth switching devices 190 may be provided, wherein, the input end of one fourth switching device 190 is connected with the dynamic switch contact of the fifth relay, the output end is connected with the target chip 700 to be tested, the input end of the other fourth switching device 190 is connected with the dynamic switch contact of the sixth relay, the output end is connected with the target chip 700 to be tested, similarly, two fifth switching devices 200 can be provided, the input end of one fifth switching device 200 is connected with the dynamic switch contact of the fifth relay, the output end of the fifth switching device is connected with the target chip 700 to be tested, the input end of the other fifth switching device 200 is connected with the dynamic switch contact of the sixth relay, and the output end of the fifth switching device is connected with the target chip 700 to be tested.
Referring to fig. 9, in the embodiment of the present application, the converter chip test circuit 100 may further include a dc offset calibration circuit 210, and the dc offset calibration circuit 210 is connected to the logic control unit 110 and the signal conditioning circuit 130, respectively. The dc offset calibration circuit 210 may include a 16bit deep digital-to-analog conversion chip.
The dc offset calibration circuit 210 is configured to convert the dc offset calibration parameter into analog dc offset calibration data after receiving the dc offset calibration parameter sent by the upper computer, and apply the analog dc offset calibration data to the signal conditioning circuit 130. Based on this, the signal conditioning circuit 130 is further configured to perform dc offset calibration on the analog waveform test data according to the analog dc offset calibration data, and then perform signal-to-noise ratio enhancement on the analog waveform test data.
Referring to fig. 8 again, in the case that the signal conditioning circuit 130 includes the driving circuit 131, and the driving circuit 131 includes the amplifying circuit 1312, and the amplifying circuit 1312 is implemented by an LMH6552 differential operational Amplifier, the output terminal of the dc offset calibration circuit 210 may be connected to the zero offset input Pin (Pin2) of the LMH6552 differential operational Amplifier through the second Buffer 220(Buffer Amplifier).
Regarding the dc offset calibration parameter, in the embodiment of the present application, the dc offset calibration parameter may be obtained by:
the upper computer generates the dc offset calibration data and sends the dc offset calibration data to the logic control unit 110, the logic control unit 110 sends the dc offset calibration data to the digital-to-analog conversion circuit 120, and the digital-to-analog conversion circuit 120 converts the dc offset calibration data into analog offset calibration data and sends the analog offset calibration data to the signal conditioning circuit 130. When the third switching device 170 is turned on, the signal conditioning circuit 130 sends the analog bias receipt calibration data to the analog-to-digital conversion acquisition circuit 180 after the signal-to-noise ratio of the analog bias receipt calibration data is improved, converts the analog bias receipt calibration data into digital bias receipt calibration feedback data through the analog-to-digital conversion acquisition circuit 180, and sends the digital bias receipt calibration feedback data to the upper computer. The dc offset calibration data may be a dc level signal "0".
Thereafter, the upper computer obtains a dc offset calibration parameter for compensating a zero offset (Hwoffset) of the actual analog waveform test signal output by the converter chip test circuit 100 with respect to the target digital waveform test data expected to be input to the converter chip test circuit 100, according to the dc offset calibration data and the digital offset calibration feedback data.
In addition, in order to simultaneously satisfy the testing of multiple target chips 700 to be tested, thereby improving the testing efficiency, in the embodiment of the present application, multiple sets of the digital-to-analog conversion circuit 120 and the signal conditioning circuit 130 may be provided, as shown in fig. 10. Of course, in the case that the converter chip test circuit 100 further includes the analog-to-digital conversion acquisition circuit 180 and the dc offset calibration circuit 210, the number of the analog-to-digital conversion acquisition circuit 180 and the dc offset calibration circuit 210 may also be set to match the digital-to-analog conversion circuit 120 and the signal conditioning circuit 130.
It should be noted that, in the case that the plurality of digital-to-analog converters includes a first digital-to-analog converter with a depth of 16bit and a second digital-to-analog converter with a depth of 24bit, since the second digital-to-analog converter may be a four-channel chip, the four sets of digital-to-analog conversion circuits 120 may share one second digital-to-analog converter, so as to further reduce the design and manufacturing cost of the converter test circuit, as shown in fig. 10.
In addition, in the embodiment of the present application, the signal conditioning circuit 130 may be disposed on a motherboard card formed by the logic control unit 110 and the digital-to-analog conversion circuit 120 in a daughter card manner. Thus, when the daughter board card is damaged, a new daughter board card can be replaced conveniently, so that the whole converter chip test circuit 100 is prevented from being scrapped, and the test cost is reduced.
Referring to fig. 11, an embodiment of the present application further provides a converter chip testing system 10, which includes an upper computer 400 and the converter chip testing circuit 100, where the converter chip testing circuit 100 is connected to the upper computer 400, and as mentioned above, the converter chip testing circuit 100 includes a logic control unit 110, a digital-to-analog conversion circuit 120 and a signal conditioning circuit 130, and the digital-to-analog conversion circuit 120 is connected to the logic control unit 110 and the signal conditioning circuit 130, respectively.
The upper computer 400 is configured to generate digital waveform test data and send the digital waveform test data to the converter chip test circuit 100. The logic control unit 110 in the converter chip test circuit 100 is configured to send the digital waveform test data to the digital-to-analog conversion circuit 120 after receiving the digital waveform test data sent by the upper computer 400. The digital-to-analog conversion circuit 120 is configured to convert the digital waveform test data into analog waveform test data, and send the analog waveform test data to the signal conditioning circuit 130. The signal conditioning circuit 130 in the converter chip test circuit 100 is configured to send the analog waveform test data to the target chip to be tested 700 after the signal-to-noise ratio of the analog waveform test data is improved, so that the target chip to be tested 700 converts the analog waveform test data into digital waveform test feedback data and sends the digital waveform test feedback data to the upper computer 400, and the upper computer 400 is configured to obtain a test result of the target chip to be tested 700 according to the digital waveform test data and the digital waveform test feedback data.
In addition, referring to fig. 12, in practical implementation, the target chip to be tested 700 may send the Digital waveform test feedback data to the upper computer 400 through the Digital Control board 1000 (Digital/Control).
In summary, in the process of testing the target chip 700 to be tested by the converter chip test circuit 100 provided in the embodiment of the present application, the logic control unit 110 is configured to send the digital waveform test data to the digital-to-analog conversion circuit 120 after receiving the digital waveform test data sent by the host computer, the digital-to-analog conversion circuit 120 is configured to convert the digital waveform test data into the analog waveform test data and send the analog waveform test data to the signal conditioning circuit 130, because the signal conditioning circuit 130 is configured to send the analog waveform test data to the target chip 700 to be tested after performing signal-to-noise ratio enhancement on the analog waveform test data, the signal quality of the analog waveform test data can be ensured, and then the subsequent target chip 700 to be tested converts the analog waveform test data into the digital waveform test feedback data and sends the digital waveform test feedback data to the host computer, and the upper computer can ensure the accuracy of the test result after obtaining the test result of the target chip 700 to be tested according to the digital waveform test data and the digital waveform test feedback data.
The converter chip testing system 10 provided in the embodiment of the present application has the same advantages as the converter chip testing circuit 100, and is not described herein again.
In the description of the present application, it should be noted that, unless otherwise explicitly specified or limited, the terms "connected" and "disposed" should be interpreted broadly, for example, they may be mechanically fixed, detachably connected or integrally connected, they may be electrically connected, and they may be communicatively connected, where the communications connection may be a wired communications connection or a wireless communications connection, and furthermore, they may be directly connected, indirectly connected through an intermediate medium, or be communicated between two elements. Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
The above description is only a few examples of the present application and is not intended to limit the present application, and those skilled in the art will appreciate that various modifications and variations can be made in the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A converter chip test circuit is characterized by comprising a logic control unit, a digital-to-analog conversion circuit and a signal conditioning circuit, wherein the digital-to-analog conversion circuit is respectively connected with the logic control unit and the signal conditioning circuit;
the logic control unit is used for sending the digital waveform test data to the digital-to-analog conversion circuit after receiving the digital waveform test data sent by the upper computer;
the digital-to-analog conversion circuit is used for converting the digital waveform test data into analog waveform test data and sending the analog waveform test data to the signal conditioning circuit;
the signal conditioning circuit is used for sending the analog waveform test data to a target chip to be tested after the signal to noise ratio of the analog waveform test data is improved, so that the target chip to be tested converts the analog waveform test data into digital waveform test feedback data and sends the digital waveform test feedback data to the upper computer, and the upper computer is used for obtaining a test result of the target chip to be tested according to the digital waveform test data and the digital waveform test feedback data.
2. The converter chip test circuit according to claim 1, further comprising a data memory, the data memory being connected to the logic control unit;
the logic control unit is used for storing the digital waveform test data in the data memory after receiving the digital waveform test data sent by the upper computer, acquiring the digital waveform test data from the data memory after receiving an initial test signal sent by the upper computer, and sending the digital waveform test data to the digital-to-analog conversion circuit, wherein the initial test signal carries identification information of the digital waveform test data.
3. The converter chip test circuit according to claim 1, wherein the digital-to-analog conversion circuit comprises a plurality of digital-to-analog converters, the digital-to-analog converters have different bit depths, and the digital-to-analog converters are respectively connected to the signal conditioning circuit through corresponding first switching devices.
4. The converter chip test circuit according to claim 1, wherein the signal conditioning circuit comprises a driving circuit and a filtering circuit, and the driving circuit is connected to the digital-to-analog conversion circuit and the filtering circuit respectively;
the drive circuit is used for transmitting the analog waveform test data to the filter circuit after amplifying the analog waveform test data;
the filter circuit is used for carrying out filtering processing on the analog waveform test data so as to improve the signal-to-noise ratio of the analog waveform test data, and then sending the analog waveform test data to a target chip to be tested.
5. The converter chip test circuit according to claim 4, wherein the filter circuit comprises a plurality of sets of filters having different filter frequency parameters, and the plurality of sets of filters are respectively connected to the driving circuit through corresponding second switching devices.
6. The converter chip test circuit according to claim 1, further comprising an analog-to-digital conversion acquisition circuit, wherein an input terminal of the analog-to-digital conversion acquisition circuit is connected to an output terminal of the signal conditioning circuit through a third switching device;
the logic control unit is also used for sending the digital waveform calibration data to the digital-to-analog conversion circuit after receiving the digital waveform calibration data sent by the upper computer;
the digital-to-analog conversion circuit is also used for converting the digital waveform calibration data into analog waveform calibration data and sending the analog waveform calibration data to the signal conditioning circuit;
when the third switching device is turned on, the signal conditioning circuit is further configured to send the analog waveform calibration data to the analog-to-digital conversion acquisition circuit after the signal-to-noise ratio of the analog waveform calibration data is improved;
the analog-to-digital conversion acquisition circuit is used for converting the analog waveform calibration data into digital waveform calibration feedback data and sending the digital waveform calibration feedback data to the upper computer, and the upper computer is used for obtaining linear calibration parameters according to the digital waveform calibration data and the digital waveform calibration feedback data and sending the digital waveform test data and the linear calibration parameters to the logic control unit;
the logic control unit is specifically configured to send the digital waveform test data to the digital-to-analog conversion circuit after the digital waveform test data is linearly calibrated by the linear calibration parameter.
7. The converter chip test circuit according to claim 1, further comprising a dc offset calibration circuit, the dc offset calibration circuit being connected to the logic control unit and the signal conditioning circuit, respectively;
the direct current offset calibration circuit is used for converting the direct current offset calibration parameters into analog direct current offset calibration data after receiving the direct current offset calibration parameters sent by the upper computer, and applying the analog direct current offset calibration data to the signal conditioning circuit;
the signal conditioning circuit is further configured to perform signal-to-noise ratio enhancement on the analog waveform test data after performing dc offset calibration on the analog waveform test data according to the analog quantity dc offset calibration data.
8. The converter chip test circuit according to any one of claims 1 to 7, wherein a plurality of sets of the digital-to-analog conversion circuit and the signal conditioning circuit are provided.
9. The converter chip test circuit according to claim 8, wherein the signal conditioning circuit is disposed on a motherboard card formed by the logic control unit and the digital-to-analog conversion circuit in a daughter board manner.
10. A converter chip test system is characterized by comprising an upper computer and a converter chip test circuit according to any one of claims 1 to 9, wherein the converter chip test circuit is connected with the upper computer;
the upper computer is used for generating digital waveform test data and sending the digital waveform test data to the converter chip test circuit.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101762760A (en) * | 2010-01-05 | 2010-06-30 | 河北旭辉电气股份有限公司 | High-speed power waveform recording and analyzing instrument |
| CN105959067A (en) * | 2016-04-22 | 2016-09-21 | 北京联盛德微电子有限责任公司 | Calibration method and device for transmitter chip |
| CN207939511U (en) * | 2018-04-09 | 2018-10-02 | 成都泰格微电子研究所有限责任公司 | A kind of RF transceiver chip |
| CN111398781A (en) * | 2020-03-25 | 2020-07-10 | 合肥悦芯半导体科技有限公司 | Analog chip test circuit and system |
| WO2021133372A1 (en) * | 2019-12-23 | 2021-07-01 | Intel Corporation | Semiconductor chip providing on-chip self-testing of an analog-to-digital converter implemented in the semiconductor chip |
| CN114121139A (en) * | 2022-01-27 | 2022-03-01 | 合肥悦芯半导体科技有限公司 | Chip testing method and device, electronic equipment and storage medium |
| CN114121140A (en) * | 2022-01-28 | 2022-03-01 | 合肥悦芯半导体科技有限公司 | Chip testing method, system, electronic device and storage medium |
-
2022
- 2022-03-11 CN CN202210238785.0A patent/CN114624571B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101762760A (en) * | 2010-01-05 | 2010-06-30 | 河北旭辉电气股份有限公司 | High-speed power waveform recording and analyzing instrument |
| CN105959067A (en) * | 2016-04-22 | 2016-09-21 | 北京联盛德微电子有限责任公司 | Calibration method and device for transmitter chip |
| CN207939511U (en) * | 2018-04-09 | 2018-10-02 | 成都泰格微电子研究所有限责任公司 | A kind of RF transceiver chip |
| WO2021133372A1 (en) * | 2019-12-23 | 2021-07-01 | Intel Corporation | Semiconductor chip providing on-chip self-testing of an analog-to-digital converter implemented in the semiconductor chip |
| CN111398781A (en) * | 2020-03-25 | 2020-07-10 | 合肥悦芯半导体科技有限公司 | Analog chip test circuit and system |
| CN114121139A (en) * | 2022-01-27 | 2022-03-01 | 合肥悦芯半导体科技有限公司 | Chip testing method and device, electronic equipment and storage medium |
| CN114121140A (en) * | 2022-01-28 | 2022-03-01 | 合肥悦芯半导体科技有限公司 | Chip testing method, system, electronic device and storage medium |
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