CN114613747A

CN114613747A - Semiconductor package including a dual signal wiring structure

Info

Publication number: CN114613747A
Application number: CN202111483220.0A
Authority: CN
Inventors: 崔熙正; 李稀裼; 朴浚曙; 柳凤炜
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2020-12-09
Filing date: 2021-12-07
Publication date: 2022-06-10
Also published as: US20220181288A1

Abstract

Disclosed is a semiconductor package including a duplexed signal wiring structure, including: a plurality of lower pads; an upper bonding pad; a semiconductor chip including a chip pad and configured to transmit or receive a first signal through the chip pad; a first wiring structure connecting the chip pad to a first lower pad among the plurality of lower pads; and a second wiring structure connecting a second lower pad among the plurality of lower pads to the upper pad, wherein the first and second lower pads are separated from each other by a minimum distance between the plurality of lower pads.

Description

Semiconductor package including a dual signal wiring structure

Technical Field

The present inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including a duplexed signal wiring structure.

Background

With rapid development of the electronic industry and user demand, electronic devices are increasingly expected to be miniaturized, have multiple functions, and have a large capacity (e.g., storage capacity, processing capacity, etc.), and therefore, semiconductor packages including a plurality of semiconductor chips have been used. With the high integration of a plurality of semiconductor chips included in a semiconductor package, a printed circuit board has not been able to often accommodate the high integration of the plurality of semiconductor chips. Therefore, semiconductor packages in which a plurality of semiconductor chips are vertically stacked or connected to each other by using an interposer (interposer) are being developed.

Disclosure of Invention

According to an exemplary embodiment of the inventive concept, a semiconductor package includes: a plurality of lower pads; an upper bonding pad; a semiconductor chip including a chip pad and configured to transmit or receive a first signal through the chip pad; a first wiring structure connecting the chip pad to a first lower pad among the plurality of lower pads; and a second wiring structure connecting a second lower pad among the plurality of lower pads to the upper pad, wherein the first and second lower pads are separated from each other by a minimum distance between the plurality of lower pads.

According to an exemplary embodiment of the inventive concept, a semiconductor package includes: a substrate; a first package including a plurality of lower pads, upper pads, and a first semiconductor chip and mounted on the substrate, the first semiconductor chip including a first chip pad and configured to transmit or receive a predefined signal through the first chip pad; and a second package including a second semiconductor chip and mounted on the first package or the substrate, the second semiconductor chip being controlled by the first semiconductor chip and configured to transmit or receive the predefined signal through a second chip pad of the second semiconductor chip, wherein the first package includes: a first routing structure connecting the first chip pad to a first lower pad among the plurality of lower pads and transmitting the predefined signal; and a second wiring structure connecting a second lower pad among the plurality of lower pads to the upper pad.

According to an exemplary embodiment of the inventive concept, a semiconductor package includes: a plurality of lower pads; an upper bonding pad; a semiconductor chip including a chip pad and configured to transmit or receive a first signal through the chip pad; a first wiring structure connecting the chip pad to a first lower pad among the plurality of lower pads; and a second wiring structure connecting a second lower pad among the plurality of lower pads to the upper pad, wherein the first lower pad and the second lower pad are physically separated from each other in the semiconductor package, and the first wiring structure and the second wiring structure are physically separated from each other in the semiconductor package.

Drawings

The above and other aspects of the present inventive concept will become more apparent by describing in detail embodiments thereof with reference to the attached drawings in which:

fig. 1A and 1B are sectional views of a semiconductor package according to an exemplary embodiment of the inventive concept;

fig. 2A and 2B are sectional views of a semiconductor package showing a stud structure according to a comparative example;

fig. 3 is a cross-sectional view of a first semiconductor package according to an exemplary embodiment of the inventive concept;

fig. 4A and 4B are cross-sectional views of a semiconductor package according to an exemplary embodiment of the inventive concept;

fig. 5A and 5B are bottom views of ball maps (ball maps) of a first semiconductor package according to an exemplary embodiment of the inventive concept;

fig. 6A and 6B are bottom views of ball diagrams of a first semiconductor package according to exemplary embodiments of the inventive concept;

fig. 7 is a block diagram of an electronic system according to an exemplary embodiment of the inventive concept; and

fig. 8 is a block diagram of a Universal Flash Storage (UFS) system according to an exemplary embodiment of the present inventive concept.

Detailed Description

Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

Fig. 1A and 1B are sectional views of a semiconductor package according to an exemplary embodiment of the inventive concept. For example, fig. 1A is a sectional view of a semiconductor package 10a including a first semiconductor package 100 and a second semiconductor package 200 mounted on a semiconductor board (or substrate) 300, and fig. 1B is a sectional view of a semiconductor package 10B including the second semiconductor package 200 mounted on the first semiconductor package 100. Hereinafter, the description made with reference to fig. 1A may also be applied to fig. 1B. The plane formed by the X-axis and the Y-axis may be referred to as a horizontal plane. A component disposed above a different component may be considered to be disposed in the + Z direction relative to the different component, and a component disposed below the different component may be considered to be disposed in the-Z direction relative to the different component.

Referring to fig. 1A, a semiconductor package 10a may include a first semiconductor package 100, a second semiconductor package 200, and a semiconductor board 300. The first semiconductor package 100 includes a memory controller 110 and the second semiconductor package 200 includes a memory device 210. Referring to fig. 1A, a first semiconductor package 100 and a second semiconductor package 200 may be mounted on a semiconductor board 300.

For example, the semiconductor package 10a may be implemented to be included in a Personal Computer (PC) or a mobile electronic device. For example, the mobile electronic device may be a laptop computer, a mobile phone, a smart phone, a tablet PC, a Personal Digital Assistant (PDA), an Enterprise Digital Assistant (EDA), a digital camera, a digital video camera, a Portable Multimedia Player (PMP), a personal navigation device or Portable Navigation Device (PND), a handheld game console, a Mobile Internet Device (MID), a wearable computer, an internet of things (IoT) device, an internet of everything (IoE) device, or a drone.

Memory controller 110 may control the operation of memory device 210. For example, memory controller 110 may be implemented by an Integrated Circuit (IC), a system on a chip (SoC), an Application Processor (AP), a mobile AP, a chipset, or a set of chips. For example, memory controller 110 may include a Random Access Memory (RAM), a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and/or a modem. The memory controller 110 may support a multi-media card (MMC) interface, an embedded MMC (emmc) interface, and a Universal Flash Storage (UFS) interface, but is not limited thereto.

For example, the memory device 210 may be implemented by a non-volatile memory device. For example, the memory device 210 may be implemented by an Electrically Erasable Programmable Read Only Memory (EEPROM), a flash memory, a Magnetic Random Access Memory (MRAM), a spin transfer torque MRAM (STT-MRAM), a ferroelectric ram (feram), a phase change ram (pram), a Resistive Ram (RRAM), a nanotube RRAM, a polymer ram (ponam), a Nano Floating Gate Memory (NFGM), a holographic memory, a molecular electronic memory device, an insulator resistance change memory, and the like.

According to an exemplary embodiment of the inventive concept, the memory device 210 may include a volatile memory device. For example, volatile memory devices can be implemented with, but are not limited to, RAM, Dynamic RAM (DRAM), or Static RAM (SRAM). For example, memory device 210 may include a wide input/output (I/O) DRAM, a Low Power Double Data Rate (LPDDR) DRAM, and the like.

The first semiconductor package 100 may include a first wiring structure 121 and a second wiring structure 122. The first wiring structure 121 may connect connection terminals (e.g., chip pads or solder balls) of the memory controller 110 to first lower pads 131 formed at the lower surface of the first semiconductor package 100. The second wiring structure 122 may connect the second lower pads 132 formed at the lower surface of the first semiconductor package 100 to the upper pads 133 formed at the upper surface of the first semiconductor package 100.

For example, the first wiring structure 121 and the second wiring structure 122 may be multiplexed to transmit the same type of signal. The first and second

lower pads

131 and 132 may be used for the same type of signal. For example, the first and second

lower pads

131 and 132 may be dedicated to the same type of signal. For example, the first and

second wiring structures

121 and 122 may be multiplexed to transmit the reference clock signal CK, and the first and second

lower pads

131 and 132 may be dedicated to the reference clock signal CK. Accordingly, only the reference clock signal CK may flow through the first and

second wiring structures

121 and 122 and the first and second

lower pads

131 and 132. The first and

second wiring structures

121 and 122 may be physically separated from each other in the first semiconductor package 100.

The second semiconductor package 200 may include a third wiring structure 221. The third wiring structure 221 may connect connection terminals (e.g., chip pads or solder balls) of the memory device 210 to lower pads 231 formed at the lower surface of the second semiconductor package 200.

Referring to fig. 1A, the semiconductor board 300 may include a fourth wiring structure 321 forming a signal path between the memory controller 110 and the memory device 210. As shown in fig. 1A, when the second semiconductor package 200 is mounted on the semiconductor board 300, the fourth wiring structure 321 may electrically connect the first wiring structure 121 to the third wiring structure 221. In other words, memory controller 110 may be connected to memory device 210. For example, the memory controller 110 and the memory device 210 may exchange signals of a predefined type through the first wiring structure 121, the third wiring structure 221, and the fourth wiring structure 321. When the second semiconductor package 200 is mounted on the semiconductor board 300, the second wiring structure 122 may not be used to transmit the predefined type of signal.

Referring to fig. 1B, the semiconductor board 300 may include a fifth wiring structure 322 forming a path between the memory controller 110 and the memory device 210. As shown in fig. 1B, when the second semiconductor package 200 is mounted on the first semiconductor package 100, the fifth wiring structure 322 may electrically connect the first wiring structure 121 to the second wiring structure 122. The second wiring structure 122 may be electrically connected to the third wiring structure 221. In other words, memory controller 110 is connected to memory device 210. For example, memory controller 110 and memory device 210 may exchange signals of a predefined type through first wiring structure 121, second wiring structure 122, third wiring structure 221, and fifth wiring structure 322.

Referring to fig. 1B, the first and second

lower pads

131 and 132 may be separated from each other by a minimum distance dmin. The minimum distance dmin may be a minimum distance between external connection terminals (e.g., solder balls) formed on the lower surface of the first semiconductor package 100. Accordingly, the signal path may be shortened so that the memory controller 110 and the memory device 210 may stably exchange the predefined type of signal.

Referring to fig. 1A and 1B, the first and

second wiring structures

121 and 122 are selectively connected according to a location where the second semiconductor package 200 is mounted, and thus, a stud structure may not be formed on a signal path between the memory controller 110 and the memory device 210. For example, regardless of the location where the second semiconductor package 200 is mounted, the memory controller 110 and the memory device 210 may exchange signals through a signal path without a stud structure. The stud structure may represent an additional wiring formed on a main path through which a signal is transmitted.

Fig. 2A and 2B are cross-sectional views of a semiconductor package for describing a stud structure according to a comparative example. Fig. 2A is a sectional view of a semiconductor package 20a including a first semiconductor package 400 and a second semiconductor package 200 mounted on a semiconductor board 300, and fig. 2B is a sectional view of a semiconductor package 20B including the second semiconductor package 200 mounted on the first semiconductor package 400.

Referring to fig. 2A and 2B, the first semiconductor package 400 may include a first wiring structure 421. The first wiring structure 421 may connect connection terminals (e.g., chip pads or solder balls) of the memory controller 110 to the lower pads 431 formed at the lower surface of the first semiconductor package 400. In addition, the first wiring structure 421 may be branched inside the first semiconductor package 400 to be connected to the upper pad 432 formed at the upper surface of the first semiconductor package 400. For example, the first wiring structure 421 may include a first portion connected to a connection terminal of the memory controller 110 and a second portion connected to the upper pad 432 and the first portion.

As shown in fig. 2A, when the second semiconductor package 200 is mounted on the semiconductor board 300, the fourth wiring structure 321 may electrically connect the first wiring structure 421 to the third wiring structure 221. For example, the memory controller 110 and the memory device 210 may exchange predefined types of signals through the first wiring structure 421, the third wiring structure 221, and the fourth wiring structure 321. In order to transmit signals of the memory controller 110 to both the lower pad 431 and the upper pad 432, the first wiring structure 421 is branched or divided into a first portion and a second portion inside the first semiconductor package 400, and thus, a stud structure STUB may be formed from the branch point to the upper pad 432 regardless of signal exchange. The stud structure may cause the generation of a reflected signal, and the reflected signal may distort signals to be exchanged between memory controller 110 and memory device 210.

As shown in fig. 2B, when the second semiconductor package 200 is mounted on the first semiconductor package 400, the first wiring structure 421 may be electrically connected to the third wiring structure 221. For example, the memory controller 110 and the memory device 210 may exchange signals of a predefined type through the first wiring structure 421 and the third wiring structure 221. Regardless of the signal exchange, the stud structure STUB may be formed from the branch point to the lower pad 431. The stud structure may cause the generation of a reflected signal, and the reflected signal may distort signals exchanged between memory controller 110 and memory device 210.

Unlike the semiconductor packages 20a and 20B shown in fig. 2A and 2B, the semiconductor packages 10a and 10B shown in fig. 1A and 1B include a wiring structure without studs, and thus signals whose distortion is minimized can be exchanged.

Fig. 3 is a cross-sectional view of a first semiconductor package 30 according to an exemplary embodiment of the inventive concept. For example, the first semiconductor package 30 of fig. 3 may be an example of the first semiconductor package 100 of fig. 1A and 1B.

Referring to fig. 3, the first semiconductor package 30 may include a lower package 500, an interposer 600 on the lower package 500, and conductive connectors 542 electrically connecting the lower package 500 to the interposer 600.

The lower package 500 may include a package substrate 510, a semiconductor chip 520, and a molding layer 541. The lower package 500 may be, for example, a flip chip package in which a semiconductor chip 520 is mounted on a package substrate 510 in a face-down manner. In this case, the chip connection terminal 521 is disposed between the chip pad 522 of the semiconductor chip 520 and the on-substrate pad 514 of the package substrate 510, and the chip connection terminal 521 may electrically/physically connect the chip pad 522 of the semiconductor chip 520 to the on-substrate pad 514 of the package substrate 510.

The package substrate 510 may include a substrate base 512 made of at least one of a phenolic resin, an epoxy resin, and a polyimide. In addition, the package substrate 510 may include substrate upper and

lower pads

514 and 511 formed at the upper and lower surfaces of the substrate base 512, respectively. An inner wiring 513 electrically connecting the substrate upper pad 514 to the substrate lower pad 511 may be formed inside the substrate base 512.

The substrate upper pad 514 and the substrate lower pad 511 may include, for example, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), or ruthenium (Ru), or an alloy thereof, but the inventive concept is not limited thereto.

The pads 514 on the substrate may be pads to which the conductive connectors 542 are attached, or may be pads to which the chip connection terminals 521 are attached. In addition, the substrate lower pad 511 may serve as a pad to which the external connection terminal 530 is attached. The substrate lower pad 511 may be an example of the first and second

lower pads

131 and 132 described above with reference to fig. 1A and 1B. The external connection terminals 530 may be, for example, solder balls or bumps. The external connection terminal 530 may electrically connect the first semiconductor package 30 to an external device.

The semiconductor chip 520 may be mounted on the package substrate 510. The semiconductor chip 520 may include a semiconductor substrate having an active surface and a passive surface opposite to each other, and a semiconductor device layer formed on the active surface of the semiconductor substrate. The semiconductor chip 520 may include a lower surface and an upper surface opposite to each other, and the chip pad 522 may be provided at the lower surface of the semiconductor chip 520. The chip pad 522 of the semiconductor chip 520 may be electrically connected to the semiconductor device layer through a wiring structure.

The semiconductor chip 520 may be a non-memory chip. For example, the semiconductor chip 520 may be a logic chip and may be implemented in, for example, an artificial intelligence semiconductor, a microprocessor, a graphic processor, a signal processor, a network processor, a chipset, an audio codec, a video codec, an AP, or an SoC, but the inventive concept is not limited thereto. The semiconductor chip 520 may correspond to the memory controller 110 described above with reference to fig. 1A through 2B.

In an exemplary embodiment of the inventive concept, the semiconductor chip 520 may be a memory chip, and may include a volatile memory chip and/or a nonvolatile memory chip. Volatile memory chips may include, for example, DRAM, SRAM, Thyristor RAM (TRAM), capacitorless RAM (ZRAM), or Two Transistor RAM (TTRAM). Further, the non-volatile memory chip may include, for example, flash memory, MRAM, STT-MRAM, FeRAM, PRAM, RRAM, nanotube RRAM, popram, or insulator resistance change memory.

For example, the semiconductor chip 520 may be mounted on the package substrate 510 such that a lower surface of the semiconductor chip 520 where the chip pad 522 is provided faces in a downward direction. For example, the lower surface of the semiconductor chip 520 faces the upper surface of the package substrate 510. The chip pad 522 of the semiconductor chip 520 may serve as a terminal for input/output data signal transmission or a terminal for power supply and/or ground for the semiconductor chip 520.

A molding layer 541 is provided on the package substrate 510, and may cover at least a portion of the semiconductor chip 520. The molding layer 541 may protect the at least one portion of the semiconductor chip 520 from an external environment. Further, the molding layer 541 may include an underfill part filling a gap between the semiconductor chip 520 and the package substrate 510 and at least partially surrounding the chip connection terminal 521 between the semiconductor chip 520 and the package substrate 510.

For example, the molding layer 541 may be formed by injecting an appropriate amount of molding material around the semiconductor chip 520 through an injection process and hardening the molding material through a hardening process. In an exemplary embodiment of the inventive concept, a molding material for forming the molding layer 541 may include an epoxy-based molding resin, a polyimide-based molding resin, or the like. For example, the molding layer 541 may include an Epoxy Molding Compound (EMC).

The interposer 600 may be disposed on the semiconductor chip 520 and the molding layer 541. Interposer 600 may include an interposer substrate 610. The interposer substrate 610 may include an interposer substrate base 612 made of at least one of phenolic, epoxy, and polyimide. The interposer substrate 610 may include interposer upper and

lower pads

614 and 611 formed at upper and lower surfaces of the interposer substrate 612, respectively. Interposer internal routing lines 613 that electrically connect the interposer upper pads 614 to the interposer lower pads 611 may be formed inside the interposer substrate base 612.

The interposer upper pad 614 and the interposer lower pad 611 may include, for example, a metal such as Cu, Al, W, Ti, Ta, In, Mo, Mn, Co, Sn, Ni, Mg, Re, Be, Ga, or Ru or an alloy thereof, but the inventive concept is not limited thereto. The interposer upper pads 614 may be examples of the upper pads 133 described above with reference to fig. 1A and 1B.

For example, the conductive connector 542 may be separated from the sidewall of the semiconductor chip 520 in the horizontal direction. The conductive connector 542 may be received in a through hole of the molding layer 541. For example, the conductive connector 542 may have an approximately pillar shape extending in a vertical direction (e.g., a direction orthogonal to the upper surface of the package substrate 510). For example, the conductive connector 542 may have a cylindrical shape, a rectangular parallelepiped shape, or a rounded shape.

The lower ends of the conductive connectors 542 may be connected to the substrate upper pads 514 of the package substrate 510, and the upper ends of the conductive connectors 542 may be connected to the interposer lower pads 611 at the lower surface of the interposer substrate base 612. The conductive connectors 542 may electrically connect the substrate upper pads 514 of the package substrate 510 to the interposer lower pads 611 of the interposer substrate 610.

For example, the conductive connection 542 may include at least one of solder, Al, Cu, Ni, W, platinum (Pt), and gold (Au).

In an exemplary embodiment of the inventive concept, the first semiconductor package 30 may include a plurality of external connection terminals for a single chip pad 522. For example, the chip pad 522 may be a pad through which the reference clock signal CK is output, and the first and second

external connection terminals

531 and 532 may be dedicated to the reference clock signal CK. The first external connection terminal 531 may be connected to the chip pad 522 through the internal wiring 513. The second external connection terminal 532 may be connected to the on-interposer pad 614 through the internal wiring 513, the conductive connector 542, and the interposer internal wiring 613.

The inner wiring 513 connected to the chip pad 522 may be connected to the first external connection terminal 531 without branching (or, for example, splitting) inside the package substrate 510. For example, the internal wiring 513 connected to the chip pad 522 may be connected to one external connection terminal. In an exemplary embodiment of the inventive concept, the second semiconductor chip located outside the first semiconductor package 30 may exchange signals with the semiconductor chip 520 through the first external connection terminal 531. For example, since signals are exchanged through the internal wiring 513 not branched inside the package substrate 510, a signal distortion phenomenon due to the stud structure may be reduced. When the semiconductor chip 520 and the second semiconductor chip exchange signals through the first external connection terminal 531, the second external connection terminal 532 may not transmit the signal output from the semiconductor chip 520. For example, the second external connection terminal 532 may be in a non-connection (NC) state.

In an exemplary embodiment of the inventive concept, the second semiconductor chip located outside the first semiconductor package 30 may exchange signals with the semiconductor chip 520 through the on-interposer bonding pad 614. In this case, the first and second

external connection terminals

531 and 532 may be electrically connected to each other outside the first semiconductor package 30. For example, by electrically connecting the first and second

external connection terminals

531 and 532 to each other, a signal output from the chip pad 522 may be transmitted to the second semiconductor chip through the on-interposer pad 614.

Referring to fig. 3, the first and second

external connection terminals

531 and 532 may be separated from each other by a minimum distance dmin. The minimum distance dmin may be a minimum distance between the

external connection terminals

531 and 532 formed on the lower surface of the first semiconductor package 30. Therefore, even when the first and second

external connection terminals

531 and 532 are electrically connected to each other outside the first semiconductor package 30, the signal path may be shortened, and thus, the semiconductor chip 520 and the second semiconductor chip may stably exchange signals.

The first semiconductor package 30 according to an exemplary embodiment of the inventive concept may include an internal wiring 513 not branched inside the package substrate 510 so that a stud-free signal path may be provided regardless of the position of the second semiconductor chip exchanging signals with the semiconductor chip 520.

Fig. 4A and 4B are sectional views of a semiconductor package according to an exemplary embodiment of the inventive concept. For example, fig. 4A is a sectional view of a semiconductor package 40a including a first semiconductor package 100a and a second semiconductor package 200a mounted on a semiconductor board 300a, and fig. 4B is a sectional view of a semiconductor package 40B including a second semiconductor package 200B mounted on a first semiconductor package 100B. The description made above with reference to fig. 1A and 1B may also be applied to fig. 4A and 4B. Further, the description made with reference to fig. 4A may also be applied to fig. 4B.

Referring to fig. 4A, the first semiconductor package 100a may include a first semiconductor chip 110 a. For example, the first semiconductor chip 110a may be a non-memory chip. The first semiconductor package 100a may be the first semiconductor package 30 described above with reference to fig. 3. The first semiconductor chip 110a may transmit or receive a predefined signal through the chip pad 111 a. In an exemplary embodiment of the inventive concept, the predefined signal may be one of the reference clock signal CK, the reset signal Rst, the data input signal D _ in, and the data output signal D _ out. The chip pad 111a may be connected to the first lower wiring structure 121a through the chip connection terminal 112a, and the first lower wiring structure 121a may be connected to the first substrate lower pad 131 a. The first substrate lower pad 131a may be physically connected to the first external connection terminal 141a for transmitting a predefined signal to the outside. The first lower wiring structure 121A may correspond to the first wiring structure 121 described above with reference to fig. 1A.

The semiconductor board 300a may include first, second, and third

package substrate pads

311a, 312a, and 313 a. As shown in fig. 4A, when the second semiconductor package 200a is mounted on the semiconductor board 300a, the semiconductor board 300a may include a substrate wiring structure 321a formed in a substrate base of the semiconductor board 300a and connecting first package substrate pads 311a for the second semiconductor package 200a to second package substrate pads 312a for the first semiconductor package 100 a.

Referring to fig. 4A, the first semiconductor package 100a may include a structure corresponding to the second wiring structure 122 of fig. 1A. For example, the first semiconductor package 100a may include a second lower wiring structure 122a, a conductive connector 123a, and an upper wiring structure 124 a. The second lower wiring structure 122a, the conductive connector 123a, and the upper wiring structure 124a may be formed by a bypass structure physically/electrically connecting the second substrate lower pad 132a to the interposer upper pad 133 a. However, the inventive concept is not limited thereto, and the first semiconductor package 100a may include a vertical connection structure physically/electrically connecting the second substrate lower pads 132a to the interposer upper pads 133a by passing through the interposer substrate 612a, the molding layer 541a, and the substrate base 512 a. The vertical connection structure may be referred to as a Through Silicon Via (TSV). The interposer upper pads 133a of fig. 4A may correspond to the upper pads 133 of fig. 1A. The second substrate lower pad 132a of fig. 4A may correspond to the second lower pad 132 of fig. 1A.

In an exemplary embodiment of the inventive concept, the first lower wiring structure 121a may be separated from the second lower wiring structure 122 a.

As shown in fig. 4A, when the second semiconductor package 200a including the second semiconductor chip 210a is mounted on the semiconductor board 300a, the second external connection terminal 142a may be in an NC state. For example, the second external connection terminal 142a among the first and second

external connection terminals

141a and 142a may not be connected to a wiring structure (e.g., the substrate wiring structure 321a) provided to the semiconductor board 300 a. The second external connection terminals 142a may be connected to the interposer upper pads 133a through the upper wiring structure 124a, the conductive connectors 123a, the second lower wiring structure 122a, and the second substrate lower pads 132 a.

Referring to fig. 4B, the second semiconductor package 200B may be mounted on the first semiconductor package 100B. The external connection terminals 241b may be formed on the lower surface of the second semiconductor package 200 b. The external connection terminal 241b may be formed based on a ball pattern for a predefined signal. For example, the external connection terminal 241b may be formed at a predefined position on the lower surface of the second semiconductor package 200b to output or receive the reference clock signal CK, the reset signal Rst, the data input signal D _ in, or the data output signal D _ out.

The interposer upper pad 133b of the first semiconductor package 100b may be formed at a position corresponding to the ball pattern of the second semiconductor package 200 b. The second semiconductor chip 210b may output a predefined signal through the chip pad 211b, and the predefined signal may be transmitted to the external connection terminal 241b through the lower wiring structure 213 b. The external connection terminals 241b may be connected to the interposer upper pads 133b of the first semiconductor package 100 b. The predefined signal may be transmitted to the second external connection terminal 142b through the upper wiring structure 124b, the conductive connection member 123b, and the second lower wiring structure 122 b. The first and second

external connection terminals

141b and 142b may be electrically connected to each other through a substrate wiring structure 321b of the semiconductor board 300 b. Accordingly, the second semiconductor chip 210b and the first semiconductor chip 110b may exchange a predefined signal with each other.

Fig. 5A and 5B are bottom views of ball patterns of a first semiconductor package according to exemplary embodiments of the inventive concept. For example, fig. 5A and 5B illustrate the arrangement of external connection terminals formed on the lower surface of the first semiconductor package 100B illustrated in fig. 4B. Fig. 5A shows an arrangement of external connection terminals having a minimum distance in the Y-axis direction and/or the X-axis direction. For example, fig. 5A shows external connection terminals arranged in an orthogonal grid pattern. Fig. 5B shows the arrangement of the external connection terminals having the smallest distance in the direction between the X-axis direction and the Y-axis direction. For example, fig. 5B shows external connection terminals arranged in a diagonal grid pattern. For example, the arrangement of the external connection terminals may include rows and columns of the external connection terminals, and the rows of the external connection terminals may be misaligned with each other.

Referring to fig. 5A, a plurality of external connection terminals 810a may be formed on a lower surface of the first semiconductor package 100 b. Each of the plurality of external connection terminals 810a may receive or output a signal predefined according to a ball diagram. For example, each of the plurality of external connection terminals 810a may receive or output one of a positive power supply voltage VDD, a negative power supply voltage VSS, a reference clock signal CK, a reset signal Rst, first to fourth data input signals Din1 to Din4(Din1, Din2, Din3, and Din4), or one of first to fourth data output signals Do1 to Do4(Do1, Do2, Do3, and Do 4).

According to an exemplary embodiment of the inventive concept, an external connection terminal duplexed for one signal may be formed on a lower surface of the first semiconductor package 100 b. For example, the duplexed first and second

external connection terminals

821a and 822a corresponding to the reset signal Rst may be formed on the lower surface of the first semiconductor package 100 b. However, the inventive concept is not limited thereto, and a duplexed external connection terminal corresponding to each of the positive power supply voltage VDD, the negative power supply voltage VSS, the reference clock signal CK, the first to fourth data input signals Din1 to Din4, or the first to fourth data output signals Do1 to Do4 may be formed.

As described above with reference to fig. 4B, the first external connection terminal 821a may be connected to the chip pad 112B of the first semiconductor chip 110B included in the first semiconductor package 100B. For example, since the first external connection terminal 821a is connected to the first semiconductor chip 110b, the first external connection terminal 821a may be referred to as a chip connection external connection terminal. The second external connection terminal 822a may be connected to the interposer substrate 612b formed on the upper surface of the molding layer 541 b. For example, since the second external connection terminal 822a is connected to a bypass structure passing through the first semiconductor package 100b, the second external connection terminal 822a may be referred to as a bypass connection external connection terminal. The duplexed first and second

external connection terminals

821a and 822a may be electrically connected to each other through a substrate wiring structure 321b formed in the semiconductor board 300 b.

Referring to fig. 5A, the dualized first and second

external connection terminals

821a and 822a may be separated from each other by a first distance Pitch 1. The first distance Pitch 1 may be a minimum distance between the plurality of external connection terminals 810a formed on the lower surface of the first semiconductor package 100 b. Although fig. 5A illustrates that the first distance Pitch 1 is a distance in the Y-axis direction, in an exemplary embodiment of the inventive concept, the first distance Pitch 1 may be a distance in the X-axis direction. Since the first and second

external connection terminals

821a and 822a are arranged at a minimum distance, a signal path may be shortened and the first and

second semiconductor chips

110b and 210b may stably exchange signals with each other. In an exemplary embodiment of the inventive concept, unlike fig. 5A, not only the first and second

external connection terminals

821a and 822a corresponding to the reset signal Rst are separated from each other by the first distance Pitch 1, but also the duplexed external connection terminals corresponding to each of the reference clock signal CK, the first to fourth data input signals Din1 to Din4, and the first to fourth data output signals Do1 to Do4 may be separated from each other by the first distance Pitch 1.

Referring to fig. 5B, external connection terminals duplexed for one signal may be formed on the lower surface of the first semiconductor package 100B. For example, the first and second

external connection terminals

821b and 822b duplexed with respect to the first data input signal Din1 may be formed on the lower surface of the first semiconductor package 100 b.

Unlike fig. 5A, the dualized first and second external connection terminals 821B and 822B of fig. 5B may be separated from each other by a second distance Pitch 2. The second distance Pitch 2 may be a minimum distance between the plurality of external connection terminals 810b formed on the lower surface of the first semiconductor package 100 b. Unlike the first distance Pitch 1 of fig. 5A, the second distance Pitch 2 may be a minimum distance in a direction between the X-axis direction and the Y-axis direction. Since the first and second

external connection terminals

821b and 822b are arranged at a minimum distance, a signal path may be shortened and the first and

second semiconductor chips

110b and 210b may stably exchange signals between each other.

Fig. 6A and 6B are bottom views of ball patterns of a first semiconductor package according to exemplary embodiments of the inventive concepts. For example, fig. 6A and 6B illustrate the arrangement of external connection terminals formed on the lower surface of the first semiconductor package 100a illustrated in fig. 4A. Fig. 6A shows an arrangement of external connection terminals having a minimum distance in the Y-axis direction and/or the X-axis direction. For example, fig. 6A shows the external connection terminals 910a arranged in an orthogonal grid pattern. Fig. 6B shows the arrangement of the external connection terminals having the smallest distance in the direction between the X-axis direction and the Y-axis direction. For example, fig. 6B shows the external connection terminals 910B arranged in a diagonal grid pattern. For example, the arrangement of the external connection terminals may include rows and columns of the external connection terminals, and the rows of the external connection terminals may be misaligned with each other. The same description as that made with reference to fig. 5A and 5B will not be repeated.

Referring to fig. 6A, the second external connection terminal 922a may be in an NC state. For example, the second external connection terminal 922a may not be connected to a wiring structure (e.g., the substrate wiring structure 321a of fig. 4A) included in the substrate base of the semiconductor board 300 a. Further, unlike fig. 5A, the first and second

external connection terminals

921a and 922a formed on the lower surface of the first semiconductor package 100a may be electrically isolated from each other. For example, the first and

second semiconductor chips

110a and 210a may stably exchange signals through a signal path without a stud structure. Referring to fig. 6B, among the first and second external connection terminals 922B and 921B, the second external connection terminal 921B may be in an NC state.

Fig. 7 is a block diagram of an electronic system 2000 according to an exemplary embodiment of the inventive concept.

The electronic system 2000 may include a controller 2010, an input/output (I/O) device 2020, a memory 2030, and an interface 2040, and the controller 2010, the I/O device 2020, the memory 2030, and the interface 2040 may be connected to each other via a bus 2050.

For example, controller 2010 may include at least one of a microprocessor, a digital signal processor, and a similar processing device. The I/O devices 2020 may include, for example, at least one of a keypad, a keyboard, and a display. Memory 2030 may be used for storing commands that are executed by controller 2010. For example, memory 2030 may be used for storing user data.

Electronic system 2000 may form a wireless communication device or a device capable of transmitting and/or receiving information in a wireless environment. In order for the electronic system 2000 to transmit/receive data through a wireless communication network, the interface 2040 may include a wireless interface. Interface 2040 may include, for example, an antenna and/or a wireless transceiver. In an exemplary embodiment of the inventive concept, the electronic system 2000 may be used for a communication interface protocol of a third generation communication system (e.g., Code Division Multiple Access (CDMA), global system for mobile communications (GSM), North American Digital Cellular (NADC), extended time division multiple access (E-TDMA), and/or Wideband Code Division Multiple Access (WCDMA)). The controller 2010 may be implemented by the

first semiconductor package

100, 100a, or 100B described above with reference to fig. 1A, 1B, 4A, or 4B or the first semiconductor package 30 described above with reference to fig. 3. The memory 2030 may be implemented by the

second semiconductor package

200, 200a, or 200B described above with reference to fig. 1A, 1B, 4A, or 4B.

Fig. 8 is a diagram of a Universal Flash Storage (UFS) system 1000 according to an exemplary embodiment of the inventive concepts. The UFS system 1000 may be a system that conforms to UFS standards published by the Joint Electron Device Engineering Council (JEDEC), and includes a UFS host 1100, a UFS device 1200, and a UFS interface 1300. The UFS host 1100 may be included in the

first semiconductor package

100, 100a, 100B described above with reference to fig. 1A, 1B, 4A, or 4B, or the first semiconductor package 30 described above with reference to fig. 3. The UFS host 1100 may be included in the semiconductor chip 520 of fig. 3. The UFS device 1200 may be included in the

second semiconductor package

200, 200a, or 200B described above with reference to fig. 1A, 1B, 4A, or 4B.

Referring to fig. 8, UFS host 1100 may be connected to UFS device 1200 through UFS interface 1300. The UFS host controller 1110 may correspond to the memory controller 110 of fig. 1A and 1B. UFS device 1200 may correspond to memory device 210 of fig. 1A and 1B.

UFS host 1100 may include UFS host controller 1110, application 1120, UFS driver 1130, host memory 1140, and UFS Interconnect (UIC) layer 1150. UFS device 1200 may include UFS device controller 1210, non-volatile memory (NVM) storage 1220, storage interface 1230, device memory 1240, UIC layer 1250, and regulator 1260. NVM storage 1220 may include multiple memory cells 1221. Although each memory cell 1221 may include a V-NAND flash memory having a 2D structure or a 3D structure, each memory cell 1221 may include another NVM, such as a PRAM and/or RRAM. The UFS device controller 1210 may be connected to the NVM storage 1220 through a storage interface 1230. The storage interface 1230 may be configured to conform to a standard protocol, such as Toggle or ONFI.

The application 1120 may refer to a program that wants to communicate with the UFS device 1200 to use the functions of the UFS device 1200. Application 1120 may send an input/output request (IOR) to UFS driver 1130 for input/output (I/O) operations on UFS device 1200. The IOR may refer to, but is not limited to, a data read request, a data store (or write) request, and/or a data erase (or discard) request.

The UFS driver 1130 may manage the UFS host controller 1110 through a UFS-host controller interface (UFS-HCI). UFS driver 1130 may convert the IOR generated by application 1120 into UFS commands defined by the UFS standard, and send the UFS commands to UFS host controller 1110. One IOR may be converted into multiple UFS commands. The UFS command may be a command specific to the UFS standard, although the UFS command may be basically defined by the SCSI standard.

The UFS host controller 1110 may send the UFS command converted by the UFS driver 1130 to the UIC layer 1250 of the UFS device 1200 through the UIC layer 1150 of the UFS host 1100 and the UFS interface 1300. During the sending of UFS commands, UFS host register 1111 of UFS host controller 1110 may be used as a Command Queue (CQ).

The UIC layer 1150 on the UFS host 1100 side may include a Mobile Industrial Processor Interface (MIPI) M-PHY 1151 and MIPI UniPro 1152, and the UIC layer 1250 on the UFS device 1200 side may also include a MIPI M-PHY 1251 and MIPI UniPro 1252.

UFS interface 1300 may include a line configured to convey a reference clock signal REF _ CLK, a line configured to convey a hardware RESET signal RESET _ n for UFS device 1200, a pair of lines configured to convey a pair of differential input signals DIN _ T and DIN _ C, and a pair of lines configured to convey a pair of differential output signals DOUT _ T and DOUT _ C. For example, referring to fig. 5A to 6B, a line configured to transmit a hardware RESET signal RESET _ n may include a dual external connection terminal for a RESET signal Rst. The pair of lines configured to transmit the pair of differential input signals DIN _ T and DIN _ C may include dual external connection terminals for the first data input signal DIN1 through the fourth data input signal DIN4, respectively. The pair of lines configured to transmit the pair of differential output signals DOUT _ T and DOUT _ C may include dual external connection terminals for the first data output signal Do1 to the fourth data output signal Do4, respectively.

The hardware RESET signal RESET _ n may include a dual external connection terminal for the RESET signal Rst.

The frequency of the reference clock signal REF _ CLK supplied from UFS host 1100 to UFS device 1200 may be, for example, one of 19.2MHz, 26MHz, 38.4MHz, and 52MHz, but is not limited thereto. UFS host 1100 may change the frequency of reference clock signal REF _ CLK during operation (e.g., during data transmission/reception operations between UFS host 1100 and UFS device 1200). UFS device 1200 may generate clock signals having various frequencies from a reference clock signal REF _ CLK provided from UFS host 1100 by using a phase-locked loop (PLL). In addition, UFS host 1100 can set the data rate between UFS host 1100 and UFS device 1200 by using the frequency of the reference clock signal REF _ CLK. For example, the data rate may be determined depending on the frequency of the reference clock signal REF _ CLK.

UFS interface 1300 may support multiple channels, each of which may be implemented as a pair of differential lines. For example, UFS interface 1300 may include at least one receive channel and at least one transmit channel. In fig. 8, a pair of lines configured to transmit a pair of differential input signals DIN _ T and DIN _ C may constitute a receive channel, and a pair of lines configured to transmit a pair of differential output signals DOUT _ T and DOUT _ C may constitute a transmit channel. Although one transmission channel and one reception channel are illustrated in fig. 8, the number of transmission channels and the number of reception channels may vary.

The receive channel and the transmit channel may transmit data based on a serial communication scheme. Due to the structure in which the receive channel is separated from the transmit channel, full-duplex communication between UFS host 1100 and UFS device 1200 may be enabled. For example, UFS device 1200 may send data to UFS host 1100 over a send channel while receiving data from UFS host 1100 over a receive channel. Furthermore, control data (e.g., commands) from UFS host 1100 to UFS device 1200 and user data to be stored in NVM storage 1220 of UFS device 1200 by UFS host 1100 or read from NVM storage 1220 of UFS device 1200 can be transferred through the same channel. Accordingly, between the UFS host 1100 and the UFS device 1200, it may not be necessary to further provide a separate channel for data transfer, in addition to a pair of reception channels and a pair of transmission channels.

The UFS device controller 1210 of the UFS device 1200 may control all operations of the UFS device 1200. The UFS device controller 1210 may manage the NVM storage 1220 by using a Logical Unit (LU)1211 as a logical data storage unit. The number of LUs 1211 may be, for example, 8, but is not limited thereto. The UFS device controller 1210 may include a Flash Translation Layer (FTL) and translate a logical data address (e.g., a Logical Block Address (LBA)) received from the UFS host 1100 to a physical data address (e.g., a Physical Block Address (PBA)) by using address mapping information of the FTL. The logical block configured to store user data in the UFS system 1000 may have a size within a predetermined range. For example, the minimum size of a logical block may be set to about 4 Kbyte.

When a command from the UFS host 1100 is applied to the UFS device 1200 through the UIC layer 1250, the UFS device controller 1210 may perform an operation in response to the command and send a completion response to the UFS host 1100 when the operation is completed.

As an example, when UFS host 1100 intends to store user data in UFS device 1200, UFS host 1100 may send a data storage command to UFS device 1200. When a response (e.g., a "transfer ready" response) indicating that UFS device 1200 is ready to receive user data (transfer ready) is received from UFS device 1200, UFS host 1100 may send the user data to UFS device 1200. The UFS device controller 1210 may temporarily store the received user data in the device memory 1240, and store the user data temporarily stored in the device memory 1240 at a selected location of the NVM storage 1220 based on address mapping information of the FTL.

As another example, when UFS host 1100 intends to read user data stored in UFS device 1200, UFS host 1100 may send a data read command to UFS device 1200. The UFS device controller 1210, having received the command, may read user data from the NVM storage 1220 based on a data read command, and temporarily store the read user data in the device memory 1240. During a read operation, the UFS device controller 1210 may detect and correct errors in read user data by using an Error Correction Code (ECC) engine embedded therein. For example, the ECC engine may generate parity bits for write data to be written to NVM storage 1220, and the generated parity bits may be stored in NVM storage 1220 with the write data. During reading data from NVM storage 1220, the ECC engine may correct errors in the read data by using the parity bits read from NVM storage 1220 along with the read data and output the error-corrected read data.

Further, the UFS device controller 1210 may transmit user data temporarily stored in the device memory 1240 to the UFS host 1100. In addition, the UFS device controller 1210 may further include an Advanced Encryption Standard (AES) engine. The AES engine may perform at least one of an encryption operation and a decryption operation on data sent to the UFS device controller 1210 by using a symmetric key algorithm.

UFS host 1100 may sequentially store commands to be sent to UFS device 1200 in UFS host registers 1111, which may function as a command queue, and sequentially send the commands to UFS device 1200. In this case, even when a previously sent command is still being processed by the UFS device 1200, for example, even before receiving a notification that a previously sent command has been processed by the UFS device 1200, the UFS host 1100 can send the next command on standby in CQ to the UFS device 1200. Accordingly, UFS device 1200 may also receive the next command from UFS host 1100 during processing of the previously sent command. The maximum number of commands that may be stored in a CQ (or queue depth, for example) may be 32, for example. In addition, CQ may be implemented as a circular queue, where the beginning and end of a command line stored in the queue are indicated by a head pointer and a tail pointer.

Each of the plurality of memory cells 1221 may include a memory cell array and a control circuit configured to control an operation of the memory cell array. For example, the memory cell array may include a 2D memory cell array or a 3D memory cell array. The memory cell array may include a plurality of memory cells. Although each memory cell is a single-layer cell (SLC) configured to store 1 bit of information, each memory cell may be a cell configured to store 2 bits or more of information, such as a double-layer cell (MLC), a triple-layer cell (TLC), and a quad-layer cell (QLC). The 3D memory cell array may include vertical NAND strings in which at least one memory cell is vertically oriented and located on another memory cell.

Voltages VCC, VCCQ1, and VCCQ2 may be applied as power supply voltages to UFS device 1200. The voltage VCC may be a main power supply voltage for the UFS device 1200 and is in the range of about 2.4V to about 3.6V. The voltage VCCQ1 may be a power supply voltage for mainly supplying a low voltage to the UFS device controller 1210 and be in the range of about 1.14V to about 1.26V. The voltage VCCQ2 may be a supply voltage for supplying a voltage lower than the voltage VCC and higher than the voltage VCCQ1 mainly to an I/O interface (such as the MIPI M-PHY 1251), and is in the range of about 1.7V to about 1.95V. The power supply voltage may be supplied to the components of UFS device 1200 through regulator 1260. For example, the regulator 1260 may be implemented as a set of cell regulators respectively connected to different ones of the above-described supply voltages.

While the inventive concept has been described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept.

This application claims priority to korean patent application No. 10-2020-.

Claims

1. A semiconductor package, comprising:

a plurality of lower pads;

an upper bonding pad;

a semiconductor chip including a chip pad and configured to transmit or receive a first signal through the chip pad;

a first wiring structure connecting the chip pad to a first lower pad among the plurality of lower pads; and

a second wiring structure connecting a second lower pad among the plurality of lower pads to the upper pad,

wherein the first and second lower pads are separated from each other by a minimum distance between the plurality of lower pads.

2. The semiconductor package of claim 1, further comprising:

a package substrate including the plurality of lower pads;

a molding layer formed on the package substrate, wherein the semiconductor chip is disposed in the molding layer, and the molding layer covers at least a portion of the semiconductor chip; and

an interposer formed on the molding layer and including the upper pad,

wherein the first wiring structure passes through the package substrate, an

The second wiring structure passes through the package substrate, the molding layer, and the interposer.

3. The semiconductor package of claim 2, wherein the second routing structure comprises:

an internal wiring formed in the package substrate;

a conductive connection through the molding layer; and

an interposer internal routing formed in the interposer.

4. The semiconductor package of claim 1, further comprising:

a first external connection terminal connected to the first lower pad; and

a second external connection terminal connected to the second lower pad,

wherein the first external connection terminal receives or transmits the first signal.

5. The semiconductor package according to claim 4, wherein the first external connection terminal and the second external connection terminal are connected to each other through a wiring structure formed in a substrate base, and

the second external connection terminal receives or transmits the first signal.

6. The semiconductor package according to claim 4, wherein the first external connection terminal is connected to a wiring structure formed in a substrate base, an

The second external connection terminal is not connected to the wiring structure.

7. The semiconductor package of claim 4, wherein the first signal is a reference clock signal, a reset signal, a data input signal, or a data output signal.

8. The semiconductor package of claim 7, wherein the semiconductor chip comprises a general purpose flash memory controller configured to exchange the first signal through the chip pad.

9. The semiconductor package of claim 1, wherein the plurality of lower pads are arranged in an orthogonal grid pattern.

10. The semiconductor package of claim 1, wherein the plurality of lower pads are arranged in rows and columns, and the rows of the plurality of lower pads are not aligned with each other.

11. A semiconductor package, comprising:

a substrate;

a first package including a plurality of lower pads, upper pads, and a first semiconductor chip and mounted on the substrate, the first semiconductor chip including a first chip pad and configured to transmit or receive a predefined signal through the first chip pad; and

a second package including a second semiconductor chip and mounted on the first package or the substrate, the second semiconductor chip controlled by the first semiconductor chip and configured to transmit or receive the predefined signal through a second chip pad of the second semiconductor chip,

wherein the first package comprises:

a first routing structure connecting the first chip pad to a first lower pad among the plurality of lower pads and transmitting the predefined signal; and

a second wiring structure connecting a second lower pad among the plurality of lower pads to the upper pad.

12. The semiconductor package of claim 11, wherein the first and second routing structures are separated from each other in the first package.

13. The semiconductor package of claim 11, wherein the substrate includes a first substrate routing structure connecting the first routing structure to the second chip pad of the second semiconductor chip when the second package is mounted on the substrate, and

the second wiring structure is not connected to the first substrate wiring structure.

14. The semiconductor package of claim 11, wherein the substrate includes a second substrate routing structure that electrically connects the first routing structure to the second routing structure when the second package is mounted on the first package.

15. The semiconductor package according to claim 14, wherein the second package comprises a plurality of external connection terminals electrically connected to chip pads of the second semiconductor chip, arranged according to a predefined ball pattern, and formed on a lower surface of the second package, wherein the chip pads comprise the second chip pads, and

the upper pads are arranged at an upper surface of the first package to correspond to the predefined ball map.

16. The semiconductor package of claim 11, wherein the first lower pad and the second lower pad are arranged by being separated from each other by a minimum distance between the plurality of lower pads.

17. The semiconductor package of claim 11, wherein the first semiconductor chip comprises a universal flash memory host, an

The second semiconductor chip includes a general flash memory device.

18. A semiconductor package, comprising:

a plurality of lower pads;

an upper bonding pad;

wherein the first and second lower pads are physically separated from each other in the semiconductor package, and the first and second wiring structures are physically separated from each other in the semiconductor package.

19. The semiconductor package of claim 18, further comprising:

a first external connection terminal connected to the first lower pad; and

a second external connection terminal connected to the second lower pad,

wherein the first external connection terminal is used for transmitting the first signal.

20. The semiconductor package of claim 18, further comprising:

a package substrate including the plurality of lower pads;

an interposer formed on the molding layer and including the upper pad,

wherein the first wiring structure passes through the package substrate, an